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GET /api/patches/19509/?format=api
{ "id": 19509, "url": "http://patches.dpdk.org/api/patches/19509/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1484637244-7548-11-git-send-email-jerin.jacob@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1484637244-7548-11-git-send-email-jerin.jacob@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1484637244-7548-11-git-send-email-jerin.jacob@caviumnetworks.com", "date": "2017-01-17T07:13:45", "name": "[dpdk-dev,v4,10/29] eal: introduce I/O device memory read/write operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "33e1afe7d6d1ac38d3649f8eeecf0df639ae3105", "submitter": { "id": 305, "url": "http://patches.dpdk.org/api/people/305/?format=api", "name": "Jerin Jacob", "email": "jerin.jacob@caviumnetworks.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1484637244-7548-11-git-send-email-jerin.jacob@caviumnetworks.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/19509/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/19509/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id CF135F94F;\n\tTue, 17 Jan 2017 08:15:24 +0100 (CET)", "from NAM03-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam03on0073.outbound.protection.outlook.com [104.47.42.73])\n\tby dpdk.org (Postfix) with ESMTP id 218D7F961\n\tfor <dev@dpdk.org>; Tue, 17 Jan 2017 08:15:22 +0100 (CET)", "from localhost.caveonetworks.com (111.93.218.67) by\n\tBY1PR0701MB1724.namprd07.prod.outlook.com (10.162.111.143) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.845.12;\n\tTue, 17 Jan 2017 07:15:16 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=RdpoeNlwxSm9NFdiPlUaqrzFGg9PNTtZOMNiYzEuxPc=;\n\tb=RyRUwpb4mhZY+BywRLdwIsiY9LMg7h68DKm/jYo1iiftnUSInYvyspEp3L1zns70KrAxUBrLSpGG7wmSpXIB799OF1gnGBWSUK7cHiwJaKkuoLjw+AudHwRje/r/wW2QosaPPRjZxg0C66jHFaTGWiETdFY5S9Ao6IU1Rnbv6aI=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Jerin.Jacob@cavium.com; ", "From": "Jerin Jacob <jerin.jacob@caviumnetworks.com>", "To": "<dev@dpdk.org>", "CC": "<konstantin.ananyev@intel.com>, <thomas.monjalon@6wind.com>,\n\t<bruce.richardson@intel.com>, <jianbo.liu@linaro.org>,\n\t<viktorin@rehivetech.com>, <santosh.shukla@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>", "Date": "Tue, 17 Jan 2017 12:43:45 +0530", "Message-ID": "<1484637244-7548-11-git-send-email-jerin.jacob@caviumnetworks.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1484637244-7548-1-git-send-email-jerin.jacob@caviumnetworks.com>", "References": "<1484212646-10338-1-git-send-email-jerin.jacob@caviumnetworks.com>\n\t<1484637244-7548-1-git-send-email-jerin.jacob@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[111.93.218.67]", "X-ClientProxiedBy": "PN1PR01CA0030.INDPRD01.PROD.OUTLOOK.COM (10.164.137.37) To\n\tBY1PR0701MB1724.namprd07.prod.outlook.com (10.162.111.143)", "X-MS-Office365-Filtering-Correlation-Id": "c4c745b2-3e10-44cf-dd83-08d43ea89843", "X-Microsoft-Antispam": "UriScan:; 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PCL:0;\n\tRULEID:(6040375)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6041248)(20161123562025)(20161123555025)(20161123564025)(20161123560025)(6072148);\n\tSRVR:BY1PR0701MB1724; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0701MB1724; ", "X-Forefront-PRVS": "01901B3451", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(4630300001)(6069001)(6009001)(7916002)(39450400003)(199003)(189002)(2906002)(4326007)(76506005)(107886002)(53416004)(189998001)(92566002)(106356001)(38730400001)(47776003)(25786008)(6486002)(54906002)(66066001)(6506006)(305945005)(7736002)(6512007)(5009440100003)(81156014)(3846002)(50226002)(5003940100001)(68736007)(4001430100002)(6116002)(76176999)(50986999)(2351001)(97736004)(81166006)(5660300001)(8676002)(105586002)(69596002)(42186005)(48376002)(6666003)(36756003)(33646002)(101416001)(2950100002)(6916009)(110136003)(50466002)(42882006)(30001)(7099028);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1724;\n\tH:localhost.caveonetworks.com; \n\tFPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Jan 2017 07:15:16.6851\n\t(UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY1PR0701MB1724", "Subject": "[dpdk-dev] [PATCH v4 10/29] eal: introduce I/O device memory\n\tread/write operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit introduces 8-bit, 16-bit, 32bit, 64bit I/O device\nmemory read/write operations along with the relaxed versions.\n\nThe weakly-ordered machine like ARM needs additional I/O barrier for\ndevice memory read/write access over PCI bus.\nBy introducing the eal abstraction for I/O device memory read/write access,\nThe drivers can access I/O device memory in architecture agnostic manner.\n\nThe relaxed version does not have additional I/O memory barrier, useful in\naccessing the device registers of integrated controllers which\nimplicitly strongly ordered with respect to memory access.\n\nSigned-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>\n---\n doc/api/doxy-api-index.md | 3 +-\n lib/librte_eal/common/Makefile | 3 +-\n lib/librte_eal/common/include/generic/rte_io.h | 263 +++++++++++++++++++++++++\n 3 files changed, 267 insertions(+), 2 deletions(-)\n create mode 100644 lib/librte_eal/common/include/generic/rte_io.h", "diff": "diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md\nindex d26d984..8b3b426 100644\n--- a/doc/api/doxy-api-index.md\n+++ b/doc/api/doxy-api-index.md\n@@ -71,7 +71,8 @@ There are many libraries, so their headers may be grouped by topics:\n [cache prefetch] (@ref rte_prefetch.h),\n [SIMD] (@ref rte_vect.h),\n [byte order] (@ref rte_byteorder.h),\n- [CPU flags] (@ref rte_cpuflags.h)\n+ [CPU flags] (@ref rte_cpuflags.h),\n+ [I/O access] (@ref rte_io.h)\n \n - **CPU multicore**:\n [interrupts] (@ref rte_interrupts.h),\ndiff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile\nindex 09a3d3a..b34dce9 100644\n--- a/lib/librte_eal/common/Makefile\n+++ b/lib/librte_eal/common/Makefile\n@@ -44,7 +44,8 @@ INC += rte_malloc.h rte_keepalive.h rte_time.h\n \n GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h\n GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h\n-GENERIC_INC += rte_vect.h\n+GENERIC_INC += rte_vect.h rte_io.h\n+\n # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk\n ARCH_DIR ?= $(RTE_ARCH)\n ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h))\ndiff --git a/lib/librte_eal/common/include/generic/rte_io.h b/lib/librte_eal/common/include/generic/rte_io.h\nnew file mode 100644\nindex 0000000..edfebf8\n--- /dev/null\n+++ b/lib/librte_eal/common/include/generic/rte_io.h\n@@ -0,0 +1,263 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2016 Cavium networks. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Cavium networks nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_IO_H_\n+#define _RTE_IO_H_\n+\n+/**\n+ * @file\n+ * I/O device memory operations\n+ *\n+ * This file defines the generic API for I/O device memory read/write operations\n+ */\n+\n+#include <stdint.h>\n+#include <rte_common.h>\n+#include <rte_atomic.h>\n+\n+#ifdef __DOXYGEN__\n+\n+/**\n+ * Read a 8-bit value from I/O device memory address *addr*.\n+ *\n+ * The relaxed version does not have additional I/O memory barrier, useful in\n+ * accessing the device registers of integrated controllers which implicitly\n+ * strongly ordered with respect to memory access.\n+ *\n+ * @param addr\n+ * I/O memory address to read the value from\n+ * @return\n+ * read value\n+ */\n+static inline uint8_t\n+rte_read8_relaxed(const volatile void *addr);\n+\n+/**\n+ * Read a 16-bit value from I/O device memory address *addr*.\n+ *\n+ * The relaxed version does not have additional I/O memory barrier, useful in\n+ * accessing the device registers of integrated controllers which implicitly\n+ * strongly ordered with respect to memory access.\n+ *\n+ * @param addr\n+ * I/O memory address to read the value from\n+ * @return\n+ * read value\n+ */\n+static inline uint16_t\n+rte_read16_relaxed(const volatile void *addr);\n+\n+/**\n+ * Read a 32-bit value from I/O device memory address *addr*.\n+ *\n+ * The relaxed version does not have additional I/O memory barrier, useful in\n+ * accessing the device registers of integrated controllers which implicitly\n+ * strongly ordered with respect to memory access.\n+ *\n+ * @param addr\n+ * I/O memory address to read the value from\n+ * @return\n+ * read value\n+ */\n+static inline uint32_t\n+rte_read32_relaxed(const volatile void *addr);\n+\n+/**\n+ * Read a 64-bit value from I/O device memory address *addr*.\n+ *\n+ * The relaxed version does not have additional I/O memory barrier, useful in\n+ * accessing the device registers of integrated controllers which implicitly\n+ * strongly ordered with respect to memory access.\n+ *\n+ * @param addr\n+ * I/O memory address to read the value from\n+ * @return\n+ * read value\n+ */\n+static inline uint64_t\n+rte_read64_relaxed(const volatile void *addr);\n+\n+/**\n+ * Write a 8-bit value to I/O device memory address *addr*.\n+ *\n+ * The relaxed version does not have additional I/O memory barrier, useful in\n+ * accessing the device registers of integrated controllers which implicitly\n+ * strongly ordered with respect to memory access.\n+ *\n+ * @param value\n+ * Value to write\n+ * @param addr\n+ * I/O memory address to write the value to\n+ */\n+\n+static inline void\n+rte_write8_relaxed(uint8_t value, volatile void *addr);\n+\n+/**\n+ * Write a 16-bit value to I/O device memory address *addr*.\n+ *\n+ * The relaxed version does not have additional I/O memory barrier, useful in\n+ * accessing the device registers of integrated controllers which implicitly\n+ * strongly ordered with respect to memory access.\n+ *\n+ * @param value\n+ * Value to write\n+ * @param addr\n+ * I/O memory address to write the value to\n+ */\n+static inline void\n+rte_write16_relaxed(uint16_t value, volatile void *addr);\n+\n+/**\n+ * Write a 32-bit value to I/O device memory address *addr*.\n+ *\n+ * The relaxed version does not have additional I/O memory barrier, useful in\n+ * accessing the device registers of integrated controllers which implicitly\n+ * strongly ordered with respect to memory access.\n+ *\n+ * @param value\n+ * Value to write\n+ * @param addr\n+ * I/O memory address to write the value to\n+ */\n+static inline void\n+rte_write32_relaxed(uint32_t value, volatile void *addr);\n+\n+/**\n+ * Write a 64-bit value to I/O device memory address *addr*.\n+ *\n+ * The relaxed version does not have additional I/O memory barrier, useful in\n+ * accessing the device registers of integrated controllers which implicitly\n+ * strongly ordered with respect to memory access.\n+ *\n+ * @param value\n+ * Value to write\n+ * @param addr\n+ * I/O memory address to write the value to\n+ */\n+static inline void\n+rte_write64_relaxed(uint64_t value, volatile void *addr);\n+\n+/**\n+ * Read a 8-bit value from I/O device memory address *addr*.\n+ *\n+ * @param addr\n+ * I/O memory address to read the value from\n+ * @return\n+ * read value\n+ */\n+static inline uint8_t\n+rte_read8(const volatile void *addr);\n+\n+/**\n+ * Read a 16-bit value from I/O device memory address *addr*.\n+ *\n+ *\n+ * @param addr\n+ * I/O memory address to read the value from\n+ * @return\n+ * read value\n+ */\n+static inline uint16_t\n+rte_read16(const volatile void *addr);\n+\n+/**\n+ * Read a 32-bit value from I/O device memory address *addr*.\n+ *\n+ * @param addr\n+ * I/O memory address to read the value from\n+ * @return\n+ * read value\n+ */\n+static inline uint32_t\n+rte_read32(const volatile void *addr);\n+\n+/**\n+ * Read a 64-bit value from I/O device memory address *addr*.\n+ *\n+ * @param addr\n+ * I/O memory address to read the value from\n+ * @return\n+ * read value\n+ */\n+static inline uint64_t\n+rte_read64(const volatile void *addr);\n+\n+/**\n+ * Write a 8-bit value to I/O device memory address *addr*.\n+ *\n+ * @param value\n+ * Value to write\n+ * @param addr\n+ * I/O memory address to write the value to\n+ */\n+\n+static inline void\n+rte_write8(uint8_t value, volatile void *addr);\n+\n+/**\n+ * Write a 16-bit value to I/O device memory address *addr*.\n+ *\n+ * @param value\n+ * Value to write\n+ * @param addr\n+ * I/O memory address to write the value to\n+ */\n+static inline void\n+rte_write16(uint16_t value, volatile void *addr);\n+\n+/**\n+ * Write a 32-bit value to I/O device memory address *addr*.\n+ *\n+ * @param value\n+ * Value to write\n+ * @param addr\n+ * I/O memory address to write the value to\n+ */\n+static inline void\n+rte_write32(uint32_t value, volatile void *addr);\n+\n+/**\n+ * Write a 64-bit value to I/O device memory address *addr*.\n+ *\n+ * @param value\n+ * Value to write\n+ * @param addr\n+ * I/O memory address to write the value to\n+ */\n+static inline void\n+rte_write64(uint64_t value, volatile void *addr);\n+\n+#endif /* __DOXYGEN__ */\n+\n+#endif /* _RTE_IO_H_ */\n", "prefixes": [ "dpdk-dev", "v4", "10/29" ] }