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GET /api/patches/193/?format=api
{ "id": 193, "url": "http://patches.dpdk.org/api/patches/193/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1408695969-9774-4-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1408695969-9774-4-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1408695969-9774-4-git-send-email-helin.zhang@intel.com", "date": "2014-08-22T08:26:07", "name": "[dpdk-dev,3/5] ixgbe: rework of updating/querying redirection table", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0a866d7810a3ac62a5484a3b0ce124e0942d23a4", "submitter": { "id": 14, "url": "http://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1408695969-9774-4-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/193/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/193/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<hzhan75@shecgisg004.sh.intel.com>", "Received": [ "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id 2EBC9B36F\n\tfor <dev@dpdk.org>; Fri, 22 Aug 2014 10:22:43 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga103.fm.intel.com with ESMTP; 22 Aug 2014 01:18:35 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 22 Aug 2014 01:22:29 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s7M8QLOd017804;\n\tFri, 22 Aug 2014 16:26:21 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s7M8QHm3009905; Fri, 22 Aug 2014 16:26:19 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s7M8QHOb009901; \n\tFri, 22 Aug 2014 16:26:17 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"4.97,862,1389772800\"; d=\"scan'208\";a=\"375656076\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 22 Aug 2014 16:26:07 +0800", "Message-Id": "<1408695969-9774-4-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "In-Reply-To": "<1408695969-9774-1-git-send-email-helin.zhang@intel.com>", "References": "<1408695969-9774-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 3/5] ixgbe: rework of updating/querying\n\tredirection table", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "X-List-Received-Date": "Fri, 22 Aug 2014 08:22:43 -0000" }, "content": "As ethdev has been changed to support multiple sizes\nof redirection table, the functions of updating/querying\nredirection table need to be reworked. In addition,\ngetting the redirection table size is supported in ops\nof 'dev_infos_get'.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nReviewed-by: Jijiang Liu <jijiang.liu@intel.com>\nReviewed-by: Cunming Liang <cunming.liang@intel.com>\nReviewed-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_ixgbe/ixgbe_ethdev.c | 136 +++++++++++++++++++++++-------------\n 1 file changed, 87 insertions(+), 49 deletions(-)", "diff": "diff --git a/lib/librte_pmd_ixgbe/ixgbe_ethdev.c b/lib/librte_pmd_ixgbe/ixgbe_ethdev.c\nindex 59122a1..4f036ec 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe_ethdev.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe_ethdev.c\n@@ -118,8 +118,9 @@ static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,\n \t\t\t\t\t uint8_t stat_idx,\n \t\t\t\t\t uint8_t is_rx);\n static void ixgbe_dev_info_get(struct rte_eth_dev *dev,\n-\t\t\t\tstruct rte_eth_dev_info *dev_info);\n-\n+\t\t\t struct rte_eth_dev_info *dev_info);\n+static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_eth_dev_info *dev_info);\n static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n \n static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,\n@@ -144,9 +145,11 @@ static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,\n static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,\n \t\tstruct rte_eth_pfc_conf *pfc_conf);\n static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n-\t\tstruct rte_eth_rss_reta *reta_conf);\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size);\n static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,\n-\t\tstruct rte_eth_rss_reta *reta_conf);\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size);\n static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);\n static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);\n static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);\n@@ -377,7 +380,7 @@ static struct eth_dev_ops ixgbevf_eth_dev_ops = {\n \t.stats_get = ixgbevf_dev_stats_get,\n \t.stats_reset = ixgbevf_dev_stats_reset,\n \t.dev_close = ixgbevf_dev_close,\n-\t.dev_infos_get = ixgbe_dev_info_get,\n+\t.dev_infos_get = ixgbevf_dev_info_get,\n \t.mtu_set = ixgbevf_dev_set_mtu,\n \t.vlan_filter_set = ixgbevf_vlan_filter_set,\n \t.vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,\n@@ -1948,6 +1951,35 @@ ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n \t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n \t\tDEV_TX_OFFLOAD_SCTP_CKSUM;\n+\tdev_info->reta_size = ETH_RSS_RETA_SIZE_128;\n+}\n+\n+static void\n+ixgbevf_dev_info_get(struct rte_eth_dev *dev,\n+\t\t struct rte_eth_dev_info *dev_info)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tdev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;\n+\tdev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;\n+\tdev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */\n+\tdev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */\n+\tdev_info->max_mac_addrs = hw->mac.num_rar_entries;\n+\tdev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;\n+\tdev_info->max_vfs = dev->pci_dev->max_vfs;\n+\tif (hw->mac.type == ixgbe_mac_82598EB)\n+\t\tdev_info->max_vmdq_pools = ETH_16_POOLS;\n+\telse\n+\t\tdev_info->max_vmdq_pools = ETH_64_POOLS;\n+\tdev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |\n+\t\t\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n+\tdev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |\n+\t\t\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_SCTP_CKSUM;\n }\n \n /* return 0 means link status changed, -1 means not changed */\n@@ -2624,38 +2656,41 @@ ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *p\n \n static int\n ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n-\t\t\t\tstruct rte_eth_rss_reta *reta_conf)\n+\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t uint16_t reta_size)\n {\n \tuint8_t i,j,mask;\n-\tuint32_t reta;\n+\tuint32_t reta, r;\n+\tuint16_t idx, shift;\n \tstruct ixgbe_hw *hw =\n \t\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n \tPMD_INIT_FUNC_TRACE();\n-\t/*\n-\t* Update Redirection Table RETA[n],n=0...31,The redirection table has\n-\t* 128-entries in 32 registers\n-\t */\n-\tfor(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n-\t\tif (i < ETH_RSS_RETA_NUM_ENTRIES/2)\n-\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n+\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < reta_size; i += 4) {\n+\t\tidx = i / RTE_BIT_WIDTH_64;\n+\t\tshift = i % RTE_BIT_WIDTH_64;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xf);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\t\tif (mask == 0xf)\n+\t\t\tr = 0;\n \t\telse\n-\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n-\t\t\t\t(i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);\n-\t\tif (mask != 0) {\n-\t\t\treta = 0;\n-\t\t\tif (mask != 0xF)\n-\t\t\t\treta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));\n-\n-\t\t\tfor (j = 0; j < 4; j++) {\n-\t\t\t\tif (mask & (0x1 << j)) {\n-\t\t\t\t\tif (mask != 0xF)\n-\t\t\t\t\t\treta &= ~(0xFF << 8 * j);\n-\t\t\t\t\treta |= reta_conf->reta[i + j] << 8*j;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);\n+\t\t\tr = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));\n+\t\tfor (j = 0, reta = 0; j < 4; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\treta |= reta_conf[idx].reta[shift + j] <<\n+\t\t\t\t\t\t\t(CHAR_BIT * j);\n+\t\t\telse\n+\t\t\t\treta |= r & (0xff << (CHAR_BIT * j));\n \t\t}\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);\n \t}\n \n \treturn 0;\n@@ -2663,32 +2698,35 @@ ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n \n static int\n ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,\n-\t\t\t\tstruct rte_eth_rss_reta *reta_conf)\n+\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t uint16_t reta_size)\n {\n-\tuint8_t i,j,mask;\n+\tuint8_t i, j, mask;\n \tuint32_t reta;\n+\tuint16_t idx, shift;\n \tstruct ixgbe_hw *hw =\n \t\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n \tPMD_INIT_FUNC_TRACE();\n-\t/*\n-\t * Read Redirection Table RETA[n],n=0...31,The redirection table has\n-\t * 128-entries in 32 registers\n-\t */\n-\tfor(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n-\t\tif (i < ETH_RSS_RETA_NUM_ENTRIES/2)\n-\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n-\t\telse\n-\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n-\t\t\t\t(i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);\n-\n-\t\tif (mask != 0) {\n-\t\t\treta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));\n-\t\t\tfor (j = 0; j < 4; j++) {\n-\t\t\t\tif (mask & (0x1 << j))\n-\t\t\t\t\treta_conf->reta[i + j] =\n-\t\t\t\t\t\t(uint8_t)((reta >> 8 * j) & 0xFF);\n-\t\t\t}\n+\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < ETH_RSS_RETA_SIZE_128; i += 4) {\n+\t\tidx = i / RTE_BIT_WIDTH_64;\n+\t\tshift = i % RTE_BIT_WIDTH_64;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xf);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\n+\t\treta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\treta_conf[idx].reta[shift + j] =\n+\t\t\t\t\t((reta >> (CHAR_BIT * j)) & 0xff);\n \t\t}\n \t}\n \n", "prefixes": [ "dpdk-dev", "3/5" ] }