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{
    "id": 191,
    "url": "http://patches.dpdk.org/api/patches/191/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1408695969-9774-2-git-send-email-helin.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1408695969-9774-2-git-send-email-helin.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1408695969-9774-2-git-send-email-helin.zhang@intel.com",
    "date": "2014-08-22T08:26:05",
    "name": "[dpdk-dev,1/5] ethdev: support of multiple sizes of redirection table",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "035dde44015d072a8b60fab37f0913ba1d0b200c",
    "submitter": {
        "id": 14,
        "url": "http://patches.dpdk.org/api/people/14/?format=api",
        "name": "Zhang, Helin",
        "email": "helin.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1408695969-9774-2-git-send-email-helin.zhang@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/191/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/191/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<hzhan75@shecgisg004.sh.intel.com>",
        "Received": [
            "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id C6F03590C\n\tfor <dev@dpdk.org>; Fri, 22 Aug 2014 10:22:39 +0200 (CEST)",
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            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s7M8QCDw009887; \n\tFri, 22 Aug 2014 16:26:12 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"4.97,862,1389772800\"; d=\"scan'208\";a=\"375656050\"",
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Fri, 22 Aug 2014 16:26:05 +0800",
        "Message-Id": "<1408695969-9774-2-git-send-email-helin.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.7.0.7",
        "In-Reply-To": "<1408695969-9774-1-git-send-email-helin.zhang@intel.com>",
        "References": "<1408695969-9774-1-git-send-email-helin.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 1/5] ethdev: support of multiple sizes of\n\tredirection table",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
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        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
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        "X-List-Received-Date": "Fri, 22 Aug 2014 08:22:40 -0000"
    },
    "content": "To support different sizes of redirection table,\n* 'struct rte_eth_rss_reta' has been redefined.\n* New element of 'reta_size' is added into\n  'struct rte_eth_dev_info'.\n* New parameter of 'redirection table size' is\n  required for updating/querying redirection\n  table entries.\n* Interfaces of updating/querying redirection\n  table entries have been reworked to support\n  multiple sizes.\nCurrently the supported redirection table sizes\nare 64, 128 and 512 entries, according to the\nhardware specifications.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nReviewed-by: Jijiang Liu <jijiang.liu@intel.com>\nReviewed-by: Cunming Liang <cunming.liang@intel.com>\nReviewed-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n lib/librte_ether/rte_ethdev.c | 116 ++++++++++++++++++++++++++----------------\n lib/librte_ether/rte_ethdev.h |  43 ++++++++++------\n 2 files changed, 99 insertions(+), 60 deletions(-)",
    "diff": "diff --git a/lib/librte_ether/rte_ethdev.c b/lib/librte_ether/rte_ethdev.c\nindex fd1010a..3b483c4 100644\n--- a/lib/librte_ether/rte_ethdev.c\n+++ b/lib/librte_ether/rte_ethdev.c\n@@ -1780,78 +1780,104 @@ rte_eth_dev_priority_flow_ctrl_set(uint8_t port_id, struct rte_eth_pfc_conf *pfc\n \treturn (-ENOTSUP);\n }\n \n-int\n-rte_eth_dev_rss_reta_update(uint8_t port_id, struct rte_eth_rss_reta *reta_conf)\n+static inline int\n+rte_eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size)\n {\n-\tstruct rte_eth_dev *dev;\n-\tuint16_t max_rxq;\n-\tuint8_t i,j;\n+\tuint16_t i, num = reta_size / RTE_BIT_WIDTH_64;\n \n-\tif (port_id >= nb_ports) {\n-\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%d\\n\", port_id);\n-\t\treturn (-ENODEV);\n-\t}\n+\tif (!reta_conf)\n+\t\treturn -EINVAL;\n \n-\t/* Invalid mask bit(s) setting */\n-\tif ((reta_conf->mask_lo == 0) && (reta_conf->mask_hi == 0)) {\n-\t\tPMD_DEBUG_TRACE(\"Invalid update mask bits for port=%d\\n\",port_id);\n-\t\treturn (-EINVAL);\n+\tfor (i = 0; i < num; i++) {\n+\t\tif (reta_conf[i].mask)\n+\t\t\treturn 0;\n \t}\n \n-\tdev = &rte_eth_devices[port_id];\n-\tmax_rxq = (dev->data->nb_rx_queues <= ETH_RSS_RETA_MAX_QUEUE) ?\n-\t\tdev->data->nb_rx_queues : ETH_RSS_RETA_MAX_QUEUE;\n-\tif (reta_conf->mask_lo != 0) {\n-\t\tfor (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES/2; i++) {\n-\t\t\tif ((reta_conf->mask_lo & (1ULL << i)) &&\n-\t\t\t\t(reta_conf->reta[i] >= max_rxq)) {\n-\t\t\t\tPMD_DEBUG_TRACE(\"RETA hash index output\"\n-\t\t\t\t\t\"configration for port=%d,invalid\"\n-\t\t\t\t\t\"queue=%d\\n\",port_id,reta_conf->reta[i]);\n+\treturn -EINVAL;\n+}\n \n-\t\t\t\treturn (-EINVAL);\n-\t\t\t}\n+static inline int\n+rte_eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t uint16_t reta_size,\n+\t\t\t uint8_t max_rxq)\n+{\n+\tuint16_t i, idx, shift;\n+\n+\tif (!reta_conf)\n+\t\treturn -EINVAL;\n+\n+\tif (max_rxq == 0) {\n+\t\tPMD_DEBUG_TRACE(\"No receive queue is available\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < reta_size; i++) {\n+\t\tidx = i / RTE_BIT_WIDTH_64;\n+\t\tshift = i % RTE_BIT_WIDTH_64;\n+\t\tif ((reta_conf[idx].mask & (0x1 << shift)) &&\n+\t\t\t(reta_conf[idx].reta[shift] >= max_rxq)) {\n+\t\t\tPMD_DEBUG_TRACE(\"reta_conf[%u]->reta[%u]: %u exceeds \"\n+\t\t\t\t\"the maximum rxq index: %u\\n\", idx, shift,\n+\t\t\t\treta_conf[idx].reta[shift], max_rxq);\n+\t\t\treturn -EINVAL;\n \t\t}\n \t}\n \n-\tif (reta_conf->mask_hi != 0) {\n-\t\tfor (i = 0; i< ETH_RSS_RETA_NUM_ENTRIES/2; i++) {\n-\t\t\tj = (uint8_t)(i + ETH_RSS_RETA_NUM_ENTRIES/2);\n+\treturn 0;\n+}\n \n-\t\t\t/* Check if the max entry >= 128 */\n-\t\t\tif ((reta_conf->mask_hi & (1ULL << i)) &&\n-\t\t\t\t(reta_conf->reta[j] >= max_rxq)) {\n-\t\t\t\tPMD_DEBUG_TRACE(\"RETA hash index output\"\n-\t\t\t\t\t\"configration for port=%d,invalid\"\n-\t\t\t\t\t\"queue=%d\\n\",port_id,reta_conf->reta[j]);\n+int\n+rte_eth_dev_rss_reta_update(uint8_t port_id,\n+\t\t\t    struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t    uint16_t reta_size)\n+{\n+\tstruct rte_eth_dev *dev;\n+\tint ret;\n \n-\t\t\t\treturn (-EINVAL);\n-\t\t\t}\n-\t\t}\n+\tif (port_id >= nb_ports) {\n+\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%d\\n\", port_id);\n+\t\treturn -ENODEV;\n \t}\n \n+\t/* Check mask bits */\n+\tret = rte_eth_check_reta_mask(reta_conf, reta_size);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tdev = &rte_eth_devices[port_id];\n+\n+\t/* Check entry value */\n+\tret = rte_eth_check_reta_entry(reta_conf, reta_size,\n+\t\t\t\tdev->data->nb_rx_queues);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n \tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_update, -ENOTSUP);\n-\treturn (*dev->dev_ops->reta_update)(dev, reta_conf);\n+\treturn (*dev->dev_ops->reta_update)(dev, reta_conf, reta_size);\n }\n \n int\n-rte_eth_dev_rss_reta_query(uint8_t port_id, struct rte_eth_rss_reta *reta_conf)\n+rte_eth_dev_rss_reta_query(uint8_t port_id,\n+\t\t\t   struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t   uint16_t reta_size)\n {\n \tstruct rte_eth_dev *dev;\n+\tint ret;\n \n \tif (port_id >= nb_ports) {\n \t\tPMD_DEBUG_TRACE(\"Invalid port_id=%d\\n\", port_id);\n-\t\treturn (-ENODEV);\n+\t\treturn -ENODEV;\n \t}\n \n-\tif((reta_conf->mask_lo == 0) && (reta_conf->mask_hi == 0)) {\n-\t\tPMD_DEBUG_TRACE(\"Invalid update mask bits for the port=%d\\n\",port_id);\n-\t\treturn (-EINVAL);\n-\t}\n+\t/* Check mask bits */\n+\tret = rte_eth_check_reta_mask(reta_conf, reta_size);\n+\tif (ret < 0)\n+\t\treturn ret;\n \n \tdev = &rte_eth_devices[port_id];\n \tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_query, -ENOTSUP);\n-\treturn (*dev->dev_ops->reta_query)(dev, reta_conf);\n+\treturn (*dev->dev_ops->reta_query)(dev, reta_conf, reta_size);\n }\n \n int\ndiff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.h\nindex 50df654..7ea901e 100644\n--- a/lib/librte_ether/rte_ethdev.h\n+++ b/lib/librte_ether/rte_ethdev.h\n@@ -426,8 +426,11 @@ struct rte_eth_rss_conf {\n \t\tETH_RSS_L2_PAYLOAD)\n \n /* Definitions used for redirection table entry size */\n-#define ETH_RSS_RETA_NUM_ENTRIES 128\n-#define ETH_RSS_RETA_MAX_QUEUE   16\n+#define ETH_RSS_RETA_SIZE_64  64\n+#define ETH_RSS_RETA_SIZE_128 128\n+#define ETH_RSS_RETA_SIZE_512 512\n+\n+#define RTE_BIT_WIDTH_64 (CHAR_BIT * sizeof(uint64_t))\n \n /* Definitions used for VMDQ and DCB functionality */\n #define ETH_VMDQ_MAX_VLAN_FILTERS   64 /**< Maximum nb. of VMDQ vlan filters. */\n@@ -491,15 +494,15 @@ struct rte_eth_vmdq_mirror_conf {\n };\n \n /**\n- * A structure used to configure Redirection Table of  the Receive Side\n- * Scaling (RSS) feature of an Ethernet port.\n+ * A structure used to configure 64 entries of Redirection Table of the\n+ * Receive Side Scaling (RSS) feature of an Ethernet port. To configure\n+ * more than 64 entries supported by hardware, an array of this structure\n+ * is needed.\n  */\n-struct rte_eth_rss_reta {\n-\t/** First 64 mask bits indicate which entry(s) need to updated/queried. */\n-\tuint64_t mask_lo;\n-\t/** Second 64 mask bits indicate which entry(s) need to updated/queried. */\n-\tuint64_t mask_hi;\n-\tuint8_t reta[ETH_RSS_RETA_NUM_ENTRIES];  /**< 128 RETA entries*/\n+struct rte_eth_rss_reta_entry64 {\n+\tuint64_t mask;\n+\t/**< Mask bits indicate which entries need to be updated/queried. */\n+\tuint8_t reta[RTE_BIT_WIDTH_64]; /**< 64 redirection table entries. */\n };\n \n /**\n@@ -906,6 +909,8 @@ struct rte_eth_dev_info {\n \tuint16_t max_vmdq_pools; /**< Maximum number of VMDq pools. */\n \tuint32_t rx_offload_capa; /**< Device RX offload capabilities. */\n \tuint32_t tx_offload_capa; /**< Device TX offload capabilities. */\n+\tuint16_t reta_size;\n+\t/**< Device redirection table size, the total number of entries. */\n };\n \n struct rte_eth_dev;\n@@ -1158,11 +1163,13 @@ typedef int (*priority_flow_ctrl_set_t)(struct rte_eth_dev *dev,\n /**< @internal Setup priority flow control parameter on an Ethernet device */\n \n typedef int (*reta_update_t)(struct rte_eth_dev *dev,\n-\t\t\t\tstruct rte_eth_rss_reta *reta_conf);\n+\t\t\t     struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t     uint16_t reta_size);\n /**< @internal Update RSS redirection table on an Ethernet device */\n \n typedef int (*reta_query_t)(struct rte_eth_dev *dev,\n-\t\t\t\tstruct rte_eth_rss_reta *reta_conf);\n+\t\t\t    struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t    uint16_t reta_size);\n /**< @internal Query RSS redirection table on an Ethernet device */\n \n typedef int (*rss_hash_update_t)(struct rte_eth_dev *dev,\n@@ -2839,14 +2846,17 @@ int rte_eth_dev_mac_addr_remove(uint8_t port, struct ether_addr *mac_addr);\n  * @param port\n  *   The port identifier of the Ethernet device.\n  * @param reta_conf\n- *    RETA to update.\n+ *   RETA to update.\n+ * @param reta_size\n+ *   Redirection table size.\n  * @return\n  *   - (0) if successful.\n  *   - (-ENOTSUP) if hardware doesn't support.\n  *   - (-EINVAL) if bad parameter.\n  */\n int rte_eth_dev_rss_reta_update(uint8_t port,\n-\t\t\tstruct rte_eth_rss_reta *reta_conf);\n+\t\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t\tuint16_t reta_size);\n \n  /**\n  * Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device.\n@@ -2855,13 +2865,16 @@ int rte_eth_dev_rss_reta_update(uint8_t port,\n  *   The port identifier of the Ethernet device.\n  * @param reta_conf\n  *   RETA to query.\n+ * @param reta_size\n+ *   Redirection table size.\n  * @return\n  *   - (0) if successful.\n  *   - (-ENOTSUP) if hardware doesn't support.\n  *   - (-EINVAL) if bad parameter.\n  */\n int rte_eth_dev_rss_reta_query(uint8_t port,\n-\t\t\tstruct rte_eth_rss_reta *reta_conf);\n+\t\t\t       struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t       uint16_t reta_size);\n \n  /**\n  * Updates unicast hash table for receiving packet with the given destination\n",
    "prefixes": [
        "dpdk-dev",
        "1/5"
    ]
}