Patch Detail

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{
    "id": 18439,
    "url": "http://patches.dpdk.org/api/patches/18439/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20161222201700.20020-4-akhil.goyal@nxp.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
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        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
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    "msgid": "<20161222201700.20020-4-akhil.goyal@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20161222201700.20020-4-akhil.goyal@nxp.com",
    "date": "2016-12-22T20:16:52",
    "name": "[dpdk-dev,v2,03/11] crypto/dpaa2_sec/hw: Sample descriptors for NXP DPAA2 SEC operations.",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "ec5256a9fdd48f7032c29c8bc8009bfe0efe9ab4",
    "submitter": {
        "id": 517,
        "url": "http://patches.dpdk.org/api/people/517/?format=api",
        "name": "Akhil Goyal",
        "email": "akhil.goyal@nxp.com"
    },
    "delegate": {
        "id": 22,
        "url": "http://patches.dpdk.org/api/users/22/?format=api",
        "username": "pdelarag",
        "first_name": "Pablo",
        "last_name": "de Lara Guarch",
        "email": "pablo.de.lara.guarch@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20161222201700.20020-4-akhil.goyal@nxp.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/18439/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/18439/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Akhil Goyal <akhil.goyal@nxp.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<thomas.monjalon@6wind.com>, <declan.doherty@intel.com>,\n\t<pablo.de.lara.guarch@intel.com>, <hemant.agrawal@nxp.com>,\n\t<john.mcnamara@intel.com>, <nhorman@tuxdriver.com>, Akhil Goyal\n\t<akhil.goyal@nxp.com>, Horia Geanta Neag <horia.geanta@nxp.com>",
        "Date": "Fri, 23 Dec 2016 01:46:52 +0530",
        "Message-ID": "<20161222201700.20020-4-akhil.goyal@nxp.com>",
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        "In-Reply-To": "<20161222201700.20020-1-akhil.goyal@nxp.com>",
        "References": "<20161205125540.6419-1-akhil.goyal@nxp.com>\n\t<20161222201700.20020-1-akhil.goyal@nxp.com>",
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        "Subject": "[dpdk-dev] [PATCH v2 03/11] crypto/dpaa2_sec/hw: Sample descriptors\n\tfor NXP DPAA2 SEC operations.",
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        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "algo.h provides APIs for constructing non-protocol offload SEC\n\tdescriptors like hmac, blkciphers etc.\nipsec.h provides APIs for IPSEC offload descriptors.\ncommon.h is a common helper file which for all desccriptors\n\nIn future, additional algorithms' descriptors(PDCP etc.) will be\nadded in the desc/\n\nSigned-off-by: Horia Geanta Neag <horia.geanta@nxp.com>\nAcked-by: Akhil Goyal <akhil.goyal@nxp.com>\n---\n drivers/crypto/dpaa2_sec/hw/desc.h        | 2570 +++++++++++++++++++++++++++++\n drivers/crypto/dpaa2_sec/hw/desc/algo.h   |  424 +++++\n drivers/crypto/dpaa2_sec/hw/desc/common.h |   96 ++\n drivers/crypto/dpaa2_sec/hw/desc/ipsec.h  | 1502 +++++++++++++++++\n 4 files changed, 4592 insertions(+)\n create mode 100644 drivers/crypto/dpaa2_sec/hw/desc.h\n create mode 100644 drivers/crypto/dpaa2_sec/hw/desc/algo.h\n create mode 100644 drivers/crypto/dpaa2_sec/hw/desc/common.h\n create mode 100644 drivers/crypto/dpaa2_sec/hw/desc/ipsec.h",
    "diff": "diff --git a/drivers/crypto/dpaa2_sec/hw/desc.h b/drivers/crypto/dpaa2_sec/hw/desc.h\nnew file mode 100644\nindex 0000000..b77fb39\n--- /dev/null\n+++ b/drivers/crypto/dpaa2_sec/hw/desc.h\n@@ -0,0 +1,2570 @@\n+/*\n+ * SEC descriptor composition header.\n+ * Definitions to support SEC descriptor instruction generation\n+ *\n+ * Copyright 2008-2016 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier: BSD-3-Clause or GPL-2.0+\n+ */\n+\n+#ifndef __RTA_DESC_H__\n+#define __RTA_DESC_H__\n+\n+/* hw/compat.h is not delivered in kernel */\n+#ifndef __KERNEL__\n+#include \"hw/compat.h\"\n+#endif\n+\n+/* Max size of any SEC descriptor in 32-bit words, inclusive of header */\n+#define MAX_CAAM_DESCSIZE\t64\n+\n+#define CAAM_CMD_SZ sizeof(uint32_t)\n+#define CAAM_PTR_SZ sizeof(dma_addr_t)\n+#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)\n+#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)\n+\n+/* Block size of any entity covered/uncovered with a KEK/TKEK */\n+#define KEK_BLOCKSIZE\t\t16\n+\n+/*\n+ * Supported descriptor command types as they show up\n+ * inside a descriptor command word.\n+ */\n+#define CMD_SHIFT\t\t27\n+#define CMD_MASK\t\t(0x1f << CMD_SHIFT)\n+\n+#define CMD_KEY\t\t\t(0x00 << CMD_SHIFT)\n+#define CMD_SEQ_KEY\t\t(0x01 << CMD_SHIFT)\n+#define CMD_LOAD\t\t(0x02 << CMD_SHIFT)\n+#define CMD_SEQ_LOAD\t\t(0x03 << CMD_SHIFT)\n+#define CMD_FIFO_LOAD\t\t(0x04 << CMD_SHIFT)\n+#define CMD_SEQ_FIFO_LOAD\t(0x05 << CMD_SHIFT)\n+#define CMD_MOVEDW\t\t(0x06 << CMD_SHIFT)\n+#define CMD_MOVEB\t\t(0x07 << CMD_SHIFT)\n+#define CMD_STORE\t\t(0x0a << CMD_SHIFT)\n+#define CMD_SEQ_STORE\t\t(0x0b << CMD_SHIFT)\n+#define CMD_FIFO_STORE\t\t(0x0c << CMD_SHIFT)\n+#define CMD_SEQ_FIFO_STORE\t(0x0d << CMD_SHIFT)\n+#define CMD_MOVE_LEN\t\t(0x0e << CMD_SHIFT)\n+#define CMD_MOVE\t\t(0x0f << CMD_SHIFT)\n+#define CMD_OPERATION\t\t((uint32_t)(0x10 << CMD_SHIFT))\n+#define CMD_SIGNATURE\t\t((uint32_t)(0x12 << CMD_SHIFT))\n+#define CMD_JUMP\t\t((uint32_t)(0x14 << CMD_SHIFT))\n+#define CMD_MATH\t\t((uint32_t)(0x15 << CMD_SHIFT))\n+#define CMD_DESC_HDR\t\t((uint32_t)(0x16 << CMD_SHIFT))\n+#define CMD_SHARED_DESC_HDR\t((uint32_t)(0x17 << CMD_SHIFT))\n+#define CMD_MATHI               ((uint32_t)(0x1d << CMD_SHIFT))\n+#define CMD_SEQ_IN_PTR\t\t((uint32_t)(0x1e << CMD_SHIFT))\n+#define CMD_SEQ_OUT_PTR\t\t((uint32_t)(0x1f << CMD_SHIFT))\n+\n+/* General-purpose class selector for all commands */\n+#define CLASS_SHIFT\t\t25\n+#define CLASS_MASK\t\t(0x03 << CLASS_SHIFT)\n+\n+#define CLASS_NONE\t\t(0x00 << CLASS_SHIFT)\n+#define CLASS_1\t\t\t(0x01 << CLASS_SHIFT)\n+#define CLASS_2\t\t\t(0x02 << CLASS_SHIFT)\n+#define CLASS_BOTH\t\t(0x03 << CLASS_SHIFT)\n+\n+/* ICV Check bits for Algo Operation command */\n+#define ICV_CHECK_DISABLE\t0\n+#define ICV_CHECK_ENABLE\t1\n+\n+\n+/* Encap Mode check bits for Algo Operation command */\n+#define DIR_ENC\t\t\t1\n+#define DIR_DEC\t\t\t0\n+\n+/*\n+ * Descriptor header command constructs\n+ * Covers shared, job, and trusted descriptor headers\n+ */\n+\n+/*\n+ * Extended Job Descriptor Header\n+ */\n+#define HDR_EXT\t\t\tBIT(24)\n+\n+/*\n+ * Read input frame as soon as possible (SHR HDR)\n+ */\n+#define HDR_RIF\t\t\tBIT(25)\n+\n+/*\n+ * Require SEQ LIODN to be the Same  (JOB HDR)\n+ */\n+#define HDR_RSLS\t\tBIT(25)\n+\n+/*\n+ * Do Not Run - marks a descriptor not executable if there was\n+ * a preceding error somewhere\n+ */\n+#define HDR_DNR\t\t\tBIT(24)\n+\n+/*\n+ * ONE - should always be set. Combination of ONE (always\n+ * set) and ZRO (always clear) forms an endianness sanity check\n+ */\n+#define HDR_ONE\t\t\tBIT(23)\n+#define HDR_ZRO\t\t\tBIT(15)\n+\n+/* Start Index or SharedDesc Length */\n+#define HDR_START_IDX_SHIFT\t16\n+#define HDR_START_IDX_MASK\t(0x3f << HDR_START_IDX_SHIFT)\n+\n+/* If shared descriptor header, 6-bit length */\n+#define HDR_DESCLEN_SHR_MASK\t0x3f\n+\n+/* If non-shared header, 7-bit length */\n+#define HDR_DESCLEN_MASK\t0x7f\n+\n+/* This is a TrustedDesc (if not SharedDesc) */\n+#define HDR_TRUSTED\t\tBIT(14)\n+\n+/* Make into TrustedDesc (if not SharedDesc) */\n+#define HDR_MAKE_TRUSTED\tBIT(13)\n+\n+/* Clear Input FiFO (if SharedDesc) */\n+#define HDR_CLEAR_IFIFO\t\tBIT(13)\n+\n+/* Save context if self-shared (if SharedDesc) */\n+#define HDR_SAVECTX\t\tBIT(12)\n+\n+/* Next item points to SharedDesc */\n+#define HDR_SHARED\t\tBIT(12)\n+\n+/*\n+ * Reverse Execution Order - execute JobDesc first, then\n+ * execute SharedDesc (normally SharedDesc goes first).\n+ */\n+#define HDR_REVERSE\t\tBIT(11)\n+\n+/* Propagate DNR property to SharedDesc */\n+#define HDR_PROP_DNR\t\tBIT(11)\n+\n+/* DECO Select Valid */\n+#define HDR_EXT_DSEL_VALID\tBIT(7)\n+\n+/* Fake trusted descriptor */\n+#define HDR_EXT_FTD\t\tBIT(8)\n+\n+/* JobDesc/SharedDesc share property */\n+#define HDR_SD_SHARE_SHIFT\t8\n+#define HDR_SD_SHARE_MASK\t(0x03 << HDR_SD_SHARE_SHIFT)\n+#define HDR_JD_SHARE_SHIFT\t8\n+#define HDR_JD_SHARE_MASK\t(0x07 << HDR_JD_SHARE_SHIFT)\n+\n+#define HDR_SHARE_NEVER\t\t(0x00 << HDR_SD_SHARE_SHIFT)\n+#define HDR_SHARE_WAIT\t\t(0x01 << HDR_SD_SHARE_SHIFT)\n+#define HDR_SHARE_SERIAL\t(0x02 << HDR_SD_SHARE_SHIFT)\n+#define HDR_SHARE_ALWAYS\t(0x03 << HDR_SD_SHARE_SHIFT)\n+#define HDR_SHARE_DEFER\t\t(0x04 << HDR_SD_SHARE_SHIFT)\n+\n+/* JobDesc/SharedDesc descriptor length */\n+#define HDR_JD_LENGTH_MASK\t0x7f\n+#define HDR_SD_LENGTH_MASK\t0x3f\n+\n+/*\n+ * KEY/SEQ_KEY Command Constructs\n+ */\n+\n+/* Key Destination Class: 01 = Class 1, 02 - Class 2 */\n+#define KEY_DEST_CLASS_SHIFT\t25\n+#define KEY_DEST_CLASS_MASK\t(0x03 << KEY_DEST_CLASS_SHIFT)\n+#define KEY_DEST_CLASS1\t\t(1 << KEY_DEST_CLASS_SHIFT)\n+#define KEY_DEST_CLASS2\t\t(2 << KEY_DEST_CLASS_SHIFT)\n+\n+/* Scatter-Gather Table/Variable Length Field */\n+#define KEY_SGF\t\t\tBIT(24)\n+#define KEY_VLF\t\t\tBIT(24)\n+\n+/* Immediate - Key follows command in the descriptor */\n+#define KEY_IMM\t\t\tBIT(23)\n+\n+/*\n+ * Already in Input Data FIFO - the Input Data Sequence is not read, since it is\n+ * already in the Input Data FIFO.\n+ */\n+#define KEY_AIDF\t\tBIT(23)\n+\n+/*\n+ * Encrypted - Key is encrypted either with the KEK, or\n+ * with the TDKEK if this descriptor is trusted\n+ */\n+#define KEY_ENC\t\t\tBIT(22)\n+\n+/*\n+ * No Write Back - Do not allow key to be FIFO STOREd\n+ */\n+#define KEY_NWB\t\t\tBIT(21)\n+\n+/*\n+ * Enhanced Encryption of Key\n+ */\n+#define KEY_EKT\t\t\tBIT(20)\n+\n+/*\n+ * Encrypted with Trusted Key\n+ */\n+#define KEY_TK\t\t\tBIT(15)\n+\n+/*\n+ * Plaintext Store\n+ */\n+#define KEY_PTS\t\t\tBIT(14)\n+\n+/*\n+ * KDEST - Key Destination: 0 - class key register,\n+ * 1 - PKHA 'e', 2 - AFHA Sbox, 3 - MDHA split key\n+ */\n+#define KEY_DEST_SHIFT\t\t16\n+#define KEY_DEST_MASK\t\t(0x03 << KEY_DEST_SHIFT)\n+\n+#define KEY_DEST_CLASS_REG\t(0x00 << KEY_DEST_SHIFT)\n+#define KEY_DEST_PKHA_E\t\t(0x01 << KEY_DEST_SHIFT)\n+#define KEY_DEST_AFHA_SBOX\t(0x02 << KEY_DEST_SHIFT)\n+#define KEY_DEST_MDHA_SPLIT\t(0x03 << KEY_DEST_SHIFT)\n+\n+/* Length in bytes */\n+#define KEY_LENGTH_MASK\t\t0x000003ff\n+\n+/*\n+ * LOAD/SEQ_LOAD/STORE/SEQ_STORE Command Constructs\n+ */\n+\n+/*\n+ * Load/Store Destination: 0 = class independent CCB,\n+ * 1 = class 1 CCB, 2 = class 2 CCB, 3 = DECO\n+ */\n+#define LDST_CLASS_SHIFT\t25\n+#define LDST_CLASS_MASK\t\t(0x03 << LDST_CLASS_SHIFT)\n+#define LDST_CLASS_IND_CCB\t(0x00 << LDST_CLASS_SHIFT)\n+#define LDST_CLASS_1_CCB\t(0x01 << LDST_CLASS_SHIFT)\n+#define LDST_CLASS_2_CCB\t(0x02 << LDST_CLASS_SHIFT)\n+#define LDST_CLASS_DECO\t\t(0x03 << LDST_CLASS_SHIFT)\n+\n+/* Scatter-Gather Table/Variable Length Field */\n+#define LDST_SGF\t\tBIT(24)\n+#define LDST_VLF\t\tBIT(24)\n+\n+/* Immediate - Key follows this command in descriptor */\n+#define LDST_IMM_MASK\t\t1\n+#define LDST_IMM_SHIFT\t\t23\n+#define LDST_IMM\t\tBIT(23)\n+\n+/* SRC/DST - Destination for LOAD, Source for STORE */\n+#define LDST_SRCDST_SHIFT\t16\n+#define LDST_SRCDST_MASK\t(0x7f << LDST_SRCDST_SHIFT)\n+\n+#define LDST_SRCDST_BYTE_CONTEXT\t(0x20 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_BYTE_KEY\t\t(0x40 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_BYTE_INFIFO\t\t(0x7c << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_BYTE_OUTFIFO\t(0x7e << LDST_SRCDST_SHIFT)\n+\n+#define LDST_SRCDST_WORD_MODE_REG\t(0x00 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECO_JQCTRL\t(0x00 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_KEYSZ_REG\t(0x01 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECO_JQDAR\t(0x01 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DATASZ_REG\t(0x02 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECO_STAT\t(0x02 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_ICVSZ_REG\t(0x03 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_BYTE_DCHKSM\t\t(0x03 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_PID\t\t(0x04 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_CHACTRL\t(0x06 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECOCTRL\t(0x06 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_IRQCTRL\t(0x07 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECO_PCLOVRD\t(0x07 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_CLRW\t\t(0x08 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECO_MATH0\t(0x08 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_STAT\t\t(0x09 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECO_MATH1\t(0x09 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECO_MATH2\t(0x0a << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECO_AAD_SZ\t(0x0b << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DECO_MATH3\t(0x0b << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_CLASS1_IV_SZ\t(0x0c << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_ALTDS_CLASS1\t(0x0f << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_PKHA_A_SZ\t(0x10 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_GTR\t\t(0x10 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_PKHA_B_SZ\t(0x11 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_PKHA_N_SZ\t(0x12 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_PKHA_E_SZ\t(0x13 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_CLASS_CTX\t(0x20 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_STR\t\t(0x20 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DESCBUF\t(0x40 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DESCBUF_JOB\t(0x41 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DESCBUF_SHARED\t(0x42 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DESCBUF_JOB_WE\t(0x45 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_DESCBUF_SHARED_WE (0x46 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_INFO_FIFO_SZL\t(0x70 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_INFO_FIFO_SZM\t(0x71 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_INFO_FIFO_L\t(0x72 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_INFO_FIFO_M\t(0x73 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_SZL\t\t(0x74 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_SZM\t\t(0x75 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_IFNSR\t\t(0x76 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_OFNSR\t\t(0x77 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_BYTE_ALTSOURCE\t(0x78 << LDST_SRCDST_SHIFT)\n+#define LDST_SRCDST_WORD_INFO_FIFO\t(0x7a << LDST_SRCDST_SHIFT)\n+\n+/* Offset in source/destination */\n+#define LDST_OFFSET_SHIFT\t8\n+#define LDST_OFFSET_MASK\t(0xff << LDST_OFFSET_SHIFT)\n+\n+/* LDOFF definitions used when DST = LDST_SRCDST_WORD_DECOCTRL */\n+/* These could also be shifted by LDST_OFFSET_SHIFT - this reads better */\n+#define LDOFF_CHG_SHARE_SHIFT\t\t0\n+#define LDOFF_CHG_SHARE_MASK\t\t(0x3 << LDOFF_CHG_SHARE_SHIFT)\n+#define LDOFF_CHG_SHARE_NEVER\t\t(0x1 << LDOFF_CHG_SHARE_SHIFT)\n+#define LDOFF_CHG_SHARE_OK_PROP\t\t(0x2 << LDOFF_CHG_SHARE_SHIFT)\n+#define LDOFF_CHG_SHARE_OK_NO_PROP\t(0x3 << LDOFF_CHG_SHARE_SHIFT)\n+\n+#define LDOFF_ENABLE_AUTO_NFIFO\t\tBIT(2)\n+#define LDOFF_DISABLE_AUTO_NFIFO\tBIT(3)\n+\n+#define LDOFF_CHG_NONSEQLIODN_SHIFT\t4\n+#define LDOFF_CHG_NONSEQLIODN_MASK\t(0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT)\n+#define LDOFF_CHG_NONSEQLIODN_SEQ\t(0x1 << LDOFF_CHG_NONSEQLIODN_SHIFT)\n+#define LDOFF_CHG_NONSEQLIODN_NON_SEQ\t(0x2 << LDOFF_CHG_NONSEQLIODN_SHIFT)\n+#define LDOFF_CHG_NONSEQLIODN_TRUSTED\t(0x3 << LDOFF_CHG_NONSEQLIODN_SHIFT)\n+\n+#define LDOFF_CHG_SEQLIODN_SHIFT\t6\n+#define LDOFF_CHG_SEQLIODN_MASK\t\t(0x3 << LDOFF_CHG_SEQLIODN_SHIFT)\n+#define LDOFF_CHG_SEQLIODN_SEQ\t\t(0x1 << LDOFF_CHG_SEQLIODN_SHIFT)\n+#define LDOFF_CHG_SEQLIODN_NON_SEQ\t(0x2 << LDOFF_CHG_SEQLIODN_SHIFT)\n+#define LDOFF_CHG_SEQLIODN_TRUSTED\t(0x3 << LDOFF_CHG_SEQLIODN_SHIFT)\n+\n+/* Data length in bytes */\n+#define LDST_LEN_SHIFT\t\t0\n+#define LDST_LEN_MASK\t\t(0xff << LDST_LEN_SHIFT)\n+\n+/* Special Length definitions when dst=deco-ctrl */\n+#define LDLEN_ENABLE_OSL_COUNT\t\tBIT(7)\n+#define LDLEN_RST_CHA_OFIFO_PTR\t\tBIT(6)\n+#define LDLEN_RST_OFIFO\t\t\tBIT(5)\n+#define LDLEN_SET_OFIFO_OFF_VALID\tBIT(4)\n+#define LDLEN_SET_OFIFO_OFF_RSVD\tBIT(3)\n+#define LDLEN_SET_OFIFO_OFFSET_SHIFT\t0\n+#define LDLEN_SET_OFIFO_OFFSET_MASK\t(3 << LDLEN_SET_OFIFO_OFFSET_SHIFT)\n+\n+/* CCB Clear Written Register bits */\n+#define CLRW_CLR_C1MODE              BIT(0)\n+#define CLRW_CLR_C1DATAS             BIT(2)\n+#define CLRW_CLR_C1ICV               BIT(3)\n+#define CLRW_CLR_C1CTX               BIT(5)\n+#define CLRW_CLR_C1KEY               BIT(6)\n+#define CLRW_CLR_PK_A                BIT(12)\n+#define CLRW_CLR_PK_B                BIT(13)\n+#define CLRW_CLR_PK_N                BIT(14)\n+#define CLRW_CLR_PK_E                BIT(15)\n+#define CLRW_CLR_C2MODE              BIT(16)\n+#define CLRW_CLR_C2KEYS              BIT(17)\n+#define CLRW_CLR_C2DATAS             BIT(18)\n+#define CLRW_CLR_C2CTX               BIT(21)\n+#define CLRW_CLR_C2KEY               BIT(22)\n+#define CLRW_RESET_CLS2_DONE         BIT(26) /* era 4 */\n+#define CLRW_RESET_CLS1_DONE         BIT(27) /* era 4 */\n+#define CLRW_RESET_CLS2_CHA          BIT(28) /* era 4 */\n+#define CLRW_RESET_CLS1_CHA          BIT(29) /* era 4 */\n+#define CLRW_RESET_OFIFO             BIT(30) /* era 3 */\n+#define CLRW_RESET_IFIFO_DFIFO       BIT(31) /* era 3 */\n+\n+/* CHA Control Register bits */\n+#define CCTRL_RESET_CHA_ALL          BIT(0)\n+#define CCTRL_RESET_CHA_AESA         BIT(1)\n+#define CCTRL_RESET_CHA_DESA         BIT(2)\n+#define CCTRL_RESET_CHA_AFHA         BIT(3)\n+#define CCTRL_RESET_CHA_KFHA         BIT(4)\n+#define CCTRL_RESET_CHA_SF8A         BIT(5)\n+#define CCTRL_RESET_CHA_PKHA         BIT(6)\n+#define CCTRL_RESET_CHA_MDHA         BIT(7)\n+#define CCTRL_RESET_CHA_CRCA         BIT(8)\n+#define CCTRL_RESET_CHA_RNG          BIT(9)\n+#define CCTRL_RESET_CHA_SF9A         BIT(10)\n+#define CCTRL_RESET_CHA_ZUCE         BIT(11)\n+#define CCTRL_RESET_CHA_ZUCA         BIT(12)\n+#define CCTRL_UNLOAD_PK_A0           BIT(16)\n+#define CCTRL_UNLOAD_PK_A1           BIT(17)\n+#define CCTRL_UNLOAD_PK_A2           BIT(18)\n+#define CCTRL_UNLOAD_PK_A3           BIT(19)\n+#define CCTRL_UNLOAD_PK_B0           BIT(20)\n+#define CCTRL_UNLOAD_PK_B1           BIT(21)\n+#define CCTRL_UNLOAD_PK_B2           BIT(22)\n+#define CCTRL_UNLOAD_PK_B3           BIT(23)\n+#define CCTRL_UNLOAD_PK_N            BIT(24)\n+#define CCTRL_UNLOAD_PK_A            BIT(26)\n+#define CCTRL_UNLOAD_PK_B            BIT(27)\n+#define CCTRL_UNLOAD_SBOX            BIT(28)\n+\n+/* IRQ Control Register (CxCIRQ) bits */\n+#define CIRQ_ADI\tBIT(1)\n+#define CIRQ_DDI\tBIT(2)\n+#define CIRQ_RCDI\tBIT(3)\n+#define CIRQ_KDI\tBIT(4)\n+#define CIRQ_S8DI\tBIT(5)\n+#define CIRQ_PDI\tBIT(6)\n+#define CIRQ_MDI\tBIT(7)\n+#define CIRQ_CDI\tBIT(8)\n+#define CIRQ_RNDI\tBIT(9)\n+#define CIRQ_S9DI\tBIT(10)\n+#define CIRQ_ZEDI\tBIT(11) /* valid for Era 5 or higher */\n+#define CIRQ_ZADI\tBIT(12) /* valid for Era 5 or higher */\n+#define CIRQ_AEI\tBIT(17)\n+#define CIRQ_DEI\tBIT(18)\n+#define CIRQ_RCEI\tBIT(19)\n+#define CIRQ_KEI\tBIT(20)\n+#define CIRQ_S8EI\tBIT(21)\n+#define CIRQ_PEI\tBIT(22)\n+#define CIRQ_MEI\tBIT(23)\n+#define CIRQ_CEI\tBIT(24)\n+#define CIRQ_RNEI\tBIT(25)\n+#define CIRQ_S9EI\tBIT(26)\n+#define CIRQ_ZEEI\tBIT(27) /* valid for Era 5 or higher */\n+#define CIRQ_ZAEI\tBIT(28) /* valid for Era 5 or higher */\n+\n+/*\n+ * FIFO_LOAD/FIFO_STORE/SEQ_FIFO_LOAD/SEQ_FIFO_STORE\n+ * Command Constructs\n+ */\n+\n+/*\n+ * Load Destination: 0 = skip (SEQ_FIFO_LOAD only),\n+ * 1 = Load for Class1, 2 = Load for Class2, 3 = Load both\n+ * Store Source: 0 = normal, 1 = Class1key, 2 = Class2key\n+ */\n+#define FIFOLD_CLASS_SHIFT\t25\n+#define FIFOLD_CLASS_MASK\t(0x03 << FIFOLD_CLASS_SHIFT)\n+#define FIFOLD_CLASS_SKIP\t(0x00 << FIFOLD_CLASS_SHIFT)\n+#define FIFOLD_CLASS_CLASS1\t(0x01 << FIFOLD_CLASS_SHIFT)\n+#define FIFOLD_CLASS_CLASS2\t(0x02 << FIFOLD_CLASS_SHIFT)\n+#define FIFOLD_CLASS_BOTH\t(0x03 << FIFOLD_CLASS_SHIFT)\n+\n+#define FIFOST_CLASS_SHIFT\t25\n+#define FIFOST_CLASS_MASK\t(0x03 << FIFOST_CLASS_SHIFT)\n+#define FIFOST_CLASS_NORMAL\t(0x00 << FIFOST_CLASS_SHIFT)\n+#define FIFOST_CLASS_CLASS1KEY\t(0x01 << FIFOST_CLASS_SHIFT)\n+#define FIFOST_CLASS_CLASS2KEY\t(0x02 << FIFOST_CLASS_SHIFT)\n+#define FIFOST_CLASS_BOTH\t(0x03 << FIFOST_CLASS_SHIFT)\n+\n+/*\n+ * Scatter-Gather Table/Variable Length Field\n+ * If set for FIFO_LOAD, refers to a SG table. Within\n+ * SEQ_FIFO_LOAD, is variable input sequence\n+ */\n+#define FIFOLDST_SGF_SHIFT\t24\n+#define FIFOLDST_SGF_MASK\t(1 << FIFOLDST_SGF_SHIFT)\n+#define FIFOLDST_VLF_MASK\t(1 << FIFOLDST_SGF_SHIFT)\n+#define FIFOLDST_SGF\t\tBIT(24)\n+#define FIFOLDST_VLF\t\tBIT(24)\n+\n+/*\n+ * Immediate - Data follows command in descriptor\n+ * AIDF - Already in Input Data FIFO\n+ */\n+#define FIFOLD_IMM_SHIFT\t23\n+#define FIFOLD_IMM_MASK\t\t(1 << FIFOLD_IMM_SHIFT)\n+#define FIFOLD_AIDF_MASK\t(1 << FIFOLD_IMM_SHIFT)\n+#define FIFOLD_IMM\t\tBIT(23)\n+#define FIFOLD_AIDF\t\tBIT(23)\n+\n+#define FIFOST_IMM_SHIFT\t23\n+#define FIFOST_IMM_MASK\t\t(1 << FIFOST_IMM_SHIFT)\n+#define FIFOST_IMM\t\tBIT(23)\n+\n+/* Continue - Not the last FIFO store to come */\n+#define FIFOST_CONT_SHIFT\t23\n+#define FIFOST_CONT_MASK\t(1 << FIFOST_CONT_SHIFT)\n+#define FIFOST_CONT\t\tBIT(23)\n+\n+/*\n+ * Extended Length - use 32-bit extended length that\n+ * follows the pointer field. Illegal with IMM set\n+ */\n+#define FIFOLDST_EXT_SHIFT\t22\n+#define FIFOLDST_EXT_MASK\t(1 << FIFOLDST_EXT_SHIFT)\n+#define FIFOLDST_EXT\t\tBIT(22)\n+\n+/* Input data type.*/\n+#define FIFOLD_TYPE_SHIFT\t16\n+#define FIFOLD_CONT_TYPE_SHIFT\t19 /* shift past last-flush bits */\n+#define FIFOLD_TYPE_MASK\t(0x3f << FIFOLD_TYPE_SHIFT)\n+\n+/* PK types */\n+#define FIFOLD_TYPE_PK\t\t(0x00 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_MASK\t(0x30 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_TYPEMASK (0x0f << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_A0\t(0x00 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_A1\t(0x01 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_A2\t(0x02 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_A3\t(0x03 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_B0\t(0x04 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_B1\t(0x05 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_B2\t(0x06 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_B3\t(0x07 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_N\t(0x08 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_A\t(0x0c << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_PK_B\t(0x0d << FIFOLD_TYPE_SHIFT)\n+\n+/* Other types. Need to OR in last/flush bits as desired */\n+#define FIFOLD_TYPE_MSG_MASK\t(0x38 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_MSG\t\t(0x10 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_MSG1OUT2\t(0x18 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_IV\t\t(0x20 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_BITDATA\t(0x28 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_AAD\t\t(0x30 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_ICV\t\t(0x38 << FIFOLD_TYPE_SHIFT)\n+\n+/* Last/Flush bits for use with \"other\" types above */\n+#define FIFOLD_TYPE_ACT_MASK\t(0x07 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_NOACTION\t(0x00 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_FLUSH1\t(0x01 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_LAST1\t(0x02 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_LAST2FLUSH\t(0x03 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_LAST2\t(0x04 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_LAST2FLUSH1 (0x05 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_LASTBOTH\t(0x06 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_LASTBOTHFL\t(0x07 << FIFOLD_TYPE_SHIFT)\n+#define FIFOLD_TYPE_NOINFOFIFO\t(0x0f << FIFOLD_TYPE_SHIFT)\n+\n+#define FIFOLDST_LEN_MASK\t0xffff\n+#define FIFOLDST_EXT_LEN_MASK\t0xffffffff\n+\n+/* Output data types */\n+#define FIFOST_TYPE_SHIFT\t16\n+#define FIFOST_TYPE_MASK\t(0x3f << FIFOST_TYPE_SHIFT)\n+\n+#define FIFOST_TYPE_PKHA_A0\t (0x00 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_A1\t (0x01 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_A2\t (0x02 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_A3\t (0x03 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_B0\t (0x04 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_B1\t (0x05 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_B2\t (0x06 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_B3\t (0x07 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_N\t (0x08 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_A\t (0x0c << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_B\t (0x0d << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_AF_SBOX_JKEK (0x20 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_E_JKEK\t (0x22 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_PKHA_E_TKEK\t (0x23 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_KEY_KEK\t (0x24 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_KEY_TKEK\t (0x25 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_SPLIT_KEK\t (0x26 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_SPLIT_TKEK\t (0x27 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_OUTFIFO_KEK\t (0x28 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_OUTFIFO_TKEK (0x29 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_MESSAGE_DATA (0x30 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_MESSAGE_DATA2 (0x31 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_RNGSTORE\t (0x34 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_RNGFIFO\t (0x35 << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_METADATA\t (0x3e << FIFOST_TYPE_SHIFT)\n+#define FIFOST_TYPE_SKIP\t (0x3f << FIFOST_TYPE_SHIFT)\n+\n+/*\n+ * OPERATION Command Constructs\n+ */\n+\n+/* Operation type selectors - OP TYPE */\n+#define OP_TYPE_SHIFT\t\t24\n+#define OP_TYPE_MASK\t\t(0x07 << OP_TYPE_SHIFT)\n+\n+#define OP_TYPE_UNI_PROTOCOL\t(0x00 << OP_TYPE_SHIFT)\n+#define OP_TYPE_PK\t\t(0x01 << OP_TYPE_SHIFT)\n+#define OP_TYPE_CLASS1_ALG\t(0x02 << OP_TYPE_SHIFT)\n+#define OP_TYPE_CLASS2_ALG\t(0x04 << OP_TYPE_SHIFT)\n+#define OP_TYPE_DECAP_PROTOCOL\t(0x06 << OP_TYPE_SHIFT)\n+#define OP_TYPE_ENCAP_PROTOCOL\t(0x07 << OP_TYPE_SHIFT)\n+\n+/* ProtocolID selectors - PROTID */\n+#define OP_PCLID_SHIFT\t\t16\n+#define OP_PCLID_MASK\t\t(0xff << OP_PCLID_SHIFT)\n+\n+/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */\n+#define OP_PCLID_IKEV1_PRF\t(0x01 << OP_PCLID_SHIFT)\n+#define OP_PCLID_IKEV2_PRF\t(0x02 << OP_PCLID_SHIFT)\n+#define OP_PCLID_SSL30_PRF\t(0x08 << OP_PCLID_SHIFT)\n+#define OP_PCLID_TLS10_PRF\t(0x09 << OP_PCLID_SHIFT)\n+#define OP_PCLID_TLS11_PRF\t(0x0a << OP_PCLID_SHIFT)\n+#define OP_PCLID_TLS12_PRF\t(0x0b << OP_PCLID_SHIFT)\n+#define OP_PCLID_DTLS10_PRF\t(0x0c << OP_PCLID_SHIFT)\n+#define OP_PCLID_PUBLICKEYPAIR\t(0x14 << OP_PCLID_SHIFT)\n+#define OP_PCLID_DSASIGN\t(0x15 << OP_PCLID_SHIFT)\n+#define OP_PCLID_DSAVERIFY\t(0x16 << OP_PCLID_SHIFT)\n+#define OP_PCLID_DIFFIEHELLMAN\t(0x17 << OP_PCLID_SHIFT)\n+#define OP_PCLID_RSAENCRYPT\t(0x18 << OP_PCLID_SHIFT)\n+#define OP_PCLID_RSADECRYPT\t(0x19 << OP_PCLID_SHIFT)\n+#define OP_PCLID_DKP_MD5\t(0x20 << OP_PCLID_SHIFT)\n+#define OP_PCLID_DKP_SHA1\t(0x21 << OP_PCLID_SHIFT)\n+#define OP_PCLID_DKP_SHA224\t(0x22 << OP_PCLID_SHIFT)\n+#define OP_PCLID_DKP_SHA256\t(0x23 << OP_PCLID_SHIFT)\n+#define OP_PCLID_DKP_SHA384\t(0x24 << OP_PCLID_SHIFT)\n+#define OP_PCLID_DKP_SHA512\t(0x25 << OP_PCLID_SHIFT)\n+\n+/* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL/ENCAP_PROTOCOL */\n+#define OP_PCLID_IPSEC\t\t(0x01 << OP_PCLID_SHIFT)\n+#define OP_PCLID_SRTP\t\t(0x02 << OP_PCLID_SHIFT)\n+#define OP_PCLID_MACSEC\t\t(0x03 << OP_PCLID_SHIFT)\n+#define OP_PCLID_WIFI\t\t(0x04 << OP_PCLID_SHIFT)\n+#define OP_PCLID_WIMAX\t\t(0x05 << OP_PCLID_SHIFT)\n+#define OP_PCLID_SSL30\t\t(0x08 << OP_PCLID_SHIFT)\n+#define OP_PCLID_TLS10\t\t(0x09 << OP_PCLID_SHIFT)\n+#define OP_PCLID_TLS11\t\t(0x0a << OP_PCLID_SHIFT)\n+#define OP_PCLID_TLS12\t\t(0x0b << OP_PCLID_SHIFT)\n+#define OP_PCLID_DTLS10\t\t(0x0c << OP_PCLID_SHIFT)\n+#define OP_PCLID_BLOB\t\t(0x0d << OP_PCLID_SHIFT)\n+#define OP_PCLID_IPSEC_NEW\t(0x11 << OP_PCLID_SHIFT)\n+#define OP_PCLID_3G_DCRC\t(0x31 << OP_PCLID_SHIFT)\n+#define OP_PCLID_3G_RLC_PDU\t(0x32 << OP_PCLID_SHIFT)\n+#define OP_PCLID_3G_RLC_SDU\t(0x33 << OP_PCLID_SHIFT)\n+#define OP_PCLID_LTE_PDCP_USER\t(0x42 << OP_PCLID_SHIFT)\n+#define OP_PCLID_LTE_PDCP_CTRL\t(0x43 << OP_PCLID_SHIFT)\n+#define OP_PCLID_LTE_PDCP_CTRL_MIXED\t(0x44 << OP_PCLID_SHIFT)\n+\n+/*\n+ * ProtocolInfo selectors\n+ */\n+#define OP_PCLINFO_MASK\t\t\t\t 0xffff\n+\n+/* for OP_PCLID_IPSEC */\n+#define OP_PCL_IPSEC_CIPHER_MASK\t\t 0xff00\n+#define OP_PCL_IPSEC_AUTH_MASK\t\t\t 0x00ff\n+\n+#define OP_PCL_IPSEC_DES_IV64\t\t\t 0x0100\n+#define OP_PCL_IPSEC_DES\t\t\t 0x0200\n+#define OP_PCL_IPSEC_3DES\t\t\t 0x0300\n+#define OP_PCL_IPSEC_NULL\t\t\t 0x0B00\n+#define OP_PCL_IPSEC_AES_CBC\t\t\t 0x0c00\n+#define OP_PCL_IPSEC_AES_CTR\t\t\t 0x0d00\n+#define OP_PCL_IPSEC_AES_XTS\t\t\t 0x1600\n+#define OP_PCL_IPSEC_AES_CCM8\t\t\t 0x0e00\n+#define OP_PCL_IPSEC_AES_CCM12\t\t\t 0x0f00\n+#define OP_PCL_IPSEC_AES_CCM16\t\t\t 0x1000\n+#define OP_PCL_IPSEC_AES_GCM8\t\t\t 0x1200\n+#define OP_PCL_IPSEC_AES_GCM12\t\t\t 0x1300\n+#define OP_PCL_IPSEC_AES_GCM16\t\t\t 0x1400\n+#define OP_PCL_IPSEC_AES_NULL_WITH_GMAC\t\t 0x1500\n+\n+#define OP_PCL_IPSEC_HMAC_NULL\t\t\t 0x0000\n+#define OP_PCL_IPSEC_HMAC_MD5_96\t\t 0x0001\n+#define OP_PCL_IPSEC_HMAC_SHA1_96\t\t 0x0002\n+#define OP_PCL_IPSEC_AES_XCBC_MAC_96\t\t 0x0005\n+#define OP_PCL_IPSEC_HMAC_MD5_128\t\t 0x0006\n+#define OP_PCL_IPSEC_HMAC_SHA1_160\t\t 0x0007\n+#define OP_PCL_IPSEC_AES_CMAC_96\t\t 0x0008\n+#define OP_PCL_IPSEC_HMAC_SHA2_256_128\t\t 0x000c\n+#define OP_PCL_IPSEC_HMAC_SHA2_384_192\t\t 0x000d\n+#define OP_PCL_IPSEC_HMAC_SHA2_512_256\t\t 0x000e\n+\n+/* For SRTP - OP_PCLID_SRTP */\n+#define OP_PCL_SRTP_CIPHER_MASK\t\t\t 0xff00\n+#define OP_PCL_SRTP_AUTH_MASK\t\t\t 0x00ff\n+\n+#define OP_PCL_SRTP_AES_CTR\t\t\t 0x0d00\n+\n+#define OP_PCL_SRTP_HMAC_SHA1_160\t\t 0x0007\n+\n+/* For SSL 3.0 - OP_PCLID_SSL30 */\n+#define OP_PCL_SSL30_AES_128_CBC_SHA\t\t 0x002f\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_2\t\t 0x0030\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_3\t\t 0x0031\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_4\t\t 0x0032\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_5\t\t 0x0033\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_6\t\t 0x0034\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_7\t\t 0x008c\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_8\t\t 0x0090\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_9\t\t 0x0094\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_10\t\t 0xc004\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_11\t\t 0xc009\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_12\t\t 0xc00e\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_13\t\t 0xc013\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_14\t\t 0xc018\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_15\t\t 0xc01d\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_16\t\t 0xc01e\n+#define OP_PCL_SSL30_AES_128_CBC_SHA_17\t\t 0xc01f\n+\n+#define OP_PCL_SSL30_AES_256_CBC_SHA\t\t 0x0035\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_2\t\t 0x0036\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_3\t\t 0x0037\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_4\t\t 0x0038\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_5\t\t 0x0039\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_6\t\t 0x003a\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_7\t\t 0x008d\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_8\t\t 0x0091\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_9\t\t 0x0095\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_10\t\t 0xc005\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_11\t\t 0xc00a\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_12\t\t 0xc00f\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_13\t\t 0xc014\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_14\t\t 0xc019\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_15\t\t 0xc020\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_16\t\t 0xc021\n+#define OP_PCL_SSL30_AES_256_CBC_SHA_17\t\t 0xc022\n+\n+#define OP_PCL_SSL30_AES_128_GCM_SHA256_1\t 0x009C\n+#define OP_PCL_SSL30_AES_256_GCM_SHA384_1\t 0x009D\n+#define OP_PCL_SSL30_AES_128_GCM_SHA256_2\t 0x009E\n+#define OP_PCL_SSL30_AES_256_GCM_SHA384_2\t 0x009F\n+#define OP_PCL_SSL30_AES_128_GCM_SHA256_3\t 0x00A0\n+#define OP_PCL_SSL30_AES_256_GCM_SHA384_3\t 0x00A1\n+#define OP_PCL_SSL30_AES_128_GCM_SHA256_4\t 0x00A2\n+#define OP_PCL_SSL30_AES_256_GCM_SHA384_4\t 0x00A3\n+#define OP_PCL_SSL30_AES_128_GCM_SHA256_5\t 0x00A4\n+#define OP_PCL_SSL30_AES_256_GCM_SHA384_5\t 0x00A5\n+#define OP_PCL_SSL30_AES_128_GCM_SHA256_6\t 0x00A6\n+\n+#define OP_PCL_TLS_DH_ANON_AES_256_GCM_SHA384\t 0x00A7\n+#define OP_PCL_TLS_PSK_AES_128_GCM_SHA256\t 0x00A8\n+#define OP_PCL_TLS_PSK_AES_256_GCM_SHA384\t 0x00A9\n+#define OP_PCL_TLS_DHE_PSK_AES_128_GCM_SHA256\t 0x00AA\n+#define OP_PCL_TLS_DHE_PSK_AES_256_GCM_SHA384\t 0x00AB\n+#define OP_PCL_TLS_RSA_PSK_AES_128_GCM_SHA256\t 0x00AC\n+#define OP_PCL_TLS_RSA_PSK_AES_256_GCM_SHA384\t 0x00AD\n+#define OP_PCL_TLS_PSK_AES_128_CBC_SHA256\t 0x00AE\n+#define OP_PCL_TLS_PSK_AES_256_CBC_SHA384\t 0x00AF\n+#define OP_PCL_TLS_DHE_PSK_AES_128_CBC_SHA256\t 0x00B2\n+#define OP_PCL_TLS_DHE_PSK_AES_256_CBC_SHA384\t 0x00B3\n+#define OP_PCL_TLS_RSA_PSK_AES_128_CBC_SHA256\t 0x00B6\n+#define OP_PCL_TLS_RSA_PSK_AES_256_CBC_SHA384\t 0x00B7\n+\n+#define OP_PCL_SSL30_3DES_EDE_CBC_MD5\t\t 0x0023\n+\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA\t\t 0x001f\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_2\t\t 0x008b\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_3\t\t 0x008f\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_4\t\t 0x0093\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_5\t\t 0x000a\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_6\t\t 0x000d\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_7\t\t 0x0010\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_8\t\t 0x0013\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_9\t\t 0x0016\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_10\t 0x001b\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_11\t 0xc003\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_12\t 0xc008\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_13\t 0xc00d\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_14\t 0xc012\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_15\t 0xc017\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_16\t 0xc01a\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_17\t 0xc01b\n+#define OP_PCL_SSL30_3DES_EDE_CBC_SHA_18\t 0xc01c\n+\n+#define OP_PCL_SSL30_DES40_CBC_MD5\t\t 0x0029\n+\n+#define OP_PCL_SSL30_DES_CBC_MD5\t\t 0x0022\n+\n+#define OP_PCL_SSL30_DES40_CBC_SHA\t\t 0x0008\n+#define OP_PCL_SSL30_DES40_CBC_SHA_2\t\t 0x000b\n+#define OP_PCL_SSL30_DES40_CBC_SHA_3\t\t 0x000e\n+#define OP_PCL_SSL30_DES40_CBC_SHA_4\t\t 0x0011\n+#define OP_PCL_SSL30_DES40_CBC_SHA_5\t\t 0x0014\n+#define OP_PCL_SSL30_DES40_CBC_SHA_6\t\t 0x0019\n+#define OP_PCL_SSL30_DES40_CBC_SHA_7\t\t 0x0026\n+\n+#define OP_PCL_SSL30_DES_CBC_SHA\t\t 0x001e\n+#define OP_PCL_SSL30_DES_CBC_SHA_2\t\t 0x0009\n+#define OP_PCL_SSL30_DES_CBC_SHA_3\t\t 0x000c\n+#define OP_PCL_SSL30_DES_CBC_SHA_4\t\t 0x000f\n+#define OP_PCL_SSL30_DES_CBC_SHA_5\t\t 0x0012\n+#define OP_PCL_SSL30_DES_CBC_SHA_6\t\t 0x0015\n+#define OP_PCL_SSL30_DES_CBC_SHA_7\t\t 0x001a\n+\n+#define OP_PCL_SSL30_RC4_128_MD5\t\t 0x0024\n+#define OP_PCL_SSL30_RC4_128_MD5_2\t\t 0x0004\n+#define OP_PCL_SSL30_RC4_128_MD5_3\t\t 0x0018\n+\n+#define OP_PCL_SSL30_RC4_40_MD5\t\t\t 0x002b\n+#define OP_PCL_SSL30_RC4_40_MD5_2\t\t 0x0003\n+#define OP_PCL_SSL30_RC4_40_MD5_3\t\t 0x0017\n+\n+#define OP_PCL_SSL30_RC4_128_SHA\t\t 0x0020\n+#define OP_PCL_SSL30_RC4_128_SHA_2\t\t 0x008a\n+#define OP_PCL_SSL30_RC4_128_SHA_3\t\t 0x008e\n+#define OP_PCL_SSL30_RC4_128_SHA_4\t\t 0x0092\n+#define OP_PCL_SSL30_RC4_128_SHA_5\t\t 0x0005\n+#define OP_PCL_SSL30_RC4_128_SHA_6\t\t 0xc002\n+#define OP_PCL_SSL30_RC4_128_SHA_7\t\t 0xc007\n+#define OP_PCL_SSL30_RC4_128_SHA_8\t\t 0xc00c\n+#define OP_PCL_SSL30_RC4_128_SHA_9\t\t 0xc011\n+#define OP_PCL_SSL30_RC4_128_SHA_10\t\t 0xc016\n+\n+#define OP_PCL_SSL30_RC4_40_SHA\t\t\t 0x0028\n+\n+\n+/* For TLS 1.0 - OP_PCLID_TLS10 */\n+#define OP_PCL_TLS10_AES_128_CBC_SHA\t\t 0x002f\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_2\t\t 0x0030\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_3\t\t 0x0031\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_4\t\t 0x0032\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_5\t\t 0x0033\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_6\t\t 0x0034\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_7\t\t 0x008c\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_8\t\t 0x0090\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_9\t\t 0x0094\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_10\t\t 0xc004\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_11\t\t 0xc009\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_12\t\t 0xc00e\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_13\t\t 0xc013\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_14\t\t 0xc018\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_15\t\t 0xc01d\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_16\t\t 0xc01e\n+#define OP_PCL_TLS10_AES_128_CBC_SHA_17\t\t 0xc01f\n+\n+#define OP_PCL_TLS10_AES_256_CBC_SHA\t\t 0x0035\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_2\t\t 0x0036\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_3\t\t 0x0037\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_4\t\t 0x0038\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_5\t\t 0x0039\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_6\t\t 0x003a\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_7\t\t 0x008d\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_8\t\t 0x0091\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_9\t\t 0x0095\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_10\t\t 0xc005\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_11\t\t 0xc00a\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_12\t\t 0xc00f\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_13\t\t 0xc014\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_14\t\t 0xc019\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_15\t\t 0xc020\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_16\t\t 0xc021\n+#define OP_PCL_TLS10_AES_256_CBC_SHA_17\t\t 0xc022\n+\n+#define OP_PCL_TLS_ECDHE_ECDSA_AES_128_CBC_SHA256  0xC023\n+#define OP_PCL_TLS_ECDHE_ECDSA_AES_256_CBC_SHA384  0xC024\n+#define OP_PCL_TLS_ECDH_ECDSA_AES_128_CBC_SHA256   0xC025\n+#define OP_PCL_TLS_ECDH_ECDSA_AES_256_CBC_SHA384   0xC026\n+#define OP_PCL_TLS_ECDHE_RSA_AES_128_CBC_SHA256\t   0xC027\n+#define OP_PCL_TLS_ECDHE_RSA_AES_256_CBC_SHA384\t   0xC028\n+#define OP_PCL_TLS_ECDH_RSA_AES_128_CBC_SHA256\t   0xC029\n+#define OP_PCL_TLS_ECDH_RSA_AES_256_CBC_SHA384\t   0xC02A\n+#define OP_PCL_TLS_ECDHE_ECDSA_AES_128_GCM_SHA256  0xC02B\n+#define OP_PCL_TLS_ECDHE_ECDSA_AES_256_GCM_SHA384  0xC02C\n+#define OP_PCL_TLS_ECDH_ECDSA_AES_128_GCM_SHA256   0xC02D\n+#define OP_PCL_TLS_ECDH_ECDSA_AES_256_GCM_SHA384   0xC02E\n+#define OP_PCL_TLS_ECDHE_RSA_AES_128_GCM_SHA256\t   0xC02F\n+#define OP_PCL_TLS_ECDHE_RSA_AES_256_GCM_SHA384\t   0xC030\n+#define OP_PCL_TLS_ECDH_RSA_AES_128_GCM_SHA256\t   0xC031\n+#define OP_PCL_TLS_ECDH_RSA_AES_256_GCM_SHA384\t   0xC032\n+#define OP_PCL_TLS_ECDHE_PSK_RC4_128_SHA\t   0xC033\n+#define OP_PCL_TLS_ECDHE_PSK_3DES_EDE_CBC_SHA\t   0xC034\n+#define OP_PCL_TLS_ECDHE_PSK_AES_128_CBC_SHA\t   0xC035\n+#define OP_PCL_TLS_ECDHE_PSK_AES_256_CBC_SHA\t   0xC036\n+#define OP_PCL_TLS_ECDHE_PSK_AES_128_CBC_SHA256\t   0xC037\n+#define OP_PCL_TLS_ECDHE_PSK_AES_256_CBC_SHA384\t   0xC038\n+\n+/* #define OP_PCL_TLS10_3DES_EDE_CBC_MD5\t0x0023 */\n+\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA\t\t 0x001f\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_2\t\t 0x008b\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_3\t\t 0x008f\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_4\t\t 0x0093\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_5\t\t 0x000a\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_6\t\t 0x000d\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_7\t\t 0x0010\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_8\t\t 0x0013\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_9\t\t 0x0016\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_10\t 0x001b\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_11\t 0xc003\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_12\t 0xc008\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_13\t 0xc00d\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_14\t 0xc012\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_15\t 0xc017\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_16\t 0xc01a\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_17\t 0xc01b\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA_18\t 0xc01c\n+\n+#define OP_PCL_TLS10_DES40_CBC_MD5\t\t 0x0029\n+\n+#define OP_PCL_TLS10_DES_CBC_MD5\t\t 0x0022\n+\n+#define OP_PCL_TLS10_DES40_CBC_SHA\t\t 0x0008\n+#define OP_PCL_TLS10_DES40_CBC_SHA_2\t\t 0x000b\n+#define OP_PCL_TLS10_DES40_CBC_SHA_3\t\t 0x000e\n+#define OP_PCL_TLS10_DES40_CBC_SHA_4\t\t 0x0011\n+#define OP_PCL_TLS10_DES40_CBC_SHA_5\t\t 0x0014\n+#define OP_PCL_TLS10_DES40_CBC_SHA_6\t\t 0x0019\n+#define OP_PCL_TLS10_DES40_CBC_SHA_7\t\t 0x0026\n+\n+\n+#define OP_PCL_TLS10_DES_CBC_SHA\t\t 0x001e\n+#define OP_PCL_TLS10_DES_CBC_SHA_2\t\t 0x0009\n+#define OP_PCL_TLS10_DES_CBC_SHA_3\t\t 0x000c\n+#define OP_PCL_TLS10_DES_CBC_SHA_4\t\t 0x000f\n+#define OP_PCL_TLS10_DES_CBC_SHA_5\t\t 0x0012\n+#define OP_PCL_TLS10_DES_CBC_SHA_6\t\t 0x0015\n+#define OP_PCL_TLS10_DES_CBC_SHA_7\t\t 0x001a\n+\n+#define OP_PCL_TLS10_RC4_128_MD5\t\t 0x0024\n+#define OP_PCL_TLS10_RC4_128_MD5_2\t\t 0x0004\n+#define OP_PCL_TLS10_RC4_128_MD5_3\t\t 0x0018\n+\n+#define OP_PCL_TLS10_RC4_40_MD5\t\t\t 0x002b\n+#define OP_PCL_TLS10_RC4_40_MD5_2\t\t 0x0003\n+#define OP_PCL_TLS10_RC4_40_MD5_3\t\t 0x0017\n+\n+#define OP_PCL_TLS10_RC4_128_SHA\t\t 0x0020\n+#define OP_PCL_TLS10_RC4_128_SHA_2\t\t 0x008a\n+#define OP_PCL_TLS10_RC4_128_SHA_3\t\t 0x008e\n+#define OP_PCL_TLS10_RC4_128_SHA_4\t\t 0x0092\n+#define OP_PCL_TLS10_RC4_128_SHA_5\t\t 0x0005\n+#define OP_PCL_TLS10_RC4_128_SHA_6\t\t 0xc002\n+#define OP_PCL_TLS10_RC4_128_SHA_7\t\t 0xc007\n+#define OP_PCL_TLS10_RC4_128_SHA_8\t\t 0xc00c\n+#define OP_PCL_TLS10_RC4_128_SHA_9\t\t 0xc011\n+#define OP_PCL_TLS10_RC4_128_SHA_10\t\t 0xc016\n+\n+#define OP_PCL_TLS10_RC4_40_SHA\t\t\t 0x0028\n+\n+#define OP_PCL_TLS10_3DES_EDE_CBC_MD5\t\t 0xff23\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA160\t 0xff30\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA224\t 0xff34\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA256\t 0xff36\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA384\t 0xff33\n+#define OP_PCL_TLS10_3DES_EDE_CBC_SHA512\t 0xff35\n+#define OP_PCL_TLS10_AES_128_CBC_SHA160\t\t 0xff80\n+#define OP_PCL_TLS10_AES_128_CBC_SHA224\t\t 0xff84\n+#define OP_PCL_TLS10_AES_128_CBC_SHA256\t\t 0xff86\n+#define OP_PCL_TLS10_AES_128_CBC_SHA384\t\t 0xff83\n+#define OP_PCL_TLS10_AES_128_CBC_SHA512\t\t 0xff85\n+#define OP_PCL_TLS10_AES_192_CBC_SHA160\t\t 0xff20\n+#define OP_PCL_TLS10_AES_192_CBC_SHA224\t\t 0xff24\n+#define OP_PCL_TLS10_AES_192_CBC_SHA256\t\t 0xff26\n+#define OP_PCL_TLS10_AES_192_CBC_SHA384\t\t 0xff23\n+#define OP_PCL_TLS10_AES_192_CBC_SHA512\t\t 0xff25\n+#define OP_PCL_TLS10_AES_256_CBC_SHA160\t\t 0xff60\n+#define OP_PCL_TLS10_AES_256_CBC_SHA224\t\t 0xff64\n+#define OP_PCL_TLS10_AES_256_CBC_SHA256\t\t 0xff66\n+#define OP_PCL_TLS10_AES_256_CBC_SHA384\t\t 0xff63\n+#define OP_PCL_TLS10_AES_256_CBC_SHA512\t\t 0xff65\n+\n+#define OP_PCL_TLS_PVT_AES_192_CBC_SHA160\t 0xff90\n+#define OP_PCL_TLS_PVT_AES_192_CBC_SHA384\t 0xff93\n+#define OP_PCL_TLS_PVT_AES_192_CBC_SHA224\t 0xff94\n+#define OP_PCL_TLS_PVT_AES_192_CBC_SHA512\t 0xff95\n+#define OP_PCL_TLS_PVT_AES_192_CBC_SHA256\t 0xff96\n+#define OP_PCL_TLS_PVT_MASTER_SECRET_PRF_FE\t 0xfffe\n+#define OP_PCL_TLS_PVT_MASTER_SECRET_PRF_FF\t 0xffff\n+\n+\n+/* For TLS 1.1 - OP_PCLID_TLS11 */\n+#define OP_PCL_TLS11_AES_128_CBC_SHA\t\t 0x002f\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_2\t\t 0x0030\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_3\t\t 0x0031\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_4\t\t 0x0032\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_5\t\t 0x0033\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_6\t\t 0x0034\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_7\t\t 0x008c\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_8\t\t 0x0090\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_9\t\t 0x0094\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_10\t\t 0xc004\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_11\t\t 0xc009\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_12\t\t 0xc00e\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_13\t\t 0xc013\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_14\t\t 0xc018\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_15\t\t 0xc01d\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_16\t\t 0xc01e\n+#define OP_PCL_TLS11_AES_128_CBC_SHA_17\t\t 0xc01f\n+\n+#define OP_PCL_TLS11_AES_256_CBC_SHA\t\t 0x0035\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_2\t\t 0x0036\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_3\t\t 0x0037\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_4\t\t 0x0038\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_5\t\t 0x0039\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_6\t\t 0x003a\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_7\t\t 0x008d\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_8\t\t 0x0091\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_9\t\t 0x0095\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_10\t\t 0xc005\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_11\t\t 0xc00a\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_12\t\t 0xc00f\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_13\t\t 0xc014\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_14\t\t 0xc019\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_15\t\t 0xc020\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_16\t\t 0xc021\n+#define OP_PCL_TLS11_AES_256_CBC_SHA_17\t\t 0xc022\n+\n+/* #define OP_PCL_TLS11_3DES_EDE_CBC_MD5\t0x0023 */\n+\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA\t\t 0x001f\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_2\t\t 0x008b\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_3\t\t 0x008f\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_4\t\t 0x0093\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_5\t\t 0x000a\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_6\t\t 0x000d\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_7\t\t 0x0010\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_8\t\t 0x0013\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_9\t\t 0x0016\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_10\t 0x001b\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_11\t 0xc003\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_12\t 0xc008\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_13\t 0xc00d\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_14\t 0xc012\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_15\t 0xc017\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_16\t 0xc01a\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_17\t 0xc01b\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA_18\t 0xc01c\n+\n+#define OP_PCL_TLS11_DES40_CBC_MD5\t\t 0x0029\n+\n+#define OP_PCL_TLS11_DES_CBC_MD5\t\t 0x0022\n+\n+#define OP_PCL_TLS11_DES40_CBC_SHA\t\t 0x0008\n+#define OP_PCL_TLS11_DES40_CBC_SHA_2\t\t 0x000b\n+#define OP_PCL_TLS11_DES40_CBC_SHA_3\t\t 0x000e\n+#define OP_PCL_TLS11_DES40_CBC_SHA_4\t\t 0x0011\n+#define OP_PCL_TLS11_DES40_CBC_SHA_5\t\t 0x0014\n+#define OP_PCL_TLS11_DES40_CBC_SHA_6\t\t 0x0019\n+#define OP_PCL_TLS11_DES40_CBC_SHA_7\t\t 0x0026\n+\n+#define OP_PCL_TLS11_DES_CBC_SHA\t\t 0x001e\n+#define OP_PCL_TLS11_DES_CBC_SHA_2\t\t 0x0009\n+#define OP_PCL_TLS11_DES_CBC_SHA_3\t\t 0x000c\n+#define OP_PCL_TLS11_DES_CBC_SHA_4\t\t 0x000f\n+#define OP_PCL_TLS11_DES_CBC_SHA_5\t\t 0x0012\n+#define OP_PCL_TLS11_DES_CBC_SHA_6\t\t 0x0015\n+#define OP_PCL_TLS11_DES_CBC_SHA_7\t\t 0x001a\n+\n+#define OP_PCL_TLS11_RC4_128_MD5\t\t 0x0024\n+#define OP_PCL_TLS11_RC4_128_MD5_2\t\t 0x0004\n+#define OP_PCL_TLS11_RC4_128_MD5_3\t\t 0x0018\n+\n+#define OP_PCL_TLS11_RC4_40_MD5\t\t\t 0x002b\n+#define OP_PCL_TLS11_RC4_40_MD5_2\t\t 0x0003\n+#define OP_PCL_TLS11_RC4_40_MD5_3\t\t 0x0017\n+\n+#define OP_PCL_TLS11_RC4_128_SHA\t\t 0x0020\n+#define OP_PCL_TLS11_RC4_128_SHA_2\t\t 0x008a\n+#define OP_PCL_TLS11_RC4_128_SHA_3\t\t 0x008e\n+#define OP_PCL_TLS11_RC4_128_SHA_4\t\t 0x0092\n+#define OP_PCL_TLS11_RC4_128_SHA_5\t\t 0x0005\n+#define OP_PCL_TLS11_RC4_128_SHA_6\t\t 0xc002\n+#define OP_PCL_TLS11_RC4_128_SHA_7\t\t 0xc007\n+#define OP_PCL_TLS11_RC4_128_SHA_8\t\t 0xc00c\n+#define OP_PCL_TLS11_RC4_128_SHA_9\t\t 0xc011\n+#define OP_PCL_TLS11_RC4_128_SHA_10\t\t 0xc016\n+\n+#define OP_PCL_TLS11_RC4_40_SHA\t\t\t 0x0028\n+\n+#define OP_PCL_TLS11_3DES_EDE_CBC_MD5\t\t 0xff23\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA160\t 0xff30\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA224\t 0xff34\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA256\t 0xff36\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA384\t 0xff33\n+#define OP_PCL_TLS11_3DES_EDE_CBC_SHA512\t 0xff35\n+#define OP_PCL_TLS11_AES_128_CBC_SHA160\t\t 0xff80\n+#define OP_PCL_TLS11_AES_128_CBC_SHA224\t\t 0xff84\n+#define OP_PCL_TLS11_AES_128_CBC_SHA256\t\t 0xff86\n+#define OP_PCL_TLS11_AES_128_CBC_SHA384\t\t 0xff83\n+#define OP_PCL_TLS11_AES_128_CBC_SHA512\t\t 0xff85\n+#define OP_PCL_TLS11_AES_192_CBC_SHA160\t\t 0xff20\n+#define OP_PCL_TLS11_AES_192_CBC_SHA224\t\t 0xff24\n+#define OP_PCL_TLS11_AES_192_CBC_SHA256\t\t 0xff26\n+#define OP_PCL_TLS11_AES_192_CBC_SHA384\t\t 0xff23\n+#define OP_PCL_TLS11_AES_192_CBC_SHA512\t\t 0xff25\n+#define OP_PCL_TLS11_AES_256_CBC_SHA160\t\t 0xff60\n+#define OP_PCL_TLS11_AES_256_CBC_SHA224\t\t 0xff64\n+#define OP_PCL_TLS11_AES_256_CBC_SHA256\t\t 0xff66\n+#define OP_PCL_TLS11_AES_256_CBC_SHA384\t\t 0xff63\n+#define OP_PCL_TLS11_AES_256_CBC_SHA512\t\t 0xff65\n+\n+\n+/* For TLS 1.2 - OP_PCLID_TLS12 */\n+#define OP_PCL_TLS12_AES_128_CBC_SHA\t\t 0x002f\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_2\t\t 0x0030\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_3\t\t 0x0031\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_4\t\t 0x0032\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_5\t\t 0x0033\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_6\t\t 0x0034\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_7\t\t 0x008c\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_8\t\t 0x0090\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_9\t\t 0x0094\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_10\t\t 0xc004\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_11\t\t 0xc009\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_12\t\t 0xc00e\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_13\t\t 0xc013\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_14\t\t 0xc018\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_15\t\t 0xc01d\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_16\t\t 0xc01e\n+#define OP_PCL_TLS12_AES_128_CBC_SHA_17\t\t 0xc01f\n+\n+#define OP_PCL_TLS12_AES_256_CBC_SHA\t\t 0x0035\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_2\t\t 0x0036\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_3\t\t 0x0037\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_4\t\t 0x0038\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_5\t\t 0x0039\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_6\t\t 0x003a\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_7\t\t 0x008d\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_8\t\t 0x0091\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_9\t\t 0x0095\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_10\t\t 0xc005\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_11\t\t 0xc00a\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_12\t\t 0xc00f\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_13\t\t 0xc014\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_14\t\t 0xc019\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_15\t\t 0xc020\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_16\t\t 0xc021\n+#define OP_PCL_TLS12_AES_256_CBC_SHA_17\t\t 0xc022\n+\n+/* #define OP_PCL_TLS12_3DES_EDE_CBC_MD5\t0x0023 */\n+\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA\t\t 0x001f\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_2\t\t 0x008b\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_3\t\t 0x008f\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_4\t\t 0x0093\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_5\t\t 0x000a\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_6\t\t 0x000d\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_7\t\t 0x0010\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_8\t\t 0x0013\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_9\t\t 0x0016\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_10\t 0x001b\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_11\t 0xc003\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_12\t 0xc008\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_13\t 0xc00d\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_14\t 0xc012\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_15\t 0xc017\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_16\t 0xc01a\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_17\t 0xc01b\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA_18\t 0xc01c\n+\n+#define OP_PCL_TLS12_DES40_CBC_MD5\t\t 0x0029\n+\n+#define OP_PCL_TLS12_DES_CBC_MD5\t\t 0x0022\n+\n+#define OP_PCL_TLS12_DES40_CBC_SHA\t\t 0x0008\n+#define OP_PCL_TLS12_DES40_CBC_SHA_2\t\t 0x000b\n+#define OP_PCL_TLS12_DES40_CBC_SHA_3\t\t 0x000e\n+#define OP_PCL_TLS12_DES40_CBC_SHA_4\t\t 0x0011\n+#define OP_PCL_TLS12_DES40_CBC_SHA_5\t\t 0x0014\n+#define OP_PCL_TLS12_DES40_CBC_SHA_6\t\t 0x0019\n+#define OP_PCL_TLS12_DES40_CBC_SHA_7\t\t 0x0026\n+\n+#define OP_PCL_TLS12_DES_CBC_SHA\t\t 0x001e\n+#define OP_PCL_TLS12_DES_CBC_SHA_2\t\t 0x0009\n+#define OP_PCL_TLS12_DES_CBC_SHA_3\t\t 0x000c\n+#define OP_PCL_TLS12_DES_CBC_SHA_4\t\t 0x000f\n+#define OP_PCL_TLS12_DES_CBC_SHA_5\t\t 0x0012\n+#define OP_PCL_TLS12_DES_CBC_SHA_6\t\t 0x0015\n+#define OP_PCL_TLS12_DES_CBC_SHA_7\t\t 0x001a\n+\n+#define OP_PCL_TLS12_RC4_128_MD5\t\t 0x0024\n+#define OP_PCL_TLS12_RC4_128_MD5_2\t\t 0x0004\n+#define OP_PCL_TLS12_RC4_128_MD5_3\t\t 0x0018\n+\n+#define OP_PCL_TLS12_RC4_40_MD5\t\t\t 0x002b\n+#define OP_PCL_TLS12_RC4_40_MD5_2\t\t 0x0003\n+#define OP_PCL_TLS12_RC4_40_MD5_3\t\t 0x0017\n+\n+#define OP_PCL_TLS12_RC4_128_SHA\t\t 0x0020\n+#define OP_PCL_TLS12_RC4_128_SHA_2\t\t 0x008a\n+#define OP_PCL_TLS12_RC4_128_SHA_3\t\t 0x008e\n+#define OP_PCL_TLS12_RC4_128_SHA_4\t\t 0x0092\n+#define OP_PCL_TLS12_RC4_128_SHA_5\t\t 0x0005\n+#define OP_PCL_TLS12_RC4_128_SHA_6\t\t 0xc002\n+#define OP_PCL_TLS12_RC4_128_SHA_7\t\t 0xc007\n+#define OP_PCL_TLS12_RC4_128_SHA_8\t\t 0xc00c\n+#define OP_PCL_TLS12_RC4_128_SHA_9\t\t 0xc011\n+#define OP_PCL_TLS12_RC4_128_SHA_10\t\t 0xc016\n+\n+#define OP_PCL_TLS12_RC4_40_SHA\t\t\t 0x0028\n+\n+/* #define OP_PCL_TLS12_AES_128_CBC_SHA256\t0x003c */\n+#define OP_PCL_TLS12_AES_128_CBC_SHA256_2\t 0x003e\n+#define OP_PCL_TLS12_AES_128_CBC_SHA256_3\t 0x003f\n+#define OP_PCL_TLS12_AES_128_CBC_SHA256_4\t 0x0040\n+#define OP_PCL_TLS12_AES_128_CBC_SHA256_5\t 0x0067\n+#define OP_PCL_TLS12_AES_128_CBC_SHA256_6\t 0x006c\n+\n+/* #define OP_PCL_TLS12_AES_256_CBC_SHA256\t0x003d */\n+#define OP_PCL_TLS12_AES_256_CBC_SHA256_2\t 0x0068\n+#define OP_PCL_TLS12_AES_256_CBC_SHA256_3\t 0x0069\n+#define OP_PCL_TLS12_AES_256_CBC_SHA256_4\t 0x006a\n+#define OP_PCL_TLS12_AES_256_CBC_SHA256_5\t 0x006b\n+#define OP_PCL_TLS12_AES_256_CBC_SHA256_6\t 0x006d\n+\n+/* AEAD_AES_xxx_CCM/GCM remain to be defined... */\n+\n+#define OP_PCL_TLS12_3DES_EDE_CBC_MD5\t\t 0xff23\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA160\t 0xff30\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA224\t 0xff34\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA256\t 0xff36\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA384\t 0xff33\n+#define OP_PCL_TLS12_3DES_EDE_CBC_SHA512\t 0xff35\n+#define OP_PCL_TLS12_AES_128_CBC_SHA160\t\t 0xff80\n+#define OP_PCL_TLS12_AES_128_CBC_SHA224\t\t 0xff84\n+#define OP_PCL_TLS12_AES_128_CBC_SHA256\t\t 0xff86\n+#define OP_PCL_TLS12_AES_128_CBC_SHA384\t\t 0xff83\n+#define OP_PCL_TLS12_AES_128_CBC_SHA512\t\t 0xff85\n+#define OP_PCL_TLS12_AES_192_CBC_SHA160\t\t 0xff20\n+#define OP_PCL_TLS12_AES_192_CBC_SHA224\t\t 0xff24\n+#define OP_PCL_TLS12_AES_192_CBC_SHA256\t\t 0xff26\n+#define OP_PCL_TLS12_AES_192_CBC_SHA384\t\t 0xff23\n+#define OP_PCL_TLS12_AES_192_CBC_SHA512\t\t 0xff25\n+#define OP_PCL_TLS12_AES_256_CBC_SHA160\t\t 0xff60\n+#define OP_PCL_TLS12_AES_256_CBC_SHA224\t\t 0xff64\n+#define OP_PCL_TLS12_AES_256_CBC_SHA256\t\t 0xff66\n+#define OP_PCL_TLS12_AES_256_CBC_SHA384\t\t 0xff63\n+#define OP_PCL_TLS12_AES_256_CBC_SHA512\t\t 0xff65\n+\n+/* For DTLS - OP_PCLID_DTLS */\n+\n+#define OP_PCL_DTLS_AES_128_CBC_SHA\t\t 0x002f\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_2\t\t 0x0030\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_3\t\t 0x0031\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_4\t\t 0x0032\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_5\t\t 0x0033\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_6\t\t 0x0034\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_7\t\t 0x008c\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_8\t\t 0x0090\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_9\t\t 0x0094\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_10\t\t 0xc004\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_11\t\t 0xc009\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_12\t\t 0xc00e\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_13\t\t 0xc013\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_14\t\t 0xc018\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_15\t\t 0xc01d\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_16\t\t 0xc01e\n+#define OP_PCL_DTLS_AES_128_CBC_SHA_17\t\t 0xc01f\n+\n+#define OP_PCL_DTLS_AES_256_CBC_SHA\t\t 0x0035\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_2\t\t 0x0036\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_3\t\t 0x0037\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_4\t\t 0x0038\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_5\t\t 0x0039\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_6\t\t 0x003a\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_7\t\t 0x008d\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_8\t\t 0x0091\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_9\t\t 0x0095\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_10\t\t 0xc005\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_11\t\t 0xc00a\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_12\t\t 0xc00f\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_13\t\t 0xc014\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_14\t\t 0xc019\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_15\t\t 0xc020\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_16\t\t 0xc021\n+#define OP_PCL_DTLS_AES_256_CBC_SHA_17\t\t 0xc022\n+\n+/* #define OP_PCL_DTLS_3DES_EDE_CBC_MD5\t\t0x0023 */\n+\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA\t\t 0x001f\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_2\t\t 0x008b\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_3\t\t 0x008f\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_4\t\t 0x0093\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_5\t\t 0x000a\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_6\t\t 0x000d\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_7\t\t 0x0010\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_8\t\t 0x0013\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_9\t\t 0x0016\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_10\t\t 0x001b\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_11\t\t 0xc003\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_12\t\t 0xc008\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_13\t\t 0xc00d\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_14\t\t 0xc012\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_15\t\t 0xc017\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_16\t\t 0xc01a\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_17\t\t 0xc01b\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA_18\t\t 0xc01c\n+\n+#define OP_PCL_DTLS_DES40_CBC_MD5\t\t 0x0029\n+\n+#define OP_PCL_DTLS_DES_CBC_MD5\t\t\t 0x0022\n+\n+#define OP_PCL_DTLS_DES40_CBC_SHA\t\t 0x0008\n+#define OP_PCL_DTLS_DES40_CBC_SHA_2\t\t 0x000b\n+#define OP_PCL_DTLS_DES40_CBC_SHA_3\t\t 0x000e\n+#define OP_PCL_DTLS_DES40_CBC_SHA_4\t\t 0x0011\n+#define OP_PCL_DTLS_DES40_CBC_SHA_5\t\t 0x0014\n+#define OP_PCL_DTLS_DES40_CBC_SHA_6\t\t 0x0019\n+#define OP_PCL_DTLS_DES40_CBC_SHA_7\t\t 0x0026\n+\n+\n+#define OP_PCL_DTLS_DES_CBC_SHA\t\t\t 0x001e\n+#define OP_PCL_DTLS_DES_CBC_SHA_2\t\t 0x0009\n+#define OP_PCL_DTLS_DES_CBC_SHA_3\t\t 0x000c\n+#define OP_PCL_DTLS_DES_CBC_SHA_4\t\t 0x000f\n+#define OP_PCL_DTLS_DES_CBC_SHA_5\t\t 0x0012\n+#define OP_PCL_DTLS_DES_CBC_SHA_6\t\t 0x0015\n+#define OP_PCL_DTLS_DES_CBC_SHA_7\t\t 0x001a\n+\n+#define OP_PCL_DTLS_3DES_EDE_CBC_MD5\t\t 0xff23\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA160\t\t 0xff30\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA224\t\t 0xff34\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA256\t\t 0xff36\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA384\t\t 0xff33\n+#define OP_PCL_DTLS_3DES_EDE_CBC_SHA512\t\t 0xff35\n+#define OP_PCL_DTLS_AES_128_CBC_SHA160\t\t 0xff80\n+#define OP_PCL_DTLS_AES_128_CBC_SHA224\t\t 0xff84\n+#define OP_PCL_DTLS_AES_128_CBC_SHA256\t\t 0xff86\n+#define OP_PCL_DTLS_AES_128_CBC_SHA384\t\t 0xff83\n+#define OP_PCL_DTLS_AES_128_CBC_SHA512\t\t 0xff85\n+#define OP_PCL_DTLS_AES_192_CBC_SHA160\t\t 0xff20\n+#define OP_PCL_DTLS_AES_192_CBC_SHA224\t\t 0xff24\n+#define OP_PCL_DTLS_AES_192_CBC_SHA256\t\t 0xff26\n+#define OP_PCL_DTLS_AES_192_CBC_SHA384\t\t 0xff23\n+#define OP_PCL_DTLS_AES_192_CBC_SHA512\t\t 0xff25\n+#define OP_PCL_DTLS_AES_256_CBC_SHA160\t\t 0xff60\n+#define OP_PCL_DTLS_AES_256_CBC_SHA224\t\t 0xff64\n+#define OP_PCL_DTLS_AES_256_CBC_SHA256\t\t 0xff66\n+#define OP_PCL_DTLS_AES_256_CBC_SHA384\t\t 0xff63\n+#define OP_PCL_DTLS_AES_256_CBC_SHA512\t\t 0xff65\n+\n+/* 802.16 WiMAX protinfos */\n+#define OP_PCL_WIMAX_OFDM\t\t\t 0x0201\n+#define OP_PCL_WIMAX_OFDMA\t\t\t 0x0231\n+\n+/* 802.11 WiFi protinfos */\n+#define OP_PCL_WIFI\t\t\t\t 0xac04\n+\n+/* MacSec protinfos */\n+#define OP_PCL_MACSEC\t\t\t\t 0x0001\n+\n+/* 3G DCRC protinfos */\n+#define OP_PCL_3G_DCRC_CRC7\t\t\t 0x0710\n+#define OP_PCL_3G_DCRC_CRC11\t\t\t 0x0B10\n+\n+/* 3G RLC protinfos */\n+#define OP_PCL_3G_RLC_NULL\t\t\t 0x0000\n+#define OP_PCL_3G_RLC_KASUMI\t\t\t 0x0001\n+#define OP_PCL_3G_RLC_SNOW\t\t\t 0x0002\n+\n+/* LTE protinfos */\n+#define OP_PCL_LTE_NULL\t\t\t\t 0x0000\n+#define OP_PCL_LTE_SNOW\t\t\t\t 0x0001\n+#define OP_PCL_LTE_AES\t\t\t\t 0x0002\n+#define OP_PCL_LTE_ZUC\t\t\t\t 0x0003\n+\n+/* LTE mixed protinfos */\n+#define OP_PCL_LTE_MIXED_AUTH_SHIFT\t0\n+#define OP_PCL_LTE_MIXED_AUTH_MASK\t(3 << OP_PCL_LTE_MIXED_AUTH_SHIFT)\n+#define OP_PCL_LTE_MIXED_ENC_SHIFT\t8\n+#define OP_PCL_LTE_MIXED_ENC_MASK\t(3 < OP_PCL_LTE_MIXED_ENC_SHIFT)\n+#define OP_PCL_LTE_MIXED_AUTH_NULL\t(OP_PCL_LTE_NULL << \\\n+\t\t\t\t\t OP_PCL_LTE_MIXED_AUTH_SHIFT)\n+#define OP_PCL_LTE_MIXED_AUTH_SNOW\t(OP_PCL_LTE_SNOW << \\\n+\t\t\t\t\t OP_PCL_LTE_MIXED_AUTH_SHIFT)\n+#define OP_PCL_LTE_MIXED_AUTH_AES\t(OP_PCL_LTE_AES << \\\n+\t\t\t\t\t OP_PCL_LTE_MIXED_AUTH_SHIFT)\n+#define OP_PCL_LTE_MIXED_AUTH_ZUC\t(OP_PCL_LTE_ZUC << \\\n+\t\t\t\t\t OP_PCL_LTE_MIXED_AUTH_SHIFT)\n+#define OP_PCL_LTE_MIXED_ENC_NULL\t(OP_PCL_LTE_NULL << \\\n+\t\t\t\t\t OP_PCL_LTE_MIXED_ENC_SHIFT)\n+#define OP_PCL_LTE_MIXED_ENC_SNOW\t(OP_PCL_LTE_SNOW << \\\n+\t\t\t\t\t OP_PCL_LTE_MIXED_ENC_SHIFT)\n+#define OP_PCL_LTE_MIXED_ENC_AES\t(OP_PCL_LTE_AES << \\\n+\t\t\t\t\t OP_PCL_LTE_MIXED_ENC_SHIFT)\n+#define OP_PCL_LTE_MIXED_ENC_ZUC\t(OP_PCL_LTE_ZUC << \\\n+\t\t\t\t\t OP_PCL_LTE_MIXED_ENC_SHIFT)\n+\n+/* PKI unidirectional protocol protinfo bits */\n+#define OP_PCL_PKPROT_DSA_MSG\t\tBIT(10)\n+#define OP_PCL_PKPROT_HASH_SHIFT\t7\n+#define OP_PCL_PKPROT_HASH_MASK\t\t(7 << OP_PCL_PKPROT_HASH_SHIFT)\n+#define OP_PCL_PKPROT_HASH_MD5\t\t(0 << OP_PCL_PKPROT_HASH_SHIFT)\n+#define OP_PCL_PKPROT_HASH_SHA1\t\t(1 << OP_PCL_PKPROT_HASH_SHIFT)\n+#define OP_PCL_PKPROT_HASH_SHA224\t(2 << OP_PCL_PKPROT_HASH_SHIFT)\n+#define OP_PCL_PKPROT_HASH_SHA256\t(3 << OP_PCL_PKPROT_HASH_SHIFT)\n+#define OP_PCL_PKPROT_HASH_SHA384\t(4 << OP_PCL_PKPROT_HASH_SHIFT)\n+#define OP_PCL_PKPROT_HASH_SHA512\t(5 << OP_PCL_PKPROT_HASH_SHIFT)\n+#define OP_PCL_PKPROT_EKT_Z\t\tBIT(6)\n+#define OP_PCL_PKPROT_DECRYPT_Z\t\tBIT(5)\n+#define OP_PCL_PKPROT_EKT_PRI\t\tBIT(4)\n+#define OP_PCL_PKPROT_TEST\t\tBIT(3)\n+#define OP_PCL_PKPROT_DECRYPT_PRI\tBIT(2)\n+#define OP_PCL_PKPROT_ECC\t\tBIT(1)\n+#define OP_PCL_PKPROT_F2M\t\tBIT(0)\n+\n+/* Blob protinfos */\n+#define OP_PCL_BLOB_TKEK_SHIFT\t\t9\n+#define OP_PCL_BLOB_TKEK\t\tBIT(9)\n+#define OP_PCL_BLOB_EKT_SHIFT\t\t8\n+#define OP_PCL_BLOB_EKT\t\t\tBIT(8)\n+#define OP_PCL_BLOB_REG_SHIFT\t\t4\n+#define OP_PCL_BLOB_REG_MASK\t\t(0xF << OP_PCL_BLOB_REG_SHIFT)\n+#define OP_PCL_BLOB_REG_MEMORY\t\t(0x0 << OP_PCL_BLOB_REG_SHIFT)\n+#define OP_PCL_BLOB_REG_KEY1\t\t(0x1 << OP_PCL_BLOB_REG_SHIFT)\n+#define OP_PCL_BLOB_REG_KEY2\t\t(0x3 << OP_PCL_BLOB_REG_SHIFT)\n+#define OP_PCL_BLOB_AFHA_SBOX\t\t(0x5 << OP_PCL_BLOB_REG_SHIFT)\n+#define OP_PCL_BLOB_REG_SPLIT\t\t(0x7 << OP_PCL_BLOB_REG_SHIFT)\n+#define OP_PCL_BLOB_REG_PKE\t\t(0x9 << OP_PCL_BLOB_REG_SHIFT)\n+#define OP_PCL_BLOB_SEC_MEM_SHIFT\t3\n+#define OP_PCL_BLOB_SEC_MEM\t\tBIT(3)\n+#define OP_PCL_BLOB_BLACK\t\tBIT(2)\n+#define OP_PCL_BLOB_FORMAT_SHIFT\t0\n+#define OP_PCL_BLOB_FORMAT_MASK\t\t0x3\n+#define OP_PCL_BLOB_FORMAT_NORMAL\t0\n+#define OP_PCL_BLOB_FORMAT_MASTER_VER\t2\n+#define OP_PCL_BLOB_FORMAT_TEST\t\t3\n+\n+/* IKE / IKEv2 protinfos */\n+#define OP_PCL_IKE_HMAC_MD5\t\t0x0100\n+#define OP_PCL_IKE_HMAC_SHA1\t\t0x0200\n+#define OP_PCL_IKE_HMAC_AES128_CBC\t0x0400\n+#define OP_PCL_IKE_HMAC_SHA256\t\t0x0500\n+#define OP_PCL_IKE_HMAC_SHA384\t\t0x0600\n+#define OP_PCL_IKE_HMAC_SHA512\t\t0x0700\n+#define OP_PCL_IKE_HMAC_AES128_CMAC\t0x0800\n+\n+/* PKI unidirectional protocol protinfo bits */\n+#define OP_PCL_PKPROT_TEST\t\tBIT(3)\n+#define OP_PCL_PKPROT_DECRYPT\t\tBIT(2)\n+#define OP_PCL_PKPROT_ECC\t\tBIT(1)\n+#define OP_PCL_PKPROT_F2M\t\tBIT(0)\n+\n+/* RSA Protinfo */\n+#define OP_PCL_RSAPROT_OP_MASK\t\t3\n+#define OP_PCL_RSAPROT_OP_ENC_F_IN\t0\n+#define OP_PCL_RSAPROT_OP_ENC_F_OUT\t1\n+#define OP_PCL_RSAPROT_OP_DEC_ND\t0\n+#define OP_PCL_RSAPROT_OP_DEC_PQD\t1\n+#define OP_PCL_RSAPROT_OP_DEC_PQDPDQC\t2\n+#define OP_PCL_RSAPROT_FFF_SHIFT\t4\n+#define OP_PCL_RSAPROT_FFF_MASK\t\t(7 << OP_PCL_RSAPROT_FFF_SHIFT)\n+#define OP_PCL_RSAPROT_FFF_RED\t\t(0 << OP_PCL_RSAPROT_FFF_SHIFT)\n+#define OP_PCL_RSAPROT_FFF_ENC\t\t(1 << OP_PCL_RSAPROT_FFF_SHIFT)\n+#define OP_PCL_RSAPROT_FFF_TK_ENC\t(5 << OP_PCL_RSAPROT_FFF_SHIFT)\n+#define OP_PCL_RSAPROT_FFF_EKT\t\t(3 << OP_PCL_RSAPROT_FFF_SHIFT)\n+#define OP_PCL_RSAPROT_FFF_TK_EKT\t(7 << OP_PCL_RSAPROT_FFF_SHIFT)\n+#define OP_PCL_RSAPROT_PPP_SHIFT\t8\n+#define OP_PCL_RSAPROT_PPP_MASK\t\t(7 << OP_PCL_RSAPROT_PPP_SHIFT)\n+#define OP_PCL_RSAPROT_PPP_RED\t\t(0 << OP_PCL_RSAPROT_PPP_SHIFT)\n+#define OP_PCL_RSAPROT_PPP_ENC\t\t(1 << OP_PCL_RSAPROT_PPP_SHIFT)\n+#define OP_PCL_RSAPROT_PPP_TK_ENC\t(5 << OP_PCL_RSAPROT_PPP_SHIFT)\n+#define OP_PCL_RSAPROT_PPP_EKT\t\t(3 << OP_PCL_RSAPROT_PPP_SHIFT)\n+#define OP_PCL_RSAPROT_PPP_TK_EKT\t(7 << OP_PCL_RSAPROT_PPP_SHIFT)\n+#define OP_PCL_RSAPROT_FMT_PKCSV15\tBIT(12)\n+\n+/* Derived Key Protocol (DKP) Protinfo */\n+#define OP_PCL_DKP_SRC_SHIFT\t14\n+#define OP_PCL_DKP_SRC_MASK\t(3 << OP_PCL_DKP_SRC_SHIFT)\n+#define OP_PCL_DKP_SRC_IMM\t(0 << OP_PCL_DKP_SRC_SHIFT)\n+#define OP_PCL_DKP_SRC_SEQ\t(1 << OP_PCL_DKP_SRC_SHIFT)\n+#define OP_PCL_DKP_SRC_PTR\t(2 << OP_PCL_DKP_SRC_SHIFT)\n+#define OP_PCL_DKP_SRC_SGF\t(3 << OP_PCL_DKP_SRC_SHIFT)\n+#define OP_PCL_DKP_DST_SHIFT\t12\n+#define OP_PCL_DKP_DST_MASK\t(3 << OP_PCL_DKP_DST_SHIFT)\n+#define OP_PCL_DKP_DST_IMM\t(0 << OP_PCL_DKP_DST_SHIFT)\n+#define OP_PCL_DKP_DST_SEQ\t(1 << OP_PCL_DKP_DST_SHIFT)\n+#define OP_PCL_DKP_DST_PTR\t(2 << OP_PCL_DKP_DST_SHIFT)\n+#define OP_PCL_DKP_DST_SGF\t(3 << OP_PCL_DKP_DST_SHIFT)\n+#define OP_PCL_DKP_KEY_SHIFT\t0\n+#define OP_PCL_DKP_KEY_MASK\t(0xfff << OP_PCL_DKP_KEY_SHIFT)\n+\n+/* For non-protocol/alg-only op commands */\n+#define OP_ALG_TYPE_SHIFT\t24\n+#define OP_ALG_TYPE_MASK\t(0x7 << OP_ALG_TYPE_SHIFT)\n+#define OP_ALG_TYPE_CLASS1\t(0x2 << OP_ALG_TYPE_SHIFT)\n+#define OP_ALG_TYPE_CLASS2\t(0x4 << OP_ALG_TYPE_SHIFT)\n+\n+#define OP_ALG_ALGSEL_SHIFT\t16\n+#define OP_ALG_ALGSEL_MASK\t(0xff << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_SUBMASK\t(0x0f << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_AES\t(0x10 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_DES\t(0x20 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_3DES\t(0x21 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_ARC4\t(0x30 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_MD5\t(0x40 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_SHA1\t(0x41 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_SHA224\t(0x42 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_SHA256\t(0x43 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_SHA384\t(0x44 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_SHA512\t(0x45 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_RNG\t(0x50 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_SNOW_F8\t(0x60 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_KASUMI\t(0x70 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_CRC\t(0x90 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_SNOW_F9\t(0xA0 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_ZUCE\t(0xB0 << OP_ALG_ALGSEL_SHIFT)\n+#define OP_ALG_ALGSEL_ZUCA\t(0xC0 << OP_ALG_ALGSEL_SHIFT)\n+\n+#define OP_ALG_AAI_SHIFT\t4\n+#define OP_ALG_AAI_MASK\t\t(0x3ff << OP_ALG_AAI_SHIFT)\n+\n+/* block cipher AAI set */\n+#define OP_ALG_AESA_MODE_MASK\t(0xF0 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR\t\t(0x00 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD128\t(0x00 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD8\t(0x01 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD16\t(0x02 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD24\t(0x03 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD32\t(0x04 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD40\t(0x05 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD48\t(0x06 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD56\t(0x07 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD64\t(0x08 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD72\t(0x09 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD80\t(0x0a << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD88\t(0x0b << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD96\t(0x0c << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD104\t(0x0d << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD112\t(0x0e << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_MOD120\t(0x0f << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CBC\t\t(0x10 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_ECB\t\t(0x20 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CFB\t\t(0x30 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_OFB\t\t(0x40 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_XTS\t\t(0x50 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CMAC\t\t(0x60 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_XCBC_MAC\t(0x70 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CCM\t\t(0x80 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_GCM\t\t(0x90 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CBC_XCBCMAC\t(0xa0 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_XCBCMAC\t(0xb0 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CBC_CMAC\t(0xc0 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_CMAC_LTE (0xd0 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CTR_CMAC\t(0xe0 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CHECKODD\t(0x80 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_DK\t\t(0x100 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_C2K\t\t(0x200 << OP_ALG_AAI_SHIFT)\n+\n+/* randomizer AAI set */\n+#define OP_ALG_RNG_MODE_MASK\t(0x30 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_RNG\t\t(0x00 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_RNG_NZB\t(0x10 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_RNG_OBP\t(0x20 << OP_ALG_AAI_SHIFT)\n+\n+/* RNG4 AAI set */\n+#define OP_ALG_AAI_RNG4_SH_SHIFT OP_ALG_AAI_SHIFT\n+#define OP_ALG_AAI_RNG4_SH_MASK\t(0x03 << OP_ALG_AAI_RNG4_SH_SHIFT)\n+#define OP_ALG_AAI_RNG4_SH_0\t(0x00 << OP_ALG_AAI_RNG4_SH_SHIFT)\n+#define OP_ALG_AAI_RNG4_SH_1\t(0x01 << OP_ALG_AAI_RNG4_SH_SHIFT)\n+#define OP_ALG_AAI_RNG4_PS\t(0x40 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_RNG4_AI\t(0x80 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_RNG4_SK\t(0x100 << OP_ALG_AAI_SHIFT)\n+\n+/* hmac/smac AAI set */\n+#define OP_ALG_AAI_HASH\t\t(0x00 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_HMAC\t\t(0x01 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_SMAC\t\t(0x02 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_HMAC_PRECOMP\t(0x04 << OP_ALG_AAI_SHIFT)\n+\n+/* CRC AAI set*/\n+#define OP_ALG_CRC_POLY_MASK\t(0x07 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_802\t\t(0x01 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_3385\t\t(0x02 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_CUST_POLY\t(0x04 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_DIS\t\t(0x10 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_DOS\t\t(0x20 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_DOC\t\t(0x40 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_IVZ\t\t(0x80 << OP_ALG_AAI_SHIFT)\n+\n+/* Kasumi/SNOW/ZUC AAI set */\n+#define OP_ALG_AAI_F8\t\t(0xc0 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_F9\t\t(0xc8 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_GSM\t\t(0x10 << OP_ALG_AAI_SHIFT)\n+#define OP_ALG_AAI_EDGE\t\t(0x20 << OP_ALG_AAI_SHIFT)\n+\n+#define OP_ALG_AS_SHIFT\t\t2\n+#define OP_ALG_AS_MASK\t\t(0x3 << OP_ALG_AS_SHIFT)\n+#define OP_ALG_AS_UPDATE\t(0 << OP_ALG_AS_SHIFT)\n+#define OP_ALG_AS_INIT\t\t(1 << OP_ALG_AS_SHIFT)\n+#define OP_ALG_AS_FINALIZE\t(2 << OP_ALG_AS_SHIFT)\n+#define OP_ALG_AS_INITFINAL\t(3 << OP_ALG_AS_SHIFT)\n+\n+#define OP_ALG_ICV_SHIFT\t1\n+#define OP_ALG_ICV_MASK\t\t(1 << OP_ALG_ICV_SHIFT)\n+#define OP_ALG_ICV_OFF\t\t0\n+#define OP_ALG_ICV_ON\t\tBIT(1)\n+\n+#define OP_ALG_DIR_SHIFT\t0\n+#define OP_ALG_DIR_MASK\t\t1\n+#define OP_ALG_DECRYPT\t\t0\n+#define OP_ALG_ENCRYPT\t\tBIT(0)\n+\n+/* PKHA algorithm type set */\n+#define OP_ALG_PK\t\t\t0x00800000\n+#define OP_ALG_PK_FUN_MASK\t\t0x3f /* clrmem, modmath, or cpymem */\n+\n+/* PKHA mode clear memory functions */\n+#define OP_ALG_PKMODE_A_RAM\t\tBIT(19)\n+#define OP_ALG_PKMODE_B_RAM\t\tBIT(18)\n+#define OP_ALG_PKMODE_E_RAM\t\tBIT(17)\n+#define OP_ALG_PKMODE_N_RAM\t\tBIT(16)\n+#define OP_ALG_PKMODE_CLEARMEM\t\tBIT(0)\n+\n+/* PKHA mode clear memory functions */\n+#define OP_ALG_PKMODE_CLEARMEM_ALL\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_A_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_B_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_N_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_E_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_ABE\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_A_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_B_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_E_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_ABN\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_A_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_B_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_N_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_AB\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_A_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_B_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_AEN\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_A_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_E_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_N_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_AE\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_A_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_E_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_AN\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_A_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_N_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_A\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_A_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_BEN\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_B_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_E_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_N_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_BE\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_B_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_E_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_BN\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_B_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_N_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_B\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_B_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_EN\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_E_RAM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_N_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_E\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_E_RAM)\n+#define OP_ALG_PKMODE_CLEARMEM_N\t(OP_ALG_PKMODE_CLEARMEM | \\\n+\t\t\t\t\t OP_ALG_PKMODE_N_RAM)\n+\n+/* PKHA mode modular-arithmetic functions */\n+#define OP_ALG_PKMODE_MOD_IN_MONTY   BIT(19)\n+#define OP_ALG_PKMODE_MOD_OUT_MONTY  BIT(18)\n+#define OP_ALG_PKMODE_MOD_F2M\t     BIT(17)\n+#define OP_ALG_PKMODE_MOD_R2_IN\t     BIT(16)\n+#define OP_ALG_PKMODE_PRJECTV\t     BIT(11)\n+#define OP_ALG_PKMODE_TIME_EQ\t     BIT(10)\n+\n+#define OP_ALG_PKMODE_OUT_B\t     0x000\n+#define OP_ALG_PKMODE_OUT_A\t     0x100\n+\n+/*\n+ * PKHA mode modular-arithmetic integer functions\n+ * Can be ORed with OP_ALG_PKMODE_OUT_A to change destination from B\n+ */\n+#define OP_ALG_PKMODE_MOD_ADD\t     0x002\n+#define OP_ALG_PKMODE_MOD_SUB_AB     0x003\n+#define OP_ALG_PKMODE_MOD_SUB_BA     0x004\n+#define OP_ALG_PKMODE_MOD_MULT\t     0x005\n+#define OP_ALG_PKMODE_MOD_MULT_IM    (0x005 | OP_ALG_PKMODE_MOD_IN_MONTY)\n+#define OP_ALG_PKMODE_MOD_MULT_IM_OM (0x005 | OP_ALG_PKMODE_MOD_IN_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_OUT_MONTY)\n+#define OP_ALG_PKMODE_MOD_EXPO\t     0x006\n+#define OP_ALG_PKMODE_MOD_EXPO_TEQ   (0x006 | OP_ALG_PKMODE_TIME_EQ)\n+#define OP_ALG_PKMODE_MOD_EXPO_IM    (0x006 | OP_ALG_PKMODE_MOD_IN_MONTY)\n+#define OP_ALG_PKMODE_MOD_EXPO_IM_TEQ (0x006 | OP_ALG_PKMODE_MOD_IN_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_TIME_EQ)\n+#define OP_ALG_PKMODE_MOD_REDUCT     0x007\n+#define OP_ALG_PKMODE_MOD_INV\t     0x008\n+#define OP_ALG_PKMODE_MOD_ECC_ADD    0x009\n+#define OP_ALG_PKMODE_MOD_ECC_DBL    0x00a\n+#define OP_ALG_PKMODE_MOD_ECC_MULT   0x00b\n+#define OP_ALG_PKMODE_MOD_MONT_CNST  0x00c\n+#define OP_ALG_PKMODE_MOD_CRT_CNST   0x00d\n+#define OP_ALG_PKMODE_MOD_GCD\t     0x00e\n+#define OP_ALG_PKMODE_MOD_PRIMALITY  0x00f\n+#define OP_ALG_PKMODE_MOD_SML_EXP    0x016\n+\n+/*\n+ * PKHA mode modular-arithmetic F2m functions\n+ * Can be ORed with OP_ALG_PKMODE_OUT_A to change destination from B\n+ */\n+#define OP_ALG_PKMODE_F2M_ADD\t     (0x002 | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_F2M_MUL\t     (0x005 | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_F2M_MUL_IM     (0x005 | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_IN_MONTY)\n+#define OP_ALG_PKMODE_F2M_MUL_IM_OM  (0x005 | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_IN_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_OUT_MONTY)\n+#define OP_ALG_PKMODE_F2M_EXP\t     (0x006 | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_F2M_EXP_TEQ    (0x006 | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_TIME_EQ)\n+#define OP_ALG_PKMODE_F2M_AMODN\t     (0x007 | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_F2M_INV\t     (0x008 | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_F2M_R2\t     (0x00c | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_F2M_GCD\t     (0x00e | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_F2M_SML_EXP    (0x016 | OP_ALG_PKMODE_MOD_F2M)\n+\n+/*\n+ * PKHA mode ECC Integer arithmetic functions\n+ * Can be ORed with OP_ALG_PKMODE_OUT_A to change destination from B\n+ */\n+#define OP_ALG_PKMODE_ECC_MOD_ADD    0x009\n+#define OP_ALG_PKMODE_ECC_MOD_ADD_IM_OM_PROJ \\\n+\t\t\t\t     (0x009 | OP_ALG_PKMODE_MOD_IN_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_OUT_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_PRJECTV)\n+#define OP_ALG_PKMODE_ECC_MOD_DBL    0x00a\n+#define OP_ALG_PKMODE_ECC_MOD_DBL_IM_OM_PROJ \\\n+\t\t\t\t     (0x00a | OP_ALG_PKMODE_MOD_IN_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_OUT_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_PRJECTV)\n+#define OP_ALG_PKMODE_ECC_MOD_MUL    0x00b\n+#define OP_ALG_PKMODE_ECC_MOD_MUL_TEQ (0x00b | OP_ALG_PKMODE_TIME_EQ)\n+#define OP_ALG_PKMODE_ECC_MOD_MUL_R2  (0x00b | OP_ALG_PKMODE_MOD_R2_IN)\n+#define OP_ALG_PKMODE_ECC_MOD_MUL_R2_TEQ \\\n+\t\t\t\t     (0x00b | OP_ALG_PKMODE_MOD_R2_IN \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_TIME_EQ)\n+#define OP_ALG_PKMODE_ECC_MOD_MUL_R2_PROJ \\\n+\t\t\t\t     (0x00b | OP_ALG_PKMODE_MOD_R2_IN \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_PRJECTV)\n+#define OP_ALG_PKMODE_ECC_MOD_MUL_R2_PROJ_TEQ \\\n+\t\t\t\t     (0x00b | OP_ALG_PKMODE_MOD_R2_IN \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_PRJECTV \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_TIME_EQ)\n+\n+/*\n+ * PKHA mode ECC F2m arithmetic functions\n+ * Can be ORed with OP_ALG_PKMODE_OUT_A to change destination from B\n+ */\n+#define OP_ALG_PKMODE_ECC_F2M_ADD    (0x009 | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_ECC_F2M_ADD_IM_OM_PROJ \\\n+\t\t\t\t     (0x009 | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_IN_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_OUT_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_PRJECTV)\n+#define OP_ALG_PKMODE_ECC_F2M_DBL    (0x00a | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_ECC_F2M_DBL_IM_OM_PROJ \\\n+\t\t\t\t     (0x00a | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_IN_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_OUT_MONTY \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_PRJECTV)\n+#define OP_ALG_PKMODE_ECC_F2M_MUL    (0x00b | OP_ALG_PKMODE_MOD_F2M)\n+#define OP_ALG_PKMODE_ECC_F2M_MUL_TEQ \\\n+\t\t\t\t     (0x00b | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_TIME_EQ)\n+#define OP_ALG_PKMODE_ECC_F2M_MUL_R2 \\\n+\t\t\t\t     (0x00b | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_R2_IN)\n+#define OP_ALG_PKMODE_ECC_F2M_MUL_R2_TEQ \\\n+\t\t\t\t     (0x00b | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_R2_IN \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_TIME_EQ)\n+#define OP_ALG_PKMODE_ECC_F2M_MUL_R2_PROJ \\\n+\t\t\t\t     (0x00b | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_R2_IN \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_PRJECTV)\n+#define OP_ALG_PKMODE_ECC_F2M_MUL_R2_PROJ_TEQ \\\n+\t\t\t\t     (0x00b | OP_ALG_PKMODE_MOD_F2M \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_MOD_R2_IN \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_PRJECTV \\\n+\t\t\t\t\t    | OP_ALG_PKMODE_TIME_EQ)\n+\n+/* PKHA mode copy-memory functions */\n+#define OP_ALG_PKMODE_SRC_REG_SHIFT  17\n+#define OP_ALG_PKMODE_SRC_REG_MASK   (7 << OP_ALG_PKMODE_SRC_REG_SHIFT)\n+#define OP_ALG_PKMODE_DST_REG_SHIFT  10\n+#define OP_ALG_PKMODE_DST_REG_MASK   (7 << OP_ALG_PKMODE_DST_REG_SHIFT)\n+#define OP_ALG_PKMODE_SRC_SEG_SHIFT  8\n+#define OP_ALG_PKMODE_SRC_SEG_MASK   (3 << OP_ALG_PKMODE_SRC_SEG_SHIFT)\n+#define OP_ALG_PKMODE_DST_SEG_SHIFT  6\n+#define OP_ALG_PKMODE_DST_SEG_MASK   (3 << OP_ALG_PKMODE_DST_SEG_SHIFT)\n+\n+#define OP_ALG_PKMODE_SRC_REG_A\t     (0 << OP_ALG_PKMODE_SRC_REG_SHIFT)\n+#define OP_ALG_PKMODE_SRC_REG_B\t     (1 << OP_ALG_PKMODE_SRC_REG_SHIFT)\n+#define OP_ALG_PKMODE_SRC_REG_N\t     (3 << OP_ALG_PKMODE_SRC_REG_SHIFT)\n+#define OP_ALG_PKMODE_DST_REG_A\t     (0 << OP_ALG_PKMODE_DST_REG_SHIFT)\n+#define OP_ALG_PKMODE_DST_REG_B\t     (1 << OP_ALG_PKMODE_DST_REG_SHIFT)\n+#define OP_ALG_PKMODE_DST_REG_E\t     (2 << OP_ALG_PKMODE_DST_REG_SHIFT)\n+#define OP_ALG_PKMODE_DST_REG_N\t     (3 << OP_ALG_PKMODE_DST_REG_SHIFT)\n+#define OP_ALG_PKMODE_SRC_SEG_0\t     (0 << OP_ALG_PKMODE_SRC_SEG_SHIFT)\n+#define OP_ALG_PKMODE_SRC_SEG_1\t     (1 << OP_ALG_PKMODE_SRC_SEG_SHIFT)\n+#define OP_ALG_PKMODE_SRC_SEG_2\t     (2 << OP_ALG_PKMODE_SRC_SEG_SHIFT)\n+#define OP_ALG_PKMODE_SRC_SEG_3\t     (3 << OP_ALG_PKMODE_SRC_SEG_SHIFT)\n+#define OP_ALG_PKMODE_DST_SEG_0\t     (0 << OP_ALG_PKMODE_DST_SEG_SHIFT)\n+#define OP_ALG_PKMODE_DST_SEG_1\t     (1 << OP_ALG_PKMODE_DST_SEG_SHIFT)\n+#define OP_ALG_PKMODE_DST_SEG_2\t     (2 << OP_ALG_PKMODE_DST_SEG_SHIFT)\n+#define OP_ALG_PKMODE_DST_SEG_3\t     (3 << OP_ALG_PKMODE_DST_SEG_SHIFT)\n+\n+/* PKHA mode copy-memory functions - amount based on N SIZE */\n+#define OP_ALG_PKMODE_COPY_NSZ\t\t0x10\n+#define OP_ALG_PKMODE_COPY_NSZ_A0_B0\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_NSZ_A0_B1\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_NSZ_A0_B2\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_NSZ_A0_B3\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_NSZ_A1_B0\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_NSZ_A1_B1\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_NSZ_A1_B2\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_NSZ_A1_B3\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_NSZ_A2_B0\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_NSZ_A2_B1\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_NSZ_A2_B2\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_NSZ_A2_B3\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_NSZ_A3_B0\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_NSZ_A3_B1\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_NSZ_A3_B2\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_NSZ_A3_B3\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_NSZ_B0_A0\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_NSZ_B0_A1\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_NSZ_B0_A2\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_NSZ_B0_A3\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_NSZ_B1_A0\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_NSZ_B1_A1\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_NSZ_B1_A2\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_NSZ_B1_A3\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_NSZ_B2_A0\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_NSZ_B2_A1\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_NSZ_B2_A2\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_NSZ_B2_A3\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_NSZ_B3_A0\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_NSZ_B3_A1\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_NSZ_B3_A2\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_NSZ_B3_A3\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_NSZ_A_B\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_NSZ_A_E\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_E)\n+#define OP_ALG_PKMODE_COPY_NSZ_A_N\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_N)\n+#define OP_ALG_PKMODE_COPY_NSZ_B_A\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_NSZ_B_E\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_E)\n+#define OP_ALG_PKMODE_COPY_NSZ_B_N\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_N)\n+#define OP_ALG_PKMODE_COPY_NSZ_N_A\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_N | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_NSZ_N_B\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_N | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_NSZ_N_E\t(OP_ALG_PKMODE_COPY_NSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_N | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_E)\n+\n+/* PKHA mode copy-memory functions - amount based on SRC SIZE */\n+#define OP_ALG_PKMODE_COPY_SSZ\t\t0x11\n+#define OP_ALG_PKMODE_COPY_SSZ_A0_B0\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_SSZ_A0_B1\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_SSZ_A0_B2\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_SSZ_A0_B3\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_SSZ_A1_B0\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_SSZ_A1_B1\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_SSZ_A1_B2\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_SSZ_A1_B3\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_SSZ_A2_B0\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_SSZ_A2_B1\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_SSZ_A2_B2\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_SSZ_A2_B3\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_SSZ_A3_B0\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_SSZ_A3_B1\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_SSZ_A3_B2\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_SSZ_A3_B3\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_SSZ_B0_A0\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_SSZ_B0_A1\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_SSZ_B0_A2\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_SSZ_B0_A3\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_SSZ_B1_A0\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_SSZ_B1_A1\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_SSZ_B1_A2\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_SSZ_B1_A3\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_1 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_SSZ_B2_A0\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_SSZ_B2_A1\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_SSZ_B2_A2\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_SSZ_B2_A3\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_2 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_SSZ_B3_A0\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_SSZ_B3_A1\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_1)\n+#define OP_ALG_PKMODE_COPY_SSZ_B3_A2\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_2)\n+#define OP_ALG_PKMODE_COPY_SSZ_B3_A3\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_SEG_3 | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_SEG_3)\n+\n+#define OP_ALG_PKMODE_COPY_SSZ_A_B\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_SSZ_A_E\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_E)\n+#define OP_ALG_PKMODE_COPY_SSZ_A_N\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_A | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_N)\n+#define OP_ALG_PKMODE_COPY_SSZ_B_A\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_SSZ_B_E\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_E)\n+#define OP_ALG_PKMODE_COPY_SSZ_B_N\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_B | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_N)\n+#define OP_ALG_PKMODE_COPY_SSZ_N_A\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_N | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_A)\n+#define OP_ALG_PKMODE_COPY_SSZ_N_B\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_N | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_B)\n+#define OP_ALG_PKMODE_COPY_SSZ_N_E\t(OP_ALG_PKMODE_COPY_SSZ | \\\n+\t\t\t\t\t OP_ALG_PKMODE_SRC_REG_N | \\\n+\t\t\t\t\t OP_ALG_PKMODE_DST_REG_E)\n+\n+/*\n+ * SEQ_IN_PTR Command Constructs\n+ */\n+\n+/* Release Buffers */\n+#define SQIN_RBS\tBIT(26)\n+\n+/* Sequence pointer is really a descriptor */\n+#define SQIN_INL\tBIT(25)\n+\n+/* Sequence pointer is a scatter-gather table */\n+#define SQIN_SGF\tBIT(24)\n+\n+/* Appends to a previous pointer */\n+#define SQIN_PRE\tBIT(23)\n+\n+/* Use extended length following pointer */\n+#define SQIN_EXT\tBIT(22)\n+\n+/* Restore sequence with pointer/length */\n+#define SQIN_RTO\tBIT(21)\n+\n+/* Replace job descriptor */\n+#define SQIN_RJD\tBIT(20)\n+\n+/* Sequence Out Pointer - start a new input sequence using output sequence */\n+#define SQIN_SOP\tBIT(19)\n+\n+#define SQIN_LEN_SHIFT\t0\n+#define SQIN_LEN_MASK\t(0xffff << SQIN_LEN_SHIFT)\n+\n+/*\n+ * SEQ_OUT_PTR Command Constructs\n+ */\n+\n+/* Sequence pointer is a scatter-gather table */\n+#define SQOUT_SGF\tBIT(24)\n+\n+/* Appends to a previous pointer */\n+#define SQOUT_PRE\tBIT(23)\n+\n+/* Restore sequence with pointer/length */\n+#define SQOUT_RTO\tBIT(21)\n+\n+/*\n+ * Ignore length field, add current output frame length back to SOL register.\n+ * Reset tracking length of bytes written to output frame.\n+ * Must be used together with SQOUT_RTO.\n+ */\n+#define SQOUT_RST\tBIT(20)\n+\n+/* Allow \"write safe\" transactions for this Output Sequence */\n+#define SQOUT_EWS\tBIT(19)\n+\n+/* Use extended length following pointer */\n+#define SQOUT_EXT\tBIT(22)\n+\n+#define SQOUT_LEN_SHIFT\t0\n+#define SQOUT_LEN_MASK\t(0xffff << SQOUT_LEN_SHIFT)\n+\n+\n+/*\n+ * SIGNATURE Command Constructs\n+ */\n+\n+/* TYPE field is all that's relevant */\n+#define SIGN_TYPE_SHIFT\t\t16\n+#define SIGN_TYPE_MASK\t\t(0x0f << SIGN_TYPE_SHIFT)\n+\n+#define SIGN_TYPE_FINAL\t\t(0x00 << SIGN_TYPE_SHIFT)\n+#define SIGN_TYPE_FINAL_RESTORE (0x01 << SIGN_TYPE_SHIFT)\n+#define SIGN_TYPE_FINAL_NONZERO (0x02 << SIGN_TYPE_SHIFT)\n+#define SIGN_TYPE_IMM_2\t\t(0x0a << SIGN_TYPE_SHIFT)\n+#define SIGN_TYPE_IMM_3\t\t(0x0b << SIGN_TYPE_SHIFT)\n+#define SIGN_TYPE_IMM_4\t\t(0x0c << SIGN_TYPE_SHIFT)\n+\n+/*\n+ * MOVE Command Constructs\n+ */\n+\n+#define MOVE_AUX_SHIFT\t\t25\n+#define MOVE_AUX_MASK\t\t(3 << MOVE_AUX_SHIFT)\n+#define MOVE_AUX_MS\t\t(2 << MOVE_AUX_SHIFT)\n+#define MOVE_AUX_LS\t\t(1 << MOVE_AUX_SHIFT)\n+\n+#define MOVE_WAITCOMP_SHIFT\t24\n+#define MOVE_WAITCOMP_MASK\t(1 << MOVE_WAITCOMP_SHIFT)\n+#define MOVE_WAITCOMP\t\tBIT(24)\n+\n+#define MOVE_SRC_SHIFT\t\t20\n+#define MOVE_SRC_MASK\t\t(0x0f << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_CLASS1CTX\t(0x00 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_CLASS2CTX\t(0x01 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_OUTFIFO\t(0x02 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_DESCBUF\t(0x03 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_MATH0\t\t(0x04 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_MATH1\t\t(0x05 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_MATH2\t\t(0x06 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_MATH3\t\t(0x07 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_INFIFO\t\t(0x08 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_INFIFO_CL\t(0x09 << MOVE_SRC_SHIFT)\n+#define MOVE_SRC_INFIFO_NO_NFIFO (0x0a << MOVE_SRC_SHIFT)\n+\n+#define MOVE_DEST_SHIFT\t\t16\n+#define MOVE_DEST_MASK\t\t(0x0f << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_CLASS1CTX\t(0x00 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_CLASS2CTX\t(0x01 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_OUTFIFO\t(0x02 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_DESCBUF\t(0x03 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_MATH0\t\t(0x04 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_MATH1\t\t(0x05 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_MATH2\t\t(0x06 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_MATH3\t\t(0x07 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_CLASS1INFIFO\t(0x08 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_CLASS2INFIFO\t(0x09 << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_INFIFO\t(0x0a << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_PK_A\t\t(0x0c << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_CLASS1KEY\t(0x0d << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_CLASS2KEY\t(0x0e << MOVE_DEST_SHIFT)\n+#define MOVE_DEST_ALTSOURCE\t(0x0f << MOVE_DEST_SHIFT)\n+\n+#define MOVE_OFFSET_SHIFT\t8\n+#define MOVE_OFFSET_MASK\t(0xff << MOVE_OFFSET_SHIFT)\n+\n+#define MOVE_LEN_SHIFT\t\t0\n+#define MOVE_LEN_MASK\t\t(0xff << MOVE_LEN_SHIFT)\n+\n+#define MOVELEN_MRSEL_SHIFT\t0\n+#define MOVELEN_MRSEL_MASK\t(0x3 << MOVE_LEN_SHIFT)\n+#define MOVELEN_MRSEL_MATH0\t(0 << MOVELEN_MRSEL_SHIFT)\n+#define MOVELEN_MRSEL_MATH1\t(1 << MOVELEN_MRSEL_SHIFT)\n+#define MOVELEN_MRSEL_MATH2\t(2 << MOVELEN_MRSEL_SHIFT)\n+#define MOVELEN_MRSEL_MATH3\t(3 << MOVELEN_MRSEL_SHIFT)\n+\n+#define MOVELEN_SIZE_SHIFT\t6\n+#define MOVELEN_SIZE_MASK\t(0x3 << MOVELEN_SIZE_SHIFT)\n+#define MOVELEN_SIZE_WORD\t(0x01 << MOVELEN_SIZE_SHIFT)\n+#define MOVELEN_SIZE_BYTE\t(0x02 << MOVELEN_SIZE_SHIFT)\n+#define MOVELEN_SIZE_DWORD\t(0x03 << MOVELEN_SIZE_SHIFT)\n+\n+/*\n+ * MATH Command Constructs\n+ */\n+\n+#define MATH_IFB_SHIFT\t\t26\n+#define MATH_IFB_MASK\t\t(1 << MATH_IFB_SHIFT)\n+#define MATH_IFB\t\tBIT(26)\n+\n+#define MATH_NFU_SHIFT\t\t25\n+#define MATH_NFU_MASK\t\t(1 << MATH_NFU_SHIFT)\n+#define MATH_NFU\t\tBIT(25)\n+\n+/* STL for MATH, SSEL for MATHI */\n+#define MATH_STL_SHIFT\t\t24\n+#define MATH_STL_MASK\t\t(1 << MATH_STL_SHIFT)\n+#define MATH_STL\t\tBIT(24)\n+\n+#define MATH_SSEL_SHIFT\t\t24\n+#define MATH_SSEL_MASK\t\t(1 << MATH_SSEL_SHIFT)\n+#define MATH_SSEL\t\tBIT(24)\n+\n+#define MATH_SWP_SHIFT\t\t0\n+#define MATH_SWP_MASK\t\t(1 << MATH_SWP_SHIFT)\n+#define MATH_SWP\t\tBIT(0)\n+\n+/* Function selectors */\n+#define MATH_FUN_SHIFT\t\t20\n+#define MATH_FUN_MASK\t\t(0x0f << MATH_FUN_SHIFT)\n+#define MATH_FUN_ADD\t\t(0x00 << MATH_FUN_SHIFT)\n+#define MATH_FUN_ADDC\t\t(0x01 << MATH_FUN_SHIFT)\n+#define MATH_FUN_SUB\t\t(0x02 << MATH_FUN_SHIFT)\n+#define MATH_FUN_SUBB\t\t(0x03 << MATH_FUN_SHIFT)\n+#define MATH_FUN_OR\t\t(0x04 << MATH_FUN_SHIFT)\n+#define MATH_FUN_AND\t\t(0x05 << MATH_FUN_SHIFT)\n+#define MATH_FUN_XOR\t\t(0x06 << MATH_FUN_SHIFT)\n+#define MATH_FUN_LSHIFT\t\t(0x07 << MATH_FUN_SHIFT)\n+#define MATH_FUN_RSHIFT\t\t(0x08 << MATH_FUN_SHIFT)\n+#define MATH_FUN_SHLD\t\t(0x09 << MATH_FUN_SHIFT)\n+#define MATH_FUN_ZBYT\t\t(0x0a << MATH_FUN_SHIFT) /* ZBYT is for MATH */\n+#define MATH_FUN_FBYT\t\t(0x0a << MATH_FUN_SHIFT) /* FBYT is for MATHI */\n+#define MATH_FUN_BSWAP\t\t(0x0b << MATH_FUN_SHIFT)\n+\n+/* Source 0 selectors */\n+#define MATH_SRC0_SHIFT\t\t16\n+#define MATH_SRC0_MASK\t\t(0x0f << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_REG0\t\t(0x00 << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_REG1\t\t(0x01 << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_REG2\t\t(0x02 << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_REG3\t\t(0x03 << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_IMM\t\t(0x04 << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_DPOVRD\t(0x07 << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_SEQINLEN\t(0x08 << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_SEQOUTLEN\t(0x09 << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_VARSEQINLEN\t(0x0a << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_VARSEQOUTLEN\t(0x0b << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_ZERO\t\t(0x0c << MATH_SRC0_SHIFT)\n+#define MATH_SRC0_ONE\t\t(0x0f << MATH_SRC0_SHIFT)\n+\n+/* Source 1 selectors */\n+#define MATH_SRC1_SHIFT\t\t12\n+#define MATHI_SRC1_SHIFT\t16\n+#define MATH_SRC1_MASK\t\t(0x0f << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_REG0\t\t(0x00 << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_REG1\t\t(0x01 << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_REG2\t\t(0x02 << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_REG3\t\t(0x03 << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_IMM\t\t(0x04 << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_DPOVRD\t(0x07 << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_VARSEQINLEN\t(0x08 << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_VARSEQOUTLEN\t(0x09 << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_INFIFO\t(0x0a << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_OUTFIFO\t(0x0b << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_ONE\t\t(0x0c << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_JOBSOURCE\t(0x0d << MATH_SRC1_SHIFT)\n+#define MATH_SRC1_ZERO\t\t(0x0f << MATH_SRC1_SHIFT)\n+\n+/* Destination selectors */\n+#define MATH_DEST_SHIFT\t\t8\n+#define MATHI_DEST_SHIFT\t12\n+#define MATH_DEST_MASK\t\t(0x0f << MATH_DEST_SHIFT)\n+#define MATH_DEST_REG0\t\t(0x00 << MATH_DEST_SHIFT)\n+#define MATH_DEST_REG1\t\t(0x01 << MATH_DEST_SHIFT)\n+#define MATH_DEST_REG2\t\t(0x02 << MATH_DEST_SHIFT)\n+#define MATH_DEST_REG3\t\t(0x03 << MATH_DEST_SHIFT)\n+#define MATH_DEST_DPOVRD\t(0x07 << MATH_DEST_SHIFT)\n+#define MATH_DEST_SEQINLEN\t(0x08 << MATH_DEST_SHIFT)\n+#define MATH_DEST_SEQOUTLEN\t(0x09 << MATH_DEST_SHIFT)\n+#define MATH_DEST_VARSEQINLEN\t(0x0a << MATH_DEST_SHIFT)\n+#define MATH_DEST_VARSEQOUTLEN\t(0x0b << MATH_DEST_SHIFT)\n+#define MATH_DEST_NONE\t\t(0x0f << MATH_DEST_SHIFT)\n+\n+/* MATHI Immediate value */\n+#define MATHI_IMM_SHIFT\t\t4\n+#define MATHI_IMM_MASK\t\t(0xff << MATHI_IMM_SHIFT)\n+\n+/* Length selectors */\n+#define MATH_LEN_SHIFT\t\t0\n+#define MATH_LEN_MASK\t\t(0x0f << MATH_LEN_SHIFT)\n+#define MATH_LEN_1BYTE\t\t0x01\n+#define MATH_LEN_2BYTE\t\t0x02\n+#define MATH_LEN_4BYTE\t\t0x04\n+#define MATH_LEN_8BYTE\t\t0x08\n+\n+/*\n+ * JUMP Command Constructs\n+ */\n+\n+#define JUMP_CLASS_SHIFT\t25\n+#define JUMP_CLASS_MASK\t\t(3 << JUMP_CLASS_SHIFT)\n+#define JUMP_CLASS_NONE\t\t0\n+#define JUMP_CLASS_CLASS1\t(1 << JUMP_CLASS_SHIFT)\n+#define JUMP_CLASS_CLASS2\t(2 << JUMP_CLASS_SHIFT)\n+#define JUMP_CLASS_BOTH\t\t(3 << JUMP_CLASS_SHIFT)\n+\n+#define JUMP_JSL_SHIFT\t\t24\n+#define JUMP_JSL_MASK\t\t(1 << JUMP_JSL_SHIFT)\n+#define JUMP_JSL\t\tBIT(24)\n+\n+#define JUMP_TYPE_SHIFT\t\t20\n+#define JUMP_TYPE_MASK\t\t(0x0f << JUMP_TYPE_SHIFT)\n+#define JUMP_TYPE_LOCAL\t\t(0x00 << JUMP_TYPE_SHIFT)\n+#define JUMP_TYPE_LOCAL_INC\t(0x01 << JUMP_TYPE_SHIFT)\n+#define JUMP_TYPE_GOSUB\t\t(0x02 << JUMP_TYPE_SHIFT)\n+#define JUMP_TYPE_LOCAL_DEC\t(0x03 << JUMP_TYPE_SHIFT)\n+#define JUMP_TYPE_NONLOCAL\t(0x04 << JUMP_TYPE_SHIFT)\n+#define JUMP_TYPE_RETURN\t(0x06 << JUMP_TYPE_SHIFT)\n+#define JUMP_TYPE_HALT\t\t(0x08 << JUMP_TYPE_SHIFT)\n+#define JUMP_TYPE_HALT_USER\t(0x0c << JUMP_TYPE_SHIFT)\n+\n+#define JUMP_TEST_SHIFT\t\t16\n+#define JUMP_TEST_MASK\t\t(0x03 << JUMP_TEST_SHIFT)\n+#define JUMP_TEST_ALL\t\t(0x00 << JUMP_TEST_SHIFT)\n+#define JUMP_TEST_INVALL\t(0x01 << JUMP_TEST_SHIFT)\n+#define JUMP_TEST_ANY\t\t(0x02 << JUMP_TEST_SHIFT)\n+#define JUMP_TEST_INVANY\t(0x03 << JUMP_TEST_SHIFT)\n+\n+/* Condition codes. JSL bit is factored in */\n+#define JUMP_COND_SHIFT\t\t8\n+#define JUMP_COND_MASK\t\t((0xff << JUMP_COND_SHIFT) | JUMP_JSL)\n+#define JUMP_COND_PK_0\t\tBIT(15)\n+#define JUMP_COND_PK_GCD_1\tBIT(14)\n+#define JUMP_COND_PK_PRIME\tBIT(13)\n+#define JUMP_COND_MATH_N\tBIT(11)\n+#define JUMP_COND_MATH_Z\tBIT(10)\n+#define JUMP_COND_MATH_C\tBIT(9)\n+#define JUMP_COND_MATH_NV\tBIT(8)\n+\n+#define JUMP_COND_JQP\t\t(BIT(15) | JUMP_JSL)\n+#define JUMP_COND_SHRD\t\t(BIT(14) | JUMP_JSL)\n+#define JUMP_COND_SELF\t\t(BIT(13) | JUMP_JSL)\n+#define JUMP_COND_CALM\t\t(BIT(12) | JUMP_JSL)\n+#define JUMP_COND_NIP\t\t(BIT(11) | JUMP_JSL)\n+#define JUMP_COND_NIFP\t\t(BIT(10) | JUMP_JSL)\n+#define JUMP_COND_NOP\t\t(BIT(9) | JUMP_JSL)\n+#define JUMP_COND_NCP\t\t(BIT(8) | JUMP_JSL)\n+\n+/* Source / destination selectors */\n+#define JUMP_SRC_DST_SHIFT\t\t12\n+#define JUMP_SRC_DST_MASK\t\t(0x0f << JUMP_SRC_DST_SHIFT)\n+#define JUMP_SRC_DST_MATH0\t\t(0x00 << JUMP_SRC_DST_SHIFT)\n+#define JUMP_SRC_DST_MATH1\t\t(0x01 << JUMP_SRC_DST_SHIFT)\n+#define JUMP_SRC_DST_MATH2\t\t(0x02 << JUMP_SRC_DST_SHIFT)\n+#define JUMP_SRC_DST_MATH3\t\t(0x03 << JUMP_SRC_DST_SHIFT)\n+#define JUMP_SRC_DST_DPOVRD\t\t(0x07 << JUMP_SRC_DST_SHIFT)\n+#define JUMP_SRC_DST_SEQINLEN\t\t(0x08 << JUMP_SRC_DST_SHIFT)\n+#define JUMP_SRC_DST_SEQOUTLEN\t\t(0x09 << JUMP_SRC_DST_SHIFT)\n+#define JUMP_SRC_DST_VARSEQINLEN\t(0x0a << JUMP_SRC_DST_SHIFT)\n+#define JUMP_SRC_DST_VARSEQOUTLEN\t(0x0b << JUMP_SRC_DST_SHIFT)\n+\n+#define JUMP_OFFSET_SHIFT\t0\n+#define JUMP_OFFSET_MASK\t(0xff << JUMP_OFFSET_SHIFT)\n+\n+/*\n+ * NFIFO ENTRY\n+ * Data Constructs\n+ *\n+ */\n+#define NFIFOENTRY_DEST_SHIFT\t30\n+#define NFIFOENTRY_DEST_MASK\t((uint32_t)(3 << NFIFOENTRY_DEST_SHIFT))\n+#define NFIFOENTRY_DEST_DECO\t(0 << NFIFOENTRY_DEST_SHIFT)\n+#define NFIFOENTRY_DEST_CLASS1\t(1 << NFIFOENTRY_DEST_SHIFT)\n+#define NFIFOENTRY_DEST_CLASS2\t((uint32_t)(2 << NFIFOENTRY_DEST_SHIFT))\n+#define NFIFOENTRY_DEST_BOTH\t((uint32_t)(3 << NFIFOENTRY_DEST_SHIFT))\n+\n+#define NFIFOENTRY_LC2_SHIFT\t29\n+#define NFIFOENTRY_LC2_MASK\t(1 << NFIFOENTRY_LC2_SHIFT)\n+#define NFIFOENTRY_LC2\t\tBIT(29)\n+\n+#define NFIFOENTRY_LC1_SHIFT\t28\n+#define NFIFOENTRY_LC1_MASK\t(1 << NFIFOENTRY_LC1_SHIFT)\n+#define NFIFOENTRY_LC1\t\tBIT(28)\n+\n+#define NFIFOENTRY_FC2_SHIFT\t27\n+#define NFIFOENTRY_FC2_MASK\t(1 << NFIFOENTRY_FC2_SHIFT)\n+#define NFIFOENTRY_FC2\t\tBIT(27)\n+\n+#define NFIFOENTRY_FC1_SHIFT\t26\n+#define NFIFOENTRY_FC1_MASK\t(1 << NFIFOENTRY_FC1_SHIFT)\n+#define NFIFOENTRY_FC1\t\tBIT(26)\n+\n+#define NFIFOENTRY_STYPE_SHIFT\t24\n+#define NFIFOENTRY_STYPE_MASK\t(3 << NFIFOENTRY_STYPE_SHIFT)\n+#define NFIFOENTRY_STYPE_DFIFO\t(0 << NFIFOENTRY_STYPE_SHIFT)\n+#define NFIFOENTRY_STYPE_OFIFO\t(1 << NFIFOENTRY_STYPE_SHIFT)\n+#define NFIFOENTRY_STYPE_PAD\t(2 << NFIFOENTRY_STYPE_SHIFT)\n+#define NFIFOENTRY_STYPE_SNOOP\t(3 << NFIFOENTRY_STYPE_SHIFT)\n+#define NFIFOENTRY_STYPE_ALTSOURCE ((0 << NFIFOENTRY_STYPE_SHIFT) \\\n+\t\t\t\t\t| NFIFOENTRY_AST)\n+#define NFIFOENTRY_STYPE_OFIFO_SYNC ((1 << NFIFOENTRY_STYPE_SHIFT) \\\n+\t\t\t\t\t| NFIFOENTRY_AST)\n+#define NFIFOENTRY_STYPE_SNOOP_ALT ((3 << NFIFOENTRY_STYPE_SHIFT) \\\n+\t\t\t\t\t| NFIFOENTRY_AST)\n+\n+#define NFIFOENTRY_DTYPE_SHIFT\t20\n+#define NFIFOENTRY_DTYPE_MASK\t(0xF << NFIFOENTRY_DTYPE_SHIFT)\n+\n+#define NFIFOENTRY_DTYPE_SBOX\t(0x0 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_AAD\t(0x1 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_IV\t(0x2 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_SAD\t(0x3 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_ICV\t(0xA << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_SKIP\t(0xE << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_MSG\t(0xF << NFIFOENTRY_DTYPE_SHIFT)\n+\n+#define NFIFOENTRY_DTYPE_PK_A0\t(0x0 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_A1\t(0x1 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_A2\t(0x2 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_A3\t(0x3 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_B0\t(0x4 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_B1\t(0x5 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_B2\t(0x6 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_B3\t(0x7 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_N\t(0x8 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_E\t(0x9 << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_A\t(0xC << NFIFOENTRY_DTYPE_SHIFT)\n+#define NFIFOENTRY_DTYPE_PK_B\t(0xD << NFIFOENTRY_DTYPE_SHIFT)\n+\n+#define NFIFOENTRY_BND_SHIFT\t19\n+#define NFIFOENTRY_BND_MASK\t(1 << NFIFOENTRY_BND_SHIFT)\n+#define NFIFOENTRY_BND\t\tBIT(19)\n+\n+#define NFIFOENTRY_PTYPE_SHIFT\t16\n+#define NFIFOENTRY_PTYPE_MASK\t(0x7 << NFIFOENTRY_PTYPE_SHIFT)\n+\n+#define NFIFOENTRY_PTYPE_ZEROS\t\t(0x0 << NFIFOENTRY_PTYPE_SHIFT)\n+#define NFIFOENTRY_PTYPE_RND_NOZEROS\t(0x1 << NFIFOENTRY_PTYPE_SHIFT)\n+#define NFIFOENTRY_PTYPE_INCREMENT\t(0x2 << NFIFOENTRY_PTYPE_SHIFT)\n+#define NFIFOENTRY_PTYPE_RND\t\t(0x3 << NFIFOENTRY_PTYPE_SHIFT)\n+#define NFIFOENTRY_PTYPE_ZEROS_NZ\t(0x4 << NFIFOENTRY_PTYPE_SHIFT)\n+#define NFIFOENTRY_PTYPE_RND_NZ_LZ\t(0x5 << NFIFOENTRY_PTYPE_SHIFT)\n+#define NFIFOENTRY_PTYPE_N\t\t(0x6 << NFIFOENTRY_PTYPE_SHIFT)\n+#define NFIFOENTRY_PTYPE_RND_NZ_N\t(0x7 << NFIFOENTRY_PTYPE_SHIFT)\n+\n+#define NFIFOENTRY_OC_SHIFT\t15\n+#define NFIFOENTRY_OC_MASK\t(1 << NFIFOENTRY_OC_SHIFT)\n+#define NFIFOENTRY_OC\t\tBIT(15)\n+\n+#define NFIFOENTRY_PR_SHIFT\t15\n+#define NFIFOENTRY_PR_MASK\t(1 << NFIFOENTRY_PR_SHIFT)\n+#define NFIFOENTRY_PR\t\tBIT(15)\n+\n+#define NFIFOENTRY_AST_SHIFT\t14\n+#define NFIFOENTRY_AST_MASK\t(1 << NFIFOENTRY_AST_SHIFT)\n+#define NFIFOENTRY_AST\t\tBIT(14)\n+\n+#define NFIFOENTRY_BM_SHIFT\t11\n+#define NFIFOENTRY_BM_MASK\t(1 << NFIFOENTRY_BM_SHIFT)\n+#define NFIFOENTRY_BM\t\tBIT(11)\n+\n+#define NFIFOENTRY_PS_SHIFT\t10\n+#define NFIFOENTRY_PS_MASK\t(1 << NFIFOENTRY_PS_SHIFT)\n+#define NFIFOENTRY_PS\t\tBIT(10)\n+\n+#define NFIFOENTRY_DLEN_SHIFT\t0\n+#define NFIFOENTRY_DLEN_MASK\t(0xFFF << NFIFOENTRY_DLEN_SHIFT)\n+\n+#define NFIFOENTRY_PLEN_SHIFT\t0\n+#define NFIFOENTRY_PLEN_MASK\t(0xFF << NFIFOENTRY_PLEN_SHIFT)\n+\n+/* Append Load Immediate Command */\n+#define FD_CMD_APPEND_LOAD_IMMEDIATE\t\t\tBIT(31)\n+\n+/* Set SEQ LIODN equal to the Non-SEQ LIODN for the job */\n+#define FD_CMD_SET_SEQ_LIODN_EQUAL_NONSEQ_LIODN\t\tBIT(30)\n+\n+/* Frame Descriptor Command for Replacement Job Descriptor */\n+#define FD_CMD_REPLACE_JOB_DESC\t\t\t\tBIT(29)\n+\n+#endif /* __RTA_DESC_H__ */\ndiff --git a/drivers/crypto/dpaa2_sec/hw/desc/algo.h b/drivers/crypto/dpaa2_sec/hw/desc/algo.h\nnew file mode 100644\nindex 0000000..a1f1907\n--- /dev/null\n+++ b/drivers/crypto/dpaa2_sec/hw/desc/algo.h\n@@ -0,0 +1,424 @@\n+/*\n+ * Copyright 2008-2016 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier: BSD-3-Clause or GPL-2.0+\n+ */\n+\n+#ifndef __DESC_ALGO_H__\n+#define __DESC_ALGO_H__\n+\n+#include \"hw/rta.h\"\n+#include \"common.h\"\n+\n+/**\n+ * DOC: Algorithms - Shared Descriptor Constructors\n+ *\n+ * Shared descriptors for algorithms (i.e. not for protocols).\n+ */\n+\n+/**\n+ * cnstr_shdsc_snow_f8 - SNOW/f8 (UEA2) as a shared descriptor\n+ * @descbuf: pointer to descriptor-under-construction buffer\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: must be true when core endianness doesn't match SEC endianness\n+ * @cipherdata: pointer to block cipher transform definitions\n+ * @dir: Cipher direction (DIR_ENC/DIR_DEC)\n+ * @count: UEA2 count value (32 bits)\n+ * @bearer: UEA2 bearer ID (5 bits)\n+ * @direction: UEA2 direction (1 bit)\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_snow_f8(uint32_t *descbuf, bool ps, bool swap,\n+\t\t\t struct alginfo *cipherdata, uint8_t dir,\n+\t\t\t uint32_t count, uint8_t bearer, uint8_t direction)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\tuint32_t ct = count;\n+\tuint8_t br = bearer;\n+\tuint8_t dr = direction;\n+\tuint32_t context[2] = {ct, (br << 27) | (dr << 26)};\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap) {\n+\t\tPROGRAM_SET_BSWAP(p);\n+\n+\t\tcontext[0] = swab32(context[0]);\n+\t\tcontext[1] = swab32(context[1]);\n+\t}\n+\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tSHR_HDR(p, SHR_ALWAYS, 1, 0);\n+\n+\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQINSZ, 4, 0);\n+\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQOUTSZ, 4, 0);\n+\tALG_OPERATION(p, OP_ALG_ALGSEL_SNOW_F8, OP_ALG_AAI_F8,\n+\t\t      OP_ALG_AS_INITFINAL, 0, dir);\n+\tLOAD(p, (uintptr_t)context, CONTEXT1, 0, 8, IMMED | COPY);\n+\tSEQFIFOLOAD(p, MSG1, 0, VLF | LAST1);\n+\tSEQFIFOSTORE(p, MSG, 0, 0, VLF);\n+\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * cnstr_shdsc_snow_f9 - SNOW/f9 (UIA2) as a shared descriptor\n+ * @descbuf: pointer to descriptor-under-construction buffer\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: must be true when core endianness doesn't match SEC endianness\n+ * @authdata: pointer to authentication transform definitions\n+ * @dir: cipher direction (DIR_ENC/DIR_DEC)\n+ * @count: UEA2 count value (32 bits)\n+ * @fresh: UEA2 fresh value ID (32 bits)\n+ * @direction: UEA2 direction (1 bit)\n+ * @datalen: size of data\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_snow_f9(uint32_t *descbuf, bool ps, bool swap,\n+\t\t\t struct alginfo *authdata, uint8_t dir, uint32_t count,\n+\t\t\t uint32_t fresh, uint8_t direction, uint32_t datalen)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\tuint64_t ct = count;\n+\tuint64_t fr = fresh;\n+\tuint64_t dr = direction;\n+\tuint64_t context[2];\n+\n+\tcontext[0] = (ct << 32) | (dr << 26);\n+\tcontext[1] = fr << 32;\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap) {\n+\t\tPROGRAM_SET_BSWAP(p);\n+\n+\t\tcontext[0] = swab64(context[0]);\n+\t\tcontext[1] = swab64(context[1]);\n+\t}\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tSHR_HDR(p, SHR_ALWAYS, 1, 0);\n+\n+\tKEY(p, KEY2, authdata->key_enc_flags, authdata->key, authdata->keylen,\n+\t    INLINE_KEY(authdata));\n+\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQINSZ, 4, 0);\n+\tALG_OPERATION(p, OP_ALG_ALGSEL_SNOW_F9, OP_ALG_AAI_F9,\n+\t\t      OP_ALG_AS_INITFINAL, 0, dir);\n+\tLOAD(p, (uintptr_t)context, CONTEXT2, 0, 16, IMMED | COPY);\n+\tSEQFIFOLOAD(p, BIT_DATA, datalen, CLASS2 | LAST2);\n+\t/* Save lower half of MAC out into a 32-bit sequence */\n+\tSEQSTORE(p, CONTEXT2, 0, 4, 0);\n+\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * cnstr_shdsc_blkcipher - block cipher transformation\n+ * @descbuf: pointer to descriptor-under-construction buffer\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: must be true when core endianness doesn't match SEC endianness\n+ * @cipherdata: pointer to block cipher transform definitions\n+ * @iv: IV data; if NULL, \"ivlen\" bytes from the input frame will be read as IV\n+ * @ivlen: IV length\n+ * @dir: DIR_ENC/DIR_DEC\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_blkcipher(uint32_t *descbuf, bool ps, bool swap,\n+\t\t\t       struct alginfo *cipherdata, uint8_t *iv,\n+\t\t\t       uint32_t ivlen, uint8_t dir)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\tconst bool is_aes_dec = (dir == DIR_DEC) &&\n+\t\t\t\t(cipherdata->algtype == OP_ALG_ALGSEL_AES);\n+\tLABEL(keyjmp);\n+\tLABEL(skipdk);\n+\tREFERENCE(pkeyjmp);\n+\tREFERENCE(pskipdk);\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap)\n+\t\tPROGRAM_SET_BSWAP(p);\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tSHR_HDR(p, SHR_SERIAL, 1, SC);\n+\n+\tpkeyjmp = JUMP(p, keyjmp, LOCAL_JUMP, ALL_TRUE, SHRD);\n+\t/* Insert Key */\n+\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\n+\tif (is_aes_dec) {\n+\t\tALG_OPERATION(p, cipherdata->algtype, cipherdata->algmode,\n+\t\t\t      OP_ALG_AS_INITFINAL, ICV_CHECK_DISABLE, dir);\n+\n+\t\tpskipdk = JUMP(p, skipdk, LOCAL_JUMP, ALL_TRUE, 0);\n+\t}\n+\tSET_LABEL(p, keyjmp);\n+\n+\tif (is_aes_dec) {\n+\t\tALG_OPERATION(p, OP_ALG_ALGSEL_AES, cipherdata->algmode |\n+\t\t\t      OP_ALG_AAI_DK, OP_ALG_AS_INITFINAL,\n+\t\t\t      ICV_CHECK_DISABLE, dir);\n+\t\tSET_LABEL(p, skipdk);\n+\t} else {\n+\t\tALG_OPERATION(p, cipherdata->algtype, cipherdata->algmode,\n+\t\t\t      OP_ALG_AS_INITFINAL, ICV_CHECK_DISABLE, dir);\n+\t}\n+\n+\tif (iv)\n+\t\t/* IV load, convert size */\n+\t\tLOAD(p, (uintptr_t)iv, CONTEXT1, 0, ivlen, IMMED | COPY);\n+\telse\n+\t\t/* IV is present first before the actual message */\n+\t\tSEQLOAD(p, CONTEXT1, 0, ivlen, 0);\n+\n+\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQINSZ, 4, 0);\n+\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQOUTSZ, 4, 0);\n+\n+\t/* Insert sequence load/store with VLF */\n+\tSEQFIFOLOAD(p, MSG1, 0, VLF | LAST1);\n+\tSEQFIFOSTORE(p, MSG, 0, 0, VLF);\n+\n+\tPATCH_JUMP(p, pkeyjmp, keyjmp);\n+\tif (is_aes_dec)\n+\t\tPATCH_JUMP(p, pskipdk, skipdk);\n+\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * cnstr_shdsc_hmac - HMAC shared\n+ * @descbuf: pointer to descriptor-under-construction buffer\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: must be true when core endianness doesn't match SEC endianness\n+ * @authdata: pointer to authentication transform definitions;\n+ *            message digest algorithm: OP_ALG_ALGSEL_MD5/ SHA1-512.\n+ * @do_icv: 0 if ICV checking is not desired, any other value if ICV checking\n+ *          is needed for all the packets processed by this shared descriptor\n+ * @trunc_len: Length of the truncated ICV to be written in the output buffer, 0\n+ *             if no truncation is needed\n+ *\n+ * Note: There's no support for keys longer than the corresponding digest size,\n+ * according to the selected algorithm.\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_hmac(uint32_t *descbuf, bool ps, bool swap,\n+\t\t\t\t   struct alginfo *authdata, uint8_t do_icv,\n+\t\t\t\t   uint8_t trunc_len)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\tuint8_t storelen, opicv, dir;\n+\tLABEL(keyjmp);\n+\tLABEL(jmpprecomp);\n+\tREFERENCE(pkeyjmp);\n+\tREFERENCE(pjmpprecomp);\n+\n+\t/* Compute fixed-size store based on alg selection */\n+\tswitch (authdata->algtype) {\n+\tcase OP_ALG_ALGSEL_MD5:\n+\t\tstorelen = 16;\n+\t\tbreak;\n+\tcase OP_ALG_ALGSEL_SHA1:\n+\t\tstorelen = 20;\n+\t\tbreak;\n+\tcase OP_ALG_ALGSEL_SHA224:\n+\t\tstorelen = 28;\n+\t\tbreak;\n+\tcase OP_ALG_ALGSEL_SHA256:\n+\t\tstorelen = 32;\n+\t\tbreak;\n+\tcase OP_ALG_ALGSEL_SHA384:\n+\t\tstorelen = 48;\n+\t\tbreak;\n+\tcase OP_ALG_ALGSEL_SHA512:\n+\t\tstorelen = 64;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttrunc_len = trunc_len && (trunc_len < storelen) ? trunc_len : storelen;\n+\n+\topicv = do_icv ? ICV_CHECK_ENABLE : ICV_CHECK_DISABLE;\n+\tdir = do_icv ? DIR_DEC : DIR_ENC;\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap)\n+\t\tPROGRAM_SET_BSWAP(p);\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tSHR_HDR(p, SHR_SERIAL, 1, SC);\n+\n+\tpkeyjmp = JUMP(p, keyjmp, LOCAL_JUMP, ALL_TRUE, SHRD);\n+\tKEY(p, KEY2, authdata->key_enc_flags, authdata->key, storelen,\n+\t    INLINE_KEY(authdata));\n+\n+\t/* Do operation */\n+\tALG_OPERATION(p, authdata->algtype, OP_ALG_AAI_HMAC,\n+\t\t      OP_ALG_AS_INITFINAL, opicv, dir);\n+\n+\tpjmpprecomp = JUMP(p, jmpprecomp, LOCAL_JUMP, ALL_TRUE, 0);\n+\tSET_LABEL(p, keyjmp);\n+\n+\tALG_OPERATION(p, authdata->algtype, OP_ALG_AAI_HMAC_PRECOMP,\n+\t\t      OP_ALG_AS_INITFINAL, opicv, dir);\n+\n+\tSET_LABEL(p, jmpprecomp);\n+\n+\t/* compute sequences */\n+\tif (opicv == ICV_CHECK_ENABLE)\n+\t\tMATHB(p, SEQINSZ, SUB, trunc_len, VSEQINSZ, 4, IMMED2);\n+\telse\n+\t\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQINSZ, 4, 0);\n+\n+\t/* Do load (variable length) */\n+\tSEQFIFOLOAD(p, MSG2, 0, VLF | LAST2);\n+\n+\tif (opicv == ICV_CHECK_ENABLE)\n+\t\tSEQFIFOLOAD(p, ICV2, trunc_len, LAST2);\n+\telse\n+\t\tSEQSTORE(p, CONTEXT2, 0, trunc_len, 0);\n+\n+\tPATCH_JUMP(p, pkeyjmp, keyjmp);\n+\tPATCH_JUMP(p, pjmpprecomp, jmpprecomp);\n+\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * cnstr_shdsc_kasumi_f8 - KASUMI F8 (Confidentiality) as a shared descriptor\n+ *                         (ETSI \"Document 1: f8 and f9 specification\")\n+ * @descbuf: pointer to descriptor-under-construction buffer\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: must be true when core endianness doesn't match SEC endianness\n+ * @cipherdata: pointer to block cipher transform definitions\n+ * @dir: cipher direction (DIR_ENC/DIR_DEC)\n+ * @count: count value (32 bits)\n+ * @bearer: bearer ID (5 bits)\n+ * @direction: direction (1 bit)\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_kasumi_f8(uint32_t *descbuf, bool ps, bool swap,\n+\t\t\t   struct alginfo *cipherdata, uint8_t dir,\n+\t\t\t   uint32_t count, uint8_t bearer, uint8_t direction)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\tuint64_t ct = count;\n+\tuint64_t br = bearer;\n+\tuint64_t dr = direction;\n+\tuint32_t context[2] = { ct, (br << 27) | (dr << 26) };\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap) {\n+\t\tPROGRAM_SET_BSWAP(p);\n+\n+\t\tcontext[0] = swab32(context[0]);\n+\t\tcontext[1] = swab32(context[1]);\n+\t}\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tSHR_HDR(p, SHR_ALWAYS, 1, 0);\n+\n+\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQINSZ, 4, 0);\n+\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQOUTSZ, 4, 0);\n+\tALG_OPERATION(p, OP_ALG_ALGSEL_KASUMI, OP_ALG_AAI_F8,\n+\t\t      OP_ALG_AS_INITFINAL, 0, dir);\n+\tLOAD(p, (uintptr_t)context, CONTEXT1, 0, 8, IMMED | COPY);\n+\tSEQFIFOLOAD(p, MSG1, 0, VLF | LAST1);\n+\tSEQFIFOSTORE(p, MSG, 0, 0, VLF);\n+\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * cnstr_shdsc_kasumi_f9 -  KASUMI F9 (Integrity) as a shared descriptor\n+ *                          (ETSI \"Document 1: f8 and f9 specification\")\n+ * @descbuf: pointer to descriptor-under-construction buffer\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: must be true when core endianness doesn't match SEC endianness\n+ * @authdata: pointer to authentication transform definitions\n+ * @dir: cipher direction (DIR_ENC/DIR_DEC)\n+ * @count: count value (32 bits)\n+ * @fresh: fresh value ID (32 bits)\n+ * @direction: direction (1 bit)\n+ * @datalen: size of data\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_kasumi_f9(uint32_t *descbuf, bool ps, bool swap,\n+\t\t\t   struct alginfo *authdata, uint8_t dir,\n+\t\t\t   uint32_t count, uint32_t fresh, uint8_t direction,\n+\t\t\t   uint32_t datalen)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\tuint16_t ctx_offset = 16;\n+\tuint32_t context[6] = {count, direction << 26, fresh, 0, 0, 0};\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap) {\n+\t\tPROGRAM_SET_BSWAP(p);\n+\n+\t\tcontext[0] = swab32(context[0]);\n+\t\tcontext[1] = swab32(context[1]);\n+\t\tcontext[2] = swab32(context[2]);\n+\t}\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tSHR_HDR(p, SHR_ALWAYS, 1, 0);\n+\n+\tKEY(p, KEY1, authdata->key_enc_flags, authdata->key, authdata->keylen,\n+\t    INLINE_KEY(authdata));\n+\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQINSZ, 4, 0);\n+\tALG_OPERATION(p, OP_ALG_ALGSEL_KASUMI, OP_ALG_AAI_F9,\n+\t\t      OP_ALG_AS_INITFINAL, 0, dir);\n+\tLOAD(p, (uintptr_t)context, CONTEXT1, 0, 24, IMMED | COPY);\n+\tSEQFIFOLOAD(p, BIT_DATA, datalen, CLASS1 | LAST1);\n+\t/* Save output MAC of DWORD 2 into a 32-bit sequence */\n+\tSEQSTORE(p, CONTEXT1, ctx_offset, 4, 0);\n+\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * cnstr_shdsc_crc - CRC32 Accelerator (IEEE 802 CRC32 protocol mode)\n+ * @descbuf: pointer to descriptor-under-construction buffer\n+ * @swap: must be true when core endianness doesn't match SEC endianness\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_crc(uint32_t *descbuf, bool swap)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap)\n+\t\tPROGRAM_SET_BSWAP(p);\n+\n+\tSHR_HDR(p, SHR_ALWAYS, 1, 0);\n+\n+\tMATHB(p, SEQINSZ, SUB, MATH2, VSEQINSZ, 4, 0);\n+\tALG_OPERATION(p, OP_ALG_ALGSEL_CRC,\n+\t\t      OP_ALG_AAI_802 | OP_ALG_AAI_DOC,\n+\t\t      OP_ALG_AS_FINALIZE, 0, DIR_ENC);\n+\tSEQFIFOLOAD(p, MSG2, 0, VLF | LAST2);\n+\tSEQSTORE(p, CONTEXT2, 0, 4, 0);\n+\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+#endif /* __DESC_ALGO_H__ */\ndiff --git a/drivers/crypto/dpaa2_sec/hw/desc/common.h b/drivers/crypto/dpaa2_sec/hw/desc/common.h\nnew file mode 100644\nindex 0000000..d2c97ac\n--- /dev/null\n+++ b/drivers/crypto/dpaa2_sec/hw/desc/common.h\n@@ -0,0 +1,96 @@\n+/*\n+ * Copyright 2008-2016 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier: BSD-3-Clause or GPL-2.0+\n+ */\n+\n+#ifndef __DESC_COMMON_H__\n+#define __DESC_COMMON_H__\n+\n+#include \"hw/rta.h\"\n+\n+/**\n+ * DOC: Shared Descriptor Constructors - shared structures\n+ *\n+ * Data structures shared between algorithm, protocol implementations.\n+ */\n+\n+/**\n+ * struct alginfo - Container for algorithm details\n+ * @algtype: algorithm selector; for valid values, see documentation of the\n+ *           functions where it is used.\n+ * @keylen: length of the provided algorithm key, in bytes\n+ * @key: address where algorithm key resides; virtual address if key_type is\n+ *       RTA_DATA_IMM, physical (bus) address if key_type is RTA_DATA_PTR or\n+ *       RTA_DATA_IMM_DMA.\n+ * @key_enc_flags: key encryption flags; see encrypt_flags parameter of KEY\n+ *                 command for valid values.\n+ * @key_type: enum rta_data_type\n+ * @algmode: algorithm mode selector; for valid values, see documentation of the\n+ *           functions where it is used.\n+ */\n+struct alginfo {\n+\tuint32_t algtype;\n+\tuint32_t keylen;\n+\tuint64_t key;\n+\tuint32_t key_enc_flags;\n+\tenum rta_data_type key_type;\n+\tuint16_t algmode;\n+};\n+\n+#define INLINE_KEY(alginfo)\tinline_flags(alginfo->key_type)\n+\n+/**\n+ * rta_inline_query() - Provide indications on which data items can be inlined\n+ *                      and which shall be referenced in a shared descriptor.\n+ * @sd_base_len: Shared descriptor base length - bytes consumed by the commands,\n+ *               excluding the data items to be inlined (or corresponding\n+ *               pointer if an item is not inlined). Each cnstr_* function that\n+ *               generates descriptors should have a define mentioning\n+ *               corresponding length.\n+ * @jd_len: Maximum length of the job descriptor(s) that will be used\n+ *          together with the shared descriptor.\n+ * @data_len: Array of lengths of the data items trying to be inlined\n+ * @inl_mask: 32bit mask with bit x = 1 if data item x can be inlined, 0\n+ *            otherwise.\n+ * @count: Number of data items (size of @data_len array); must be <= 32\n+ *\n+ * Return: 0 if data can be inlined / referenced, negative value if not. If 0,\n+ *         check @inl_mask for details.\n+ */\n+static inline int rta_inline_query(unsigned int sd_base_len,\n+\t\t\t\t   unsigned int jd_len,\n+\t\t\t\t   unsigned int *data_len,\n+\t\t\t\t   uint32_t *inl_mask,\n+\t\t\t\t   unsigned int count)\n+{\n+\tint rem_bytes = (int)(CAAM_DESC_BYTES_MAX - sd_base_len - jd_len);\n+\tunsigned int i;\n+\n+\t*inl_mask = 0;\n+\tfor (i = 0; (i < count) && (rem_bytes > 0); i++) {\n+\t\tif (rem_bytes - (int)(data_len[i] +\n+\t\t\t(count - i - 1) * CAAM_PTR_SZ) >= 0) {\n+\t\t\trem_bytes -= data_len[i];\n+\t\t\t*inl_mask |= (1 << i);\n+\t\t} else {\n+\t\t\trem_bytes -= CAAM_PTR_SZ;\n+\t\t}\n+\t}\n+\n+\treturn (rem_bytes >= 0) ? 0 : -1;\n+}\n+\n+/**\n+ * struct protcmd - Container for Protocol Operation Command fields\n+ * @optype: command type\n+ * @protid: protocol Identifier\n+ * @protinfo: protocol Information\n+ */\n+struct protcmd {\n+\tuint32_t optype;\n+\tuint32_t protid;\n+\tuint16_t protinfo;\n+};\n+\n+#endif /* __DESC_COMMON_H__ */\ndiff --git a/drivers/crypto/dpaa2_sec/hw/desc/ipsec.h b/drivers/crypto/dpaa2_sec/hw/desc/ipsec.h\nnew file mode 100644\nindex 0000000..ad3b784\n--- /dev/null\n+++ b/drivers/crypto/dpaa2_sec/hw/desc/ipsec.h\n@@ -0,0 +1,1502 @@\n+/*\n+ * Copyright 2008-2016 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier: BSD-3-Clause or GPL-2.0+\n+ */\n+\n+#ifndef __DESC_IPSEC_H__\n+#define __DESC_IPSEC_H__\n+\n+#include \"hw/rta.h\"\n+#include \"common.h\"\n+\n+/**\n+ * DOC: IPsec Shared Descriptor Constructors\n+ *\n+ * Shared descriptors for IPsec protocol.\n+ */\n+\n+/* General IPSec ESP encap / decap PDB options */\n+\n+/**\n+ * PDBOPTS_ESP_ESN - Extended sequence included\n+ */\n+#define PDBOPTS_ESP_ESN\t\t0x10\n+\n+/**\n+ * PDBOPTS_ESP_IPVSN - Process IPv6 header\n+ *\n+ * Valid only for IPsec legacy mode.\n+ */\n+#define PDBOPTS_ESP_IPVSN\t0x02\n+\n+/**\n+ * PDBOPTS_ESP_TUNNEL - Tunnel mode next-header byte\n+ *\n+ * Valid only for IPsec legacy mode.\n+ */\n+#define PDBOPTS_ESP_TUNNEL\t0x01\n+\n+/* IPSec ESP Encap PDB options */\n+\n+/**\n+ * PDBOPTS_ESP_UPDATE_CSUM - Update ip header checksum\n+ *\n+ * Valid only for IPsec legacy mode.\n+ */\n+#define PDBOPTS_ESP_UPDATE_CSUM 0x80\n+\n+/**\n+ * PDBOPTS_ESP_DIFFSERV - Copy TOS/TC from inner iphdr\n+ *\n+ * Valid only for IPsec legacy mode.\n+ */\n+#define PDBOPTS_ESP_DIFFSERV\t0x40\n+\n+/**\n+ * PDBOPTS_ESP_IVSRC - IV comes from internal random gen\n+ */\n+#define PDBOPTS_ESP_IVSRC\t0x20\n+\n+/**\n+ * PDBOPTS_ESP_IPHDRSRC - IP header comes from PDB\n+ *\n+ * Valid only for IPsec legacy mode.\n+ */\n+#define PDBOPTS_ESP_IPHDRSRC\t0x08\n+\n+/**\n+ * PDBOPTS_ESP_INCIPHDR - Prepend IP header to output frame\n+ *\n+ * Valid only for IPsec legacy mode.\n+ */\n+#define PDBOPTS_ESP_INCIPHDR\t0x04\n+\n+/**\n+ * PDBOPTS_ESP_OIHI_MASK - Mask for Outer IP Header Included\n+ *\n+ * Valid only for IPsec new mode.\n+ */\n+#define PDBOPTS_ESP_OIHI_MASK\t0x0c\n+\n+/**\n+ * PDBOPTS_ESP_OIHI_PDB_INL - Prepend IP header to output frame from PDB (where\n+ *                            it is inlined).\n+ *\n+ * Valid only for IPsec new mode.\n+ */\n+#define PDBOPTS_ESP_OIHI_PDB_INL 0x0c\n+\n+/**\n+ * PDBOPTS_ESP_OIHI_PDB_REF - Prepend IP header to output frame from PDB\n+ *                            (referenced by pointer).\n+ *\n+ * Vlid only for IPsec new mode.\n+ */\n+#define PDBOPTS_ESP_OIHI_PDB_REF 0x08\n+\n+/**\n+ * PDBOPTS_ESP_OIHI_IF - Prepend IP header to output frame from input frame\n+ *\n+ * Valid only for IPsec new mode.\n+ */\n+#define PDBOPTS_ESP_OIHI_IF\t0x04\n+\n+/**\n+ * PDBOPTS_ESP_NAT - Enable RFC 3948 UDP-encapsulated-ESP\n+ *\n+ * Valid only for IPsec new mode.\n+ */\n+#define PDBOPTS_ESP_NAT\t\t0x02\n+\n+/**\n+ * PDBOPTS_ESP_NUC - Enable NAT UDP Checksum\n+ *\n+ * Valid only for IPsec new mode.\n+ */\n+#define PDBOPTS_ESP_NUC\t\t0x01\n+\n+/* IPSec ESP Decap PDB options */\n+\n+/**\n+ * PDBOPTS_ESP_ARS_MASK - antireplay window mask\n+ */\n+#define PDBOPTS_ESP_ARS_MASK\t0xc0\n+\n+/**\n+ * PDBOPTS_ESP_ARSNONE - No antireplay window\n+ */\n+#define PDBOPTS_ESP_ARSNONE\t0x00\n+\n+/**\n+ * PDBOPTS_ESP_ARS64 - 64-entry antireplay window\n+ */\n+#define PDBOPTS_ESP_ARS64\t0xc0\n+\n+/**\n+ * PDBOPTS_ESP_ARS128 - 128-entry antireplay window\n+ *\n+ * Valid only for IPsec new mode.\n+ */\n+#define PDBOPTS_ESP_ARS128\t0x80\n+\n+/**\n+ * PDBOPTS_ESP_ARS32 - 32-entry antireplay window\n+ */\n+#define PDBOPTS_ESP_ARS32\t0x40\n+\n+/**\n+ * PDBOPTS_ESP_VERIFY_CSUM - Validate ip header checksum\n+ *\n+ * Valid only for IPsec legacy mode.\n+ */\n+#define PDBOPTS_ESP_VERIFY_CSUM 0x20\n+\n+/**\n+ * PDBOPTS_ESP_TECN - Implement RRFC6040 ECN tunneling from outer header to\n+ *                    inner header.\n+ *\n+ * Valid only for IPsec new mode.\n+ */\n+#define PDBOPTS_ESP_TECN\t0x20\n+\n+/**\n+ * PDBOPTS_ESP_OUTFMT - Output only decapsulation\n+ *\n+ * Valid only for IPsec legacy mode.\n+ */\n+#define PDBOPTS_ESP_OUTFMT\t0x08\n+\n+/**\n+ * PDBOPTS_ESP_AOFL - Adjust out frame len\n+ *\n+ * Valid only for IPsec legacy mode and for SEC >= 5.3.\n+ */\n+#define PDBOPTS_ESP_AOFL\t0x04\n+\n+/**\n+ * PDBOPTS_ESP_ETU - EtherType Update\n+ *\n+ * Add corresponding ethertype (0x0800 for IPv4, 0x86dd for IPv6) in the output\n+ * frame.\n+ * Valid only for IPsec new mode.\n+ */\n+#define PDBOPTS_ESP_ETU\t\t0x01\n+\n+#define PDBHMO_ESP_DECAP_SHIFT\t\t28\n+#define PDBHMO_ESP_ENCAP_SHIFT\t\t28\n+#define PDBNH_ESP_ENCAP_SHIFT\t\t16\n+#define PDBNH_ESP_ENCAP_MASK\t\t(0xff << PDBNH_ESP_ENCAP_SHIFT)\n+#define PDBHDRLEN_ESP_DECAP_SHIFT\t16\n+#define PDBHDRLEN_MASK\t\t\t(0x0fff << PDBHDRLEN_ESP_DECAP_SHIFT)\n+#define PDB_NH_OFFSET_SHIFT\t\t8\n+#define PDB_NH_OFFSET_MASK\t\t(0xff << PDB_NH_OFFSET_SHIFT)\n+\n+/**\n+ * PDBHMO_ESP_DECAP_DTTL - IPsec ESP decrement TTL (IPv4) / Hop limit (IPv6)\n+ *                         HMO option.\n+ */\n+#define PDBHMO_ESP_DECAP_DTTL\t(0x02 << PDBHMO_ESP_DECAP_SHIFT)\n+\n+/**\n+ * PDBHMO_ESP_ENCAP_DTTL - IPsec ESP increment TTL (IPv4) / Hop limit (IPv6)\n+ *                         HMO option.\n+ */\n+#define PDBHMO_ESP_ENCAP_DTTL\t(0x02 << PDBHMO_ESP_ENCAP_SHIFT)\n+\n+/**\n+ * PDBHMO_ESP_DIFFSERV - (Decap) DiffServ Copy - Copy the IPv4 TOS or IPv6\n+ *                       Traffic Class byte from the outer IP header to the\n+ *                       inner IP header.\n+ */\n+#define PDBHMO_ESP_DIFFSERV\t(0x01 << PDBHMO_ESP_DECAP_SHIFT)\n+\n+/**\n+ * PDBHMO_ESP_SNR - (Encap) - Sequence Number Rollover control\n+ *\n+ * Configures behaviour in case of SN / ESN rollover:\n+ * error if SNR = 1, rollover allowed if SNR = 0.\n+ * Valid only for IPsec new mode.\n+ */\n+#define PDBHMO_ESP_SNR\t\t(0x01 << PDBHMO_ESP_ENCAP_SHIFT)\n+\n+/**\n+ * PDBHMO_ESP_DFBIT - (Encap) Copy DF bit - if an IPv4 tunnel mode outer IP\n+ *                    header is coming from the PDB, copy the DF bit from the\n+ *                    inner IP header to the outer IP header.\n+ */\n+#define PDBHMO_ESP_DFBIT\t(0x04 << PDBHMO_ESP_ENCAP_SHIFT)\n+\n+/**\n+ * PDBHMO_ESP_DFV - (Decap) - DF bit value\n+ *\n+ * If ODF = 1, DF bit in output frame is replaced by DFV.\n+ * Valid only from SEC Era 5 onwards.\n+ */\n+#define PDBHMO_ESP_DFV\t\t(0x04 << PDBHMO_ESP_DECAP_SHIFT)\n+\n+/**\n+ * PDBHMO_ESP_ODF - (Decap) Override DF bit in IPv4 header of decapsulated\n+ *                  output frame.\n+ *\n+ * If ODF = 1, DF is replaced with the value of DFV bit.\n+ * Valid only from SEC Era 5 onwards.\n+ */\n+#define PDBHMO_ESP_ODF\t\t(0x08 << PDBHMO_ESP_DECAP_SHIFT)\n+\n+/**\n+ * struct ipsec_encap_cbc - PDB part for IPsec CBC encapsulation\n+ * @iv: 16-byte array initialization vector\n+ */\n+struct ipsec_encap_cbc {\n+\tuint8_t iv[16];\n+};\n+\n+\n+/**\n+ * struct ipsec_encap_ctr - PDB part for IPsec CTR encapsulation\n+ * @ctr_nonce: 4-byte array nonce\n+ * @ctr_initial: initial count constant\n+ * @iv: initialization vector\n+ */\n+struct ipsec_encap_ctr {\n+\tuint8_t ctr_nonce[4];\n+\tuint32_t ctr_initial;\n+\tuint64_t iv;\n+};\n+\n+/**\n+ * struct ipsec_encap_ccm - PDB part for IPsec CCM encapsulation\n+ * @salt: 3-byte array salt (lower 24 bits)\n+ * @ccm_opt: CCM algorithm options - MSB-LSB description:\n+ *  b0_flags (8b) - CCM B0; use 0x5B for 8-byte ICV, 0x6B for 12-byte ICV,\n+ *    0x7B for 16-byte ICV (cf. RFC4309, RFC3610)\n+ *  ctr_flags (8b) - counter flags; constant equal to 0x3\n+ *  ctr_initial (16b) - initial count constant\n+ * @iv: initialization vector\n+ */\n+struct ipsec_encap_ccm {\n+\tuint8_t salt[4];\n+\tuint32_t ccm_opt;\n+\tuint64_t iv;\n+};\n+\n+/**\n+ * struct ipsec_encap_gcm - PDB part for IPsec GCM encapsulation\n+ * @salt: 3-byte array salt (lower 24 bits)\n+ * @rsvd: reserved, do not use\n+ * @iv: initialization vector\n+ */\n+struct ipsec_encap_gcm {\n+\tuint8_t salt[4];\n+\tuint32_t rsvd;\n+\tuint64_t iv;\n+};\n+\n+/**\n+ * struct ipsec_encap_pdb - PDB for IPsec encapsulation\n+ * @options: MSB-LSB description (both for legacy and new modes)\n+ *  hmo (header manipulation options) - 4b\n+ *  reserved - 4b\n+ *  next header (legacy) / reserved (new) - 8b\n+ *  next header offset (legacy) / AOIPHO (actual outer IP header offset) - 8b\n+ *  option flags (depend on selected algorithm) - 8b\n+ * @seq_num_ext_hi: (optional) IPsec Extended Sequence Number (ESN)\n+ * @seq_num: IPsec sequence number\n+ * @spi: IPsec SPI (Security Parameters Index)\n+ * @ip_hdr_len: optional IP Header length (in bytes)\n+ *  reserved - 16b\n+ *  Opt. IP Hdr Len - 16b\n+ * @ip_hdr: optional IP Header content (only for IPsec legacy mode)\n+ */\n+struct ipsec_encap_pdb {\n+\tuint32_t options;\n+\tuint32_t seq_num_ext_hi;\n+\tuint32_t seq_num;\n+\tunion {\n+\t\tstruct ipsec_encap_cbc cbc;\n+\t\tstruct ipsec_encap_ctr ctr;\n+\t\tstruct ipsec_encap_ccm ccm;\n+\t\tstruct ipsec_encap_gcm gcm;\n+\t};\n+\tuint32_t spi;\n+\tuint32_t ip_hdr_len;\n+\tuint8_t ip_hdr[0];\n+};\n+\n+static inline unsigned int __rta_copy_ipsec_encap_pdb(struct program *program,\n+\t\t\t\t\t\t  struct ipsec_encap_pdb *pdb,\n+\t\t\t\t\t\t  uint32_t algtype)\n+{\n+\tunsigned int start_pc = program->current_pc;\n+\n+\t__rta_out32(program, pdb->options);\n+\t__rta_out32(program, pdb->seq_num_ext_hi);\n+\t__rta_out32(program, pdb->seq_num);\n+\n+\tswitch (algtype & OP_PCL_IPSEC_CIPHER_MASK) {\n+\tcase OP_PCL_IPSEC_DES_IV64:\n+\tcase OP_PCL_IPSEC_DES:\n+\tcase OP_PCL_IPSEC_3DES:\n+\tcase OP_PCL_IPSEC_AES_CBC:\n+\tcase OP_PCL_IPSEC_NULL:\n+\t\trta_copy_data(program, pdb->cbc.iv, sizeof(pdb->cbc.iv));\n+\t\tbreak;\n+\n+\tcase OP_PCL_IPSEC_AES_CTR:\n+\t\trta_copy_data(program, pdb->ctr.ctr_nonce,\n+\t\t\t      sizeof(pdb->ctr.ctr_nonce));\n+\t\t__rta_out32(program, pdb->ctr.ctr_initial);\n+\t\t__rta_out64(program, true, pdb->ctr.iv);\n+\t\tbreak;\n+\n+\tcase OP_PCL_IPSEC_AES_CCM8:\n+\tcase OP_PCL_IPSEC_AES_CCM12:\n+\tcase OP_PCL_IPSEC_AES_CCM16:\n+\t\trta_copy_data(program, pdb->ccm.salt, sizeof(pdb->ccm.salt));\n+\t\t__rta_out32(program, pdb->ccm.ccm_opt);\n+\t\t__rta_out64(program, true, pdb->ccm.iv);\n+\t\tbreak;\n+\n+\tcase OP_PCL_IPSEC_AES_GCM8:\n+\tcase OP_PCL_IPSEC_AES_GCM12:\n+\tcase OP_PCL_IPSEC_AES_GCM16:\n+\tcase OP_PCL_IPSEC_AES_NULL_WITH_GMAC:\n+\t\trta_copy_data(program, pdb->gcm.salt, sizeof(pdb->gcm.salt));\n+\t\t__rta_out32(program, pdb->gcm.rsvd);\n+\t\t__rta_out64(program, true, pdb->gcm.iv);\n+\t\tbreak;\n+\t}\n+\n+\t__rta_out32(program, pdb->spi);\n+\t__rta_out32(program, pdb->ip_hdr_len);\n+\n+\treturn start_pc;\n+}\n+\n+/**\n+ * struct ipsec_decap_cbc - PDB part for IPsec CBC decapsulation\n+ * @rsvd: reserved, do not use\n+ */\n+struct ipsec_decap_cbc {\n+\tuint32_t rsvd[2];\n+};\n+\n+/**\n+ * struct ipsec_decap_ctr - PDB part for IPsec CTR decapsulation\n+ * @ctr_nonce: 4-byte array nonce\n+ * @ctr_initial: initial count constant\n+ */\n+struct ipsec_decap_ctr {\n+\tuint8_t ctr_nonce[4];\n+\tuint32_t ctr_initial;\n+};\n+\n+/**\n+ * struct ipsec_decap_ccm - PDB part for IPsec CCM decapsulation\n+ * @salt: 3-byte salt (lower 24 bits)\n+ * @ccm_opt: CCM algorithm options - MSB-LSB description:\n+ *  b0_flags (8b) - CCM B0; use 0x5B for 8-byte ICV, 0x6B for 12-byte ICV,\n+ *    0x7B for 16-byte ICV (cf. RFC4309, RFC3610)\n+ *  ctr_flags (8b) - counter flags; constant equal to 0x3\n+ *  ctr_initial (16b) - initial count constant\n+ */\n+struct ipsec_decap_ccm {\n+\tuint8_t salt[4];\n+\tuint32_t ccm_opt;\n+};\n+\n+/**\n+ * struct ipsec_decap_gcm - PDB part for IPsec GCN decapsulation\n+ * @salt: 4-byte salt\n+ * @rsvd: reserved, do not use\n+ */\n+struct ipsec_decap_gcm {\n+\tuint8_t salt[4];\n+\tuint32_t rsvd;\n+};\n+\n+/**\n+ * struct ipsec_decap_pdb - PDB for IPsec decapsulation\n+ * @options: MSB-LSB description (both for legacy and new modes)\n+ *  hmo (header manipulation options) - 4b\n+ *  IP header length - 12b\n+ *  next header offset (legacy) / AOIPHO (actual outer IP header offset) - 8b\n+ *  option flags (depend on selected algorithm) - 8b\n+ * @seq_num_ext_hi: (optional) IPsec Extended Sequence Number (ESN)\n+ * @seq_num: IPsec sequence number\n+ * @anti_replay: Anti-replay window; size depends on ARS (option flags);\n+ *  format must be Big Endian, irrespective of platform\n+ */\n+struct ipsec_decap_pdb {\n+\tuint32_t options;\n+\tunion {\n+\t\tstruct ipsec_decap_cbc cbc;\n+\t\tstruct ipsec_decap_ctr ctr;\n+\t\tstruct ipsec_decap_ccm ccm;\n+\t\tstruct ipsec_decap_gcm gcm;\n+\t};\n+\tuint32_t seq_num_ext_hi;\n+\tuint32_t seq_num;\n+\tuint32_t anti_replay[4];\n+};\n+\n+static inline unsigned int __rta_copy_ipsec_decap_pdb(struct program *program,\n+\t\t\t\t\t\t  struct ipsec_decap_pdb *pdb,\n+\t\t\t\t\t\t  uint32_t algtype)\n+{\n+\tunsigned int start_pc = program->current_pc;\n+\tunsigned int i, ars;\n+\n+\t__rta_out32(program, pdb->options);\n+\n+\tswitch (algtype & OP_PCL_IPSEC_CIPHER_MASK) {\n+\tcase OP_PCL_IPSEC_DES_IV64:\n+\tcase OP_PCL_IPSEC_DES:\n+\tcase OP_PCL_IPSEC_3DES:\n+\tcase OP_PCL_IPSEC_AES_CBC:\n+\tcase OP_PCL_IPSEC_NULL:\n+\t\t__rta_out32(program, pdb->cbc.rsvd[0]);\n+\t\t__rta_out32(program, pdb->cbc.rsvd[1]);\n+\t\tbreak;\n+\n+\tcase OP_PCL_IPSEC_AES_CTR:\n+\t\trta_copy_data(program, pdb->ctr.ctr_nonce,\n+\t\t\t      sizeof(pdb->ctr.ctr_nonce));\n+\t\t__rta_out32(program, pdb->ctr.ctr_initial);\n+\t\tbreak;\n+\n+\tcase OP_PCL_IPSEC_AES_CCM8:\n+\tcase OP_PCL_IPSEC_AES_CCM12:\n+\tcase OP_PCL_IPSEC_AES_CCM16:\n+\t\trta_copy_data(program, pdb->ccm.salt, sizeof(pdb->ccm.salt));\n+\t\t__rta_out32(program, pdb->ccm.ccm_opt);\n+\t\tbreak;\n+\n+\tcase OP_PCL_IPSEC_AES_GCM8:\n+\tcase OP_PCL_IPSEC_AES_GCM12:\n+\tcase OP_PCL_IPSEC_AES_GCM16:\n+\tcase OP_PCL_IPSEC_AES_NULL_WITH_GMAC:\n+\t\trta_copy_data(program, pdb->gcm.salt, sizeof(pdb->gcm.salt));\n+\t\t__rta_out32(program, pdb->gcm.rsvd);\n+\t\tbreak;\n+\t}\n+\n+\t__rta_out32(program, pdb->seq_num_ext_hi);\n+\t__rta_out32(program, pdb->seq_num);\n+\n+\tswitch (pdb->options & PDBOPTS_ESP_ARS_MASK) {\n+\tcase PDBOPTS_ESP_ARS128:\n+\t\tars = 4;\n+\t\tbreak;\n+\tcase PDBOPTS_ESP_ARS64:\n+\t\tars = 2;\n+\t\tbreak;\n+\tcase PDBOPTS_ESP_ARS32:\n+\t\tars = 1;\n+\t\tbreak;\n+\tcase PDBOPTS_ESP_ARSNONE:\n+\tdefault:\n+\t\tars = 0;\n+\t\tbreak;\n+\t}\n+\n+\tfor (i = 0; i < ars; i++)\n+\t\t__rta_out_be32(program, pdb->anti_replay[i]);\n+\n+\treturn start_pc;\n+}\n+\n+/**\n+ * enum ipsec_icv_size - Type selectors for icv size in IPsec protocol\n+ * @IPSEC_ICV_MD5_SIZE: full-length MD5 ICV\n+ * @IPSEC_ICV_MD5_TRUNC_SIZE: truncated MD5 ICV\n+ */\n+enum ipsec_icv_size {\n+\tIPSEC_ICV_MD5_SIZE = 16,\n+\tIPSEC_ICV_MD5_TRUNC_SIZE = 12\n+};\n+\n+/*\n+ * IPSec ESP Datapath Protocol Override Register (DPOVRD)\n+ */\n+\n+#define IPSEC_DECO_DPOVRD_USE\t\t0x80\n+\n+struct ipsec_deco_dpovrd {\n+\tuint8_t ovrd_ecn;\n+\tuint8_t ip_hdr_len;\n+\tuint8_t nh_offset;\n+\tunion {\n+\t\tuint8_t next_header;\t/* next header if encap */\n+\t\tuint8_t rsvd;\t\t/* reserved if decap */\n+\t};\n+};\n+\n+struct ipsec_new_encap_deco_dpovrd {\n+#define IPSEC_NEW_ENCAP_DECO_DPOVRD_USE\t0x8000\n+\tuint16_t ovrd_ip_hdr_len;\t/* OVRD + outer IP header material\n+\t\t\t\t\t * length\n+\t\t\t\t\t */\n+#define IPSEC_NEW_ENCAP_OIMIF\t\t0x80\n+\tuint8_t oimif_aoipho;\t\t/* OIMIF + actual outer IP header\n+\t\t\t\t\t * offset\n+\t\t\t\t\t */\n+\tuint8_t rsvd;\n+};\n+\n+struct ipsec_new_decap_deco_dpovrd {\n+\tuint8_t ovrd;\n+\tuint8_t aoipho_hi;\t\t/* upper nibble of actual outer IP\n+\t\t\t\t\t * header\n+\t\t\t\t\t */\n+\tuint16_t aoipho_lo_ip_hdr_len;\t/* lower nibble of actual outer IP\n+\t\t\t\t\t * header + outer IP header material\n+\t\t\t\t\t */\n+};\n+\n+static inline void __gen_auth_key(struct program *program,\n+\t\t\t\t  struct alginfo *authdata)\n+{\n+\tuint32_t dkp_protid;\n+\n+\tswitch (authdata->algtype & OP_PCL_IPSEC_AUTH_MASK) {\n+\tcase OP_PCL_IPSEC_HMAC_MD5_96:\n+\tcase OP_PCL_IPSEC_HMAC_MD5_128:\n+\t\tdkp_protid = OP_PCLID_DKP_MD5;\n+\t\tbreak;\n+\tcase OP_PCL_IPSEC_HMAC_SHA1_96:\n+\tcase OP_PCL_IPSEC_HMAC_SHA1_160:\n+\t\tdkp_protid = OP_PCLID_DKP_SHA1;\n+\t\tbreak;\n+\tcase OP_PCL_IPSEC_HMAC_SHA2_256_128:\n+\t\tdkp_protid = OP_PCLID_DKP_SHA256;\n+\t\tbreak;\n+\tcase OP_PCL_IPSEC_HMAC_SHA2_384_192:\n+\t\tdkp_protid = OP_PCLID_DKP_SHA384;\n+\t\tbreak;\n+\tcase OP_PCL_IPSEC_HMAC_SHA2_512_256:\n+\t\tdkp_protid = OP_PCLID_DKP_SHA512;\n+\t\tbreak;\n+\tdefault:\n+\t\tKEY(program, KEY2, authdata->key_enc_flags, authdata->key,\n+\t\t    authdata->keylen, INLINE_KEY(authdata));\n+\t\treturn;\n+\t}\n+\n+\tif (authdata->key_type == RTA_DATA_PTR)\n+\t\tDKP_PROTOCOL(program, dkp_protid, OP_PCL_DKP_SRC_PTR,\n+\t\t\t     OP_PCL_DKP_DST_PTR, (uint16_t)authdata->keylen,\n+\t\t\t     authdata->key, authdata->key_type);\n+\telse\n+\t\tDKP_PROTOCOL(program, dkp_protid, OP_PCL_DKP_SRC_IMM,\n+\t\t\t     OP_PCL_DKP_DST_IMM, (uint16_t)authdata->keylen,\n+\t\t\t     authdata->key, authdata->key_type);\n+}\n+\n+/**\n+ * cnstr_shdsc_ipsec_encap - IPSec ESP encapsulation protocol-level shared\n+ *                           descriptor.\n+ * @descbuf: pointer to buffer used for descriptor construction\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: if true, perform descriptor byte swapping on a 4-byte boundary\n+ * @pdb: pointer to the PDB to be used with this descriptor\n+ *       This structure will be copied inline to the descriptor under\n+ *       construction. No error checking will be made. Refer to the\n+ *       block guide for a details of the encapsulation PDB.\n+ * @cipherdata: pointer to block cipher transform definitions\n+ *              Valid algorithm values - one of OP_PCL_IPSEC_*\n+ * @authdata: pointer to authentication transform definitions\n+ *            If an authentication key is required by the protocol:\n+ *            -For SEC Eras 1-5, an MDHA split key must be provided;\n+ *            Note that the size of the split key itself must be specified.\n+ *            -For SEC Eras 6+, a \"normal\" key must be provided; DKP (Derived\n+ *            Key Protocol) will be used to compute MDHA on the fly in HW.\n+ *            Valid algorithm values - one of OP_PCL_IPSEC_*\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_ipsec_encap(uint32_t *descbuf, bool ps, bool swap,\n+\t\t\t\t\t  struct ipsec_encap_pdb *pdb,\n+\t\t\t\t\t  struct alginfo *cipherdata,\n+\t\t\t\t\t  struct alginfo *authdata)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\n+\tLABEL(keyjmp);\n+\tREFERENCE(pkeyjmp);\n+\tLABEL(hdr);\n+\tREFERENCE(phdr);\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap)\n+\t\tPROGRAM_SET_BSWAP(p);\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tphdr = SHR_HDR(p, SHR_SERIAL, hdr, 0);\n+\t__rta_copy_ipsec_encap_pdb(p, pdb, cipherdata->algtype);\n+\tCOPY_DATA(p, pdb->ip_hdr, pdb->ip_hdr_len);\n+\tSET_LABEL(p, hdr);\n+\tpkeyjmp = JUMP(p, keyjmp, LOCAL_JUMP, ALL_TRUE, BOTH|SHRD);\n+\tif (authdata->keylen) {\n+\t\tif (rta_sec_era < RTA_SEC_ERA_6)\n+\t\t\tKEY(p, MDHA_SPLIT_KEY, authdata->key_enc_flags,\n+\t\t\t    authdata->key, authdata->keylen,\n+\t\t\t    INLINE_KEY(authdata));\n+\t\telse\n+\t\t\t__gen_auth_key(p, authdata);\n+\t}\n+\tif (cipherdata->keylen)\n+\t\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\tSET_LABEL(p, keyjmp);\n+\tPROTOCOL(p, OP_TYPE_ENCAP_PROTOCOL,\n+\t\t OP_PCLID_IPSEC,\n+\t\t (uint16_t)(cipherdata->algtype | authdata->algtype));\n+\tPATCH_JUMP(p, pkeyjmp, keyjmp);\n+\tPATCH_HDR(p, phdr, hdr);\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * cnstr_shdsc_ipsec_decap - IPSec ESP decapsulation protocol-level shared\n+ *                           descriptor.\n+ * @descbuf: pointer to buffer used for descriptor construction\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: if true, perform descriptor byte swapping on a 4-byte boundary\n+ * @pdb: pointer to the PDB to be used with this descriptor\n+ *       This structure will be copied inline to the descriptor under\n+ *       construction. No error checking will be made. Refer to the\n+ *       block guide for details about the decapsulation PDB.\n+ * @cipherdata: pointer to block cipher transform definitions.\n+ *              Valid algorithm values - one of OP_PCL_IPSEC_*\n+ * @authdata: pointer to authentication transform definitions\n+ *            If an authentication key is required by the protocol:\n+ *            -For SEC Eras 1-5, an MDHA split key must be provided;\n+ *            Note that the size of the split key itself must be specified.\n+ *            -For SEC Eras 6+, a \"normal\" key must be provided; DKP (Derived\n+ *            Key Protocol) will be used to compute MDHA on the fly in HW.\n+ *            Valid algorithm values - one of OP_PCL_IPSEC_*\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_ipsec_decap(uint32_t *descbuf, bool ps, bool swap,\n+\t\t\t\t\t  struct ipsec_decap_pdb *pdb,\n+\t\t\t\t\t  struct alginfo *cipherdata,\n+\t\t\t\t\t  struct alginfo *authdata)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\n+\tLABEL(keyjmp);\n+\tREFERENCE(pkeyjmp);\n+\tLABEL(hdr);\n+\tREFERENCE(phdr);\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap)\n+\t\tPROGRAM_SET_BSWAP(p);\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tphdr = SHR_HDR(p, SHR_SERIAL, hdr, 0);\n+\t__rta_copy_ipsec_decap_pdb(p, pdb, cipherdata->algtype);\n+\tSET_LABEL(p, hdr);\n+\tpkeyjmp = JUMP(p, keyjmp, LOCAL_JUMP, ALL_TRUE, BOTH|SHRD);\n+\tif (authdata->keylen) {\n+\t\tif (rta_sec_era < RTA_SEC_ERA_6)\n+\t\t\tKEY(p, MDHA_SPLIT_KEY, authdata->key_enc_flags,\n+\t\t\t    authdata->key, authdata->keylen,\n+\t\t\t    INLINE_KEY(authdata));\n+\t\telse\n+\t\t\t__gen_auth_key(p, authdata);\n+\t}\n+\tif (cipherdata->keylen)\n+\t\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\tSET_LABEL(p, keyjmp);\n+\tPROTOCOL(p, OP_TYPE_DECAP_PROTOCOL,\n+\t\t OP_PCLID_IPSEC,\n+\t\t (uint16_t)(cipherdata->algtype | authdata->algtype));\n+\tPATCH_JUMP(p, pkeyjmp, keyjmp);\n+\tPATCH_HDR(p, phdr, hdr);\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * cnstr_shdsc_ipsec_encap_des_aes_xcbc - IPSec DES-CBC/3DES-CBC and\n+ *     AES-XCBC-MAC-96 ESP encapsulation shared descriptor.\n+ * @descbuf: pointer to buffer used for descriptor construction\n+ * @pdb: pointer to the PDB to be used with this descriptor\n+ *       This structure will be copied inline to the descriptor under\n+ *       construction. No error checking will be made. Refer to the\n+ *       block guide for a details of the encapsulation PDB.\n+ * @cipherdata: pointer to block cipher transform definitions\n+ *              Valid algorithm values - OP_PCL_IPSEC_DES, OP_PCL_IPSEC_3DES.\n+ * @authdata: pointer to authentication transform definitions\n+ *            Valid algorithm value: OP_PCL_IPSEC_AES_XCBC_MAC_96.\n+ *\n+ * Supported only for platforms with 32-bit address pointers and SEC ERA 4 or\n+ * higher. The tunnel/transport mode of the IPsec ESP is supported only if the\n+ * Outer/Transport IP Header is present in the encapsulation output packet.\n+ * The descriptor performs DES-CBC/3DES-CBC & HMAC-MD5-96 and then rereads\n+ * the input packet to do the AES-XCBC-MAC-96 calculation and to overwrite\n+ * the MD5 ICV.\n+ * The descriptor uses all the benefits of the built-in protocol by computing\n+ * the IPsec ESP with a hardware supported algorithms combination\n+ * (DES-CBC/3DES-CBC & HMAC-MD5-96). The HMAC-MD5 authentication algorithm\n+ * was chosen in order to speed up the computational time for this intermediate\n+ * step.\n+ * Warning: The user must allocate at least 32 bytes for the authentication key\n+ * (in order to use it also with HMAC-MD5-96),even when using a shorter key\n+ * for the AES-XCBC-MAC-96.\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_ipsec_encap_des_aes_xcbc(uint32_t *descbuf,\n+\t\tstruct ipsec_encap_pdb *pdb, struct alginfo *cipherdata,\n+\t\tstruct alginfo *authdata)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\n+\tLABEL(hdr);\n+\tLABEL(shd_ptr);\n+\tLABEL(keyjump);\n+\tLABEL(outptr);\n+\tLABEL(swapped_seqin_fields);\n+\tLABEL(swapped_seqin_ptr);\n+\tREFERENCE(phdr);\n+\tREFERENCE(pkeyjump);\n+\tREFERENCE(move_outlen);\n+\tREFERENCE(move_seqout_ptr);\n+\tREFERENCE(swapped_seqin_ptr_jump);\n+\tREFERENCE(write_swapped_seqin_ptr);\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tphdr = SHR_HDR(p, SHR_SERIAL, hdr, 0);\n+\t__rta_copy_ipsec_encap_pdb(p, pdb, cipherdata->algtype);\n+\tCOPY_DATA(p, pdb->ip_hdr, pdb->ip_hdr_len);\n+\tSET_LABEL(p, hdr);\n+\tpkeyjump = JUMP(p, keyjump, LOCAL_JUMP, ALL_TRUE, SHRD | SELF);\n+\t/*\n+\t * Hard-coded KEY arguments. The descriptor uses all the benefits of\n+\t * the built-in protocol by computing the IPsec ESP with a hardware\n+\t * supported algorithms combination (DES-CBC/3DES-CBC & HMAC-MD5-96).\n+\t * The HMAC-MD5 authentication algorithm was chosen with\n+\t * the keys options from below in order to speed up the computational\n+\t * time for this intermediate step.\n+\t * Warning: The user must allocate at least 32 bytes for\n+\t * the authentication key (in order to use it also with HMAC-MD5-96),\n+\t * even when using a shorter key for the AES-XCBC-MAC-96.\n+\t */\n+\tKEY(p, MDHA_SPLIT_KEY, 0, authdata->key, 32, INLINE_KEY(authdata));\n+\tSET_LABEL(p, keyjump);\n+\tLOAD(p, LDST_SRCDST_WORD_CLRW | CLRW_CLR_C1MODE | CLRW_CLR_C1DATAS |\n+\t     CLRW_CLR_C1CTX | CLRW_CLR_C1KEY | CLRW_RESET_CLS1_CHA, CLRW, 0, 4,\n+\t     IMMED);\n+\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\tPROTOCOL(p, OP_TYPE_ENCAP_PROTOCOL, OP_PCLID_IPSEC,\n+\t\t (uint16_t)(cipherdata->algtype | OP_PCL_IPSEC_HMAC_MD5_96));\n+\t/* Swap SEQINPTR to SEQOUTPTR. */\n+\tmove_seqout_ptr = MOVE(p, DESCBUF, 0, MATH1, 0, 16, WAITCOMP | IMMED);\n+\tMATHB(p, MATH1, AND, ~(CMD_SEQ_IN_PTR ^ CMD_SEQ_OUT_PTR), MATH1,\n+\t      8, IFB | IMMED2);\n+/*\n+ * TODO: RTA currently doesn't support creating a LOAD command\n+ * with another command as IMM.\n+ * To be changed when proper support is added in RTA.\n+ */\n+\tLOAD(p, 0xa00000e5, MATH3, 4, 4, IMMED);\n+\tMATHB(p, MATH3, SHLD, MATH3, MATH3,  8, 0);\n+\twrite_swapped_seqin_ptr = MOVE(p, MATH1, 0, DESCBUF, 0, 20, WAITCOMP |\n+\t\t\t\t       IMMED);\n+\tswapped_seqin_ptr_jump = JUMP(p, swapped_seqin_ptr, LOCAL_JUMP,\n+\t\t\t\t      ALL_TRUE, 0);\n+\tLOAD(p, LDST_SRCDST_WORD_CLRW | CLRW_CLR_C1MODE | CLRW_CLR_C1DATAS |\n+\t     CLRW_CLR_C1CTX | CLRW_CLR_C1KEY | CLRW_RESET_CLS1_CHA, CLRW, 0, 4,\n+\t     0);\n+\tSEQOUTPTR(p, 0, 65535, RTO);\n+\tmove_outlen = MOVE(p, DESCBUF, 0, MATH0, 4, 8, WAITCOMP | IMMED);\n+\tMATHB(p, MATH0, SUB,\n+\t      (uint64_t)(pdb->ip_hdr_len + IPSEC_ICV_MD5_TRUNC_SIZE),\n+\t      VSEQINSZ, 4, IMMED2);\n+\tMATHB(p, MATH0, SUB, IPSEC_ICV_MD5_TRUNC_SIZE, VSEQOUTSZ, 4, IMMED2);\n+\tKEY(p, KEY1, authdata->key_enc_flags, authdata->key, authdata->keylen,\n+\t    0);\n+\tALG_OPERATION(p, OP_ALG_ALGSEL_AES, OP_ALG_AAI_XCBC_MAC,\n+\t\t      OP_ALG_AS_INITFINAL, ICV_CHECK_DISABLE, DIR_ENC);\n+\tSEQFIFOLOAD(p, SKIP, pdb->ip_hdr_len, 0);\n+\tSEQFIFOLOAD(p, MSG1, 0, VLF | FLUSH1 | LAST1);\n+\tSEQFIFOSTORE(p, SKIP, 0, 0, VLF);\n+\tSEQSTORE(p, CONTEXT1, 0, IPSEC_ICV_MD5_TRUNC_SIZE, 0);\n+/*\n+ * TODO: RTA currently doesn't support adding labels in or after Job Descriptor.\n+ * To be changed when proper support is added in RTA.\n+ */\n+\t/* Label the Shared Descriptor Pointer */\n+\tSET_LABEL(p, shd_ptr);\n+\tshd_ptr += 1;\n+\t/* Label the Output Pointer */\n+\tSET_LABEL(p, outptr);\n+\toutptr += 3;\n+\t/* Label the first word after JD */\n+\tSET_LABEL(p, swapped_seqin_fields);\n+\tswapped_seqin_fields += 8;\n+\t/* Label the second word after JD */\n+\tSET_LABEL(p, swapped_seqin_ptr);\n+\tswapped_seqin_ptr += 9;\n+\n+\tPATCH_HDR(p, phdr, hdr);\n+\tPATCH_JUMP(p, pkeyjump, keyjump);\n+\tPATCH_JUMP(p, swapped_seqin_ptr_jump, swapped_seqin_ptr);\n+\tPATCH_MOVE(p, move_outlen, outptr);\n+\tPATCH_MOVE(p, move_seqout_ptr, shd_ptr);\n+\tPATCH_MOVE(p, write_swapped_seqin_ptr, swapped_seqin_fields);\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * cnstr_shdsc_ipsec_decap_des_aes_xcbc - IPSec DES-CBC/3DES-CBC and\n+ *     AES-XCBC-MAC-96 ESP decapsulation shared descriptor.\n+ * @descbuf: pointer to buffer used for descriptor construction\n+ * @pdb: pointer to the PDB to be used with this descriptor\n+ *       This structure will be copied inline to the descriptor under\n+ *       construction. No error checking will be made. Refer to the\n+ *       block guide for a details of the encapsulation PDB.\n+ * @cipherdata: pointer to block cipher transform definitions\n+ *              Valid algorithm values - OP_PCL_IPSEC_DES, OP_PCL_IPSEC_3DES.\n+ * @authdata: pointer to authentication transform definitions\n+ *            Valid algorithm value: OP_PCL_IPSEC_AES_XCBC_MAC_96.\n+ *\n+ * Supported only for platforms with 32-bit address pointers and SEC ERA 4 or\n+ * higher. The tunnel/transport mode of the IPsec ESP is supported only if the\n+ * Outer/Transport IP Header is present in the decapsulation input packet.\n+ * The descriptor computes the AES-XCBC-MAC-96 to check if the received ICV\n+ * is correct, rereads the input packet to compute the MD5 ICV, overwrites\n+ * the XCBC ICV, and then sends the modified input packet to the\n+ * DES-CBC/3DES-CBC & HMAC-MD5-96 IPsec.\n+ * The descriptor uses all the benefits of the built-in protocol by computing\n+ * the IPsec ESP with a hardware supported algorithms combination\n+ * (DES-CBC/3DES-CBC & HMAC-MD5-96). The HMAC-MD5 authentication algorithm\n+ * was chosen in order to speed up the computational time for this intermediate\n+ * step.\n+ * Warning: The user must allocate at least 32 bytes for the authentication key\n+ * (in order to use it also with HMAC-MD5-96),even when using a shorter key\n+ * for the AES-XCBC-MAC-96.\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_ipsec_decap_des_aes_xcbc(uint32_t *descbuf,\n+\t\tstruct ipsec_decap_pdb *pdb, struct alginfo *cipherdata,\n+\t\tstruct alginfo *authdata)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\tuint32_t ip_hdr_len = (pdb->options & PDBHDRLEN_MASK) >>\n+\t\t\t\tPDBHDRLEN_ESP_DECAP_SHIFT;\n+\n+\tLABEL(hdr);\n+\tLABEL(jump_cmd);\n+\tLABEL(keyjump);\n+\tLABEL(outlen);\n+\tLABEL(seqin_ptr);\n+\tLABEL(seqout_ptr);\n+\tLABEL(swapped_seqout_fields);\n+\tLABEL(swapped_seqout_ptr);\n+\tREFERENCE(seqout_ptr_jump);\n+\tREFERENCE(phdr);\n+\tREFERENCE(pkeyjump);\n+\tREFERENCE(move_jump);\n+\tREFERENCE(move_jump_back);\n+\tREFERENCE(move_seqin_ptr);\n+\tREFERENCE(swapped_seqout_ptr_jump);\n+\tREFERENCE(write_swapped_seqout_ptr);\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tphdr = SHR_HDR(p, SHR_SERIAL, hdr, 0);\n+\t__rta_copy_ipsec_decap_pdb(p, pdb, cipherdata->algtype);\n+\tSET_LABEL(p, hdr);\n+\tpkeyjump = JUMP(p, keyjump, LOCAL_JUMP, ALL_TRUE, SHRD | SELF);\n+\t/*\n+\t * Hard-coded KEY arguments. The descriptor uses all the benefits of\n+\t * the built-in protocol by computing the IPsec ESP with a hardware\n+\t * supported algorithms combination (DES-CBC/3DES-CBC & HMAC-MD5-96).\n+\t * The HMAC-MD5 authentication algorithm was chosen with\n+\t * the keys options from bellow in order to speed up the computational\n+\t * time for this intermediate step.\n+\t * Warning: The user must allocate at least 32 bytes for\n+\t * the authentication key (in order to use it also with HMAC-MD5-96),\n+\t * even when using a shorter key for the AES-XCBC-MAC-96.\n+\t */\n+\tKEY(p, MDHA_SPLIT_KEY, 0, authdata->key, 32, INLINE_KEY(authdata));\n+\tSET_LABEL(p, keyjump);\n+\tLOAD(p, LDST_SRCDST_WORD_CLRW | CLRW_CLR_C1MODE | CLRW_CLR_C1DATAS |\n+\t     CLRW_CLR_C1CTX | CLRW_CLR_C1KEY | CLRW_RESET_CLS1_CHA, CLRW, 0, 4,\n+\t     0);\n+\tKEY(p, KEY1, authdata->key_enc_flags, authdata->key, authdata->keylen,\n+\t    INLINE_KEY(authdata));\n+\tMATHB(p, SEQINSZ, SUB,\n+\t      (uint64_t)(ip_hdr_len + IPSEC_ICV_MD5_TRUNC_SIZE), MATH0, 4,\n+\t      IMMED2);\n+\tMATHB(p, MATH0, SUB, ZERO, VSEQINSZ, 4, 0);\n+\tALG_OPERATION(p, OP_ALG_ALGSEL_MD5, OP_ALG_AAI_HMAC_PRECOMP,\n+\t\t      OP_ALG_AS_INITFINAL, ICV_CHECK_DISABLE, DIR_ENC);\n+\tALG_OPERATION(p, OP_ALG_ALGSEL_AES, OP_ALG_AAI_XCBC_MAC,\n+\t\t      OP_ALG_AS_INITFINAL, ICV_CHECK_ENABLE, DIR_DEC);\n+\tSEQFIFOLOAD(p, SKIP, ip_hdr_len, 0);\n+\tSEQFIFOLOAD(p, MSG1, 0, VLF | FLUSH1);\n+\tSEQFIFOLOAD(p, ICV1, IPSEC_ICV_MD5_TRUNC_SIZE, FLUSH1 | LAST1);\n+\t/* Swap SEQOUTPTR to SEQINPTR. */\n+\tmove_seqin_ptr = MOVE(p, DESCBUF, 0, MATH1, 0, 16, WAITCOMP | IMMED);\n+\tMATHB(p, MATH1, OR, CMD_SEQ_IN_PTR ^ CMD_SEQ_OUT_PTR, MATH1, 8,\n+\t      IFB | IMMED2);\n+/*\n+ * TODO: RTA currently doesn't support creating a LOAD command\n+ * with another command as IMM.\n+ * To be changed when proper support is added in RTA.\n+ */\n+\tLOAD(p, 0xA00000e1, MATH3, 4, 4, IMMED);\n+\tMATHB(p, MATH3, SHLD, MATH3, MATH3,  8, 0);\n+\twrite_swapped_seqout_ptr = MOVE(p, MATH1, 0, DESCBUF, 0, 20, WAITCOMP |\n+\t\t\t\t\tIMMED);\n+\tswapped_seqout_ptr_jump = JUMP(p, swapped_seqout_ptr, LOCAL_JUMP,\n+\t\t\t\t       ALL_TRUE, 0);\n+/*\n+ * TODO: To be changed when proper support is added in RTA (can't load\n+ * a command that is also written by RTA).\n+ * Change when proper RTA support is added.\n+ */\n+\tSET_LABEL(p, jump_cmd);\n+\tWORD(p, 0xA00000f3);\n+\tSEQINPTR(p, 0, 65535, RTO);\n+\tMATHB(p, MATH0, SUB, ZERO, VSEQINSZ, 4, 0);\n+\tMATHB(p, MATH0, ADD, ip_hdr_len, VSEQOUTSZ, 4, IMMED2);\n+\tmove_jump = MOVE(p, DESCBUF, 0, OFIFO, 0, 8, WAITCOMP | IMMED);\n+\tmove_jump_back = MOVE(p, OFIFO, 0, DESCBUF, 0, 8, IMMED);\n+\tSEQFIFOLOAD(p, SKIP, ip_hdr_len, 0);\n+\tSEQFIFOLOAD(p, MSG2, 0, VLF | LAST2);\n+\tSEQFIFOSTORE(p, SKIP, 0, 0, VLF);\n+\tSEQSTORE(p, CONTEXT2, 0, IPSEC_ICV_MD5_TRUNC_SIZE, 0);\n+\tseqout_ptr_jump = JUMP(p, seqout_ptr, LOCAL_JUMP, ALL_TRUE, CALM);\n+\n+\tLOAD(p, LDST_SRCDST_WORD_CLRW | CLRW_CLR_C1MODE | CLRW_CLR_C1DATAS |\n+\t     CLRW_CLR_C1CTX | CLRW_CLR_C1KEY | CLRW_CLR_C2MODE |\n+\t     CLRW_CLR_C2DATAS | CLRW_CLR_C2CTX | CLRW_RESET_CLS1_CHA, CLRW, 0,\n+\t     4, 0);\n+\tSEQINPTR(p, 0, 65535, RTO);\n+\tMATHB(p, MATH0, ADD,\n+\t      (uint64_t)(ip_hdr_len + IPSEC_ICV_MD5_TRUNC_SIZE), SEQINSZ, 4,\n+\t      IMMED2);\n+\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\tPROTOCOL(p, OP_TYPE_DECAP_PROTOCOL, OP_PCLID_IPSEC,\n+\t\t (uint16_t)(cipherdata->algtype | OP_PCL_IPSEC_HMAC_MD5_96));\n+/*\n+ * TODO: RTA currently doesn't support adding labels in or after Job Descriptor.\n+ * To be changed when proper support is added in RTA.\n+ */\n+\t/* Label the SEQ OUT PTR */\n+\tSET_LABEL(p, seqout_ptr);\n+\tseqout_ptr += 2;\n+\t/* Label the Output Length */\n+\tSET_LABEL(p, outlen);\n+\toutlen += 4;\n+\t/* Label the SEQ IN PTR */\n+\tSET_LABEL(p, seqin_ptr);\n+\tseqin_ptr += 5;\n+\t/* Label the first word after JD */\n+\tSET_LABEL(p, swapped_seqout_fields);\n+\tswapped_seqout_fields += 8;\n+\t/* Label the second word after JD */\n+\tSET_LABEL(p, swapped_seqout_ptr);\n+\tswapped_seqout_ptr += 9;\n+\n+\tPATCH_HDR(p, phdr, hdr);\n+\tPATCH_JUMP(p, pkeyjump, keyjump);\n+\tPATCH_JUMP(p, seqout_ptr_jump, seqout_ptr);\n+\tPATCH_JUMP(p, swapped_seqout_ptr_jump, swapped_seqout_ptr);\n+\tPATCH_MOVE(p, move_jump, jump_cmd);\n+\tPATCH_MOVE(p, move_jump_back, seqin_ptr);\n+\tPATCH_MOVE(p, move_seqin_ptr, outlen);\n+\tPATCH_MOVE(p, write_swapped_seqout_ptr, swapped_seqout_fields);\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * IPSEC_NEW_ENC_BASE_DESC_LEN - IPsec new mode encap shared descriptor length\n+ *\n+ * Accounts only for the \"base\" commands and is intended to be used by upper\n+ * layers to determine whether Outer IP Header and/or keys can be inlined or\n+ * not. To be used as first parameter of rta_inline_query().\n+ */\n+#define IPSEC_NEW_ENC_BASE_DESC_LEN\t(5 * CAAM_CMD_SZ + \\\n+\t\t\t\t\t sizeof(struct ipsec_encap_pdb))\n+\n+/**\n+ * IPSEC_NEW_NULL_ENC_BASE_DESC_LEN - IPsec new mode encap shared descriptor\n+ *                                    length for the case of\n+ *                                    NULL encryption / authentication\n+ *\n+ * Accounts only for the \"base\" commands and is intended to be used by upper\n+ * layers to determine whether Outer IP Header and/or key can be inlined or\n+ * not. To be used as first parameter of rta_inline_query().\n+ */\n+#define IPSEC_NEW_NULL_ENC_BASE_DESC_LEN\t(4 * CAAM_CMD_SZ + \\\n+\t\t\t\t\t\t sizeof(struct ipsec_encap_pdb))\n+\n+/**\n+ * cnstr_shdsc_ipsec_new_encap -  IPSec new mode ESP encapsulation\n+ *     protocol-level shared descriptor.\n+ * @descbuf: pointer to buffer used for descriptor construction\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: must be true when core endianness doesn't match SEC endianness\n+ * @pdb: pointer to the PDB to be used with this descriptor\n+ *       This structure will be copied inline to the descriptor under\n+ *       construction. No error checking will be made. Refer to the\n+ *       block guide for details about the encapsulation PDB.\n+ * @opt_ip_hdr:  pointer to Optional IP Header\n+ *     -if OIHI = PDBOPTS_ESP_OIHI_PDB_INL, opt_ip_hdr points to the buffer to\n+ *     be inlined in the PDB. Number of bytes (buffer size) copied is provided\n+ *     in pdb->ip_hdr_len.\n+ *     -if OIHI = PDBOPTS_ESP_OIHI_PDB_REF, opt_ip_hdr points to the address of\n+ *     the Optional IP Header. The address will be inlined in the PDB verbatim.\n+ *     -for other values of OIHI options field, opt_ip_hdr is not used.\n+ * @cipherdata: pointer to block cipher transform definitions\n+ *              Valid algorithm values - one of OP_PCL_IPSEC_*\n+ * @authdata: pointer to authentication transform definitions.\n+ *            If an authentication key is required by the protocol, a \"normal\"\n+ *            key must be provided; DKP (Derived Key Protocol) will be used to\n+ *            compute MDHA on the fly in HW.\n+ *            Valid algorithm values - one of OP_PCL_IPSEC_*\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_ipsec_new_encap(uint32_t *descbuf, bool ps,\n+\t\t\t\t\t      bool swap,\n+\t\t\t\t\t      struct ipsec_encap_pdb *pdb,\n+\t\t\t\t\t      uint8_t *opt_ip_hdr,\n+\t\t\t\t\t      struct alginfo *cipherdata,\n+\t\t\t\t\t      struct alginfo *authdata)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\n+\tLABEL(keyjmp);\n+\tREFERENCE(pkeyjmp);\n+\tLABEL(hdr);\n+\tREFERENCE(phdr);\n+\n+\tif (rta_sec_era < RTA_SEC_ERA_8) {\n+\t\tpr_err(\"IPsec new mode encap: available only for Era %d or above\\n\",\n+\t\t       USER_SEC_ERA(RTA_SEC_ERA_8));\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap)\n+\t\tPROGRAM_SET_BSWAP(p);\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tphdr = SHR_HDR(p, SHR_SERIAL, hdr, 0);\n+\n+\t__rta_copy_ipsec_encap_pdb(p, pdb, cipherdata->algtype);\n+\n+\tswitch (pdb->options & PDBOPTS_ESP_OIHI_MASK) {\n+\tcase PDBOPTS_ESP_OIHI_PDB_INL:\n+\t\tCOPY_DATA(p, opt_ip_hdr, pdb->ip_hdr_len);\n+\t\tbreak;\n+\tcase PDBOPTS_ESP_OIHI_PDB_REF:\n+\t\tif (ps)\n+\t\t\tCOPY_DATA(p, opt_ip_hdr, 8);\n+\t\telse\n+\t\t\tCOPY_DATA(p, opt_ip_hdr, 4);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\tSET_LABEL(p, hdr);\n+\n+\tpkeyjmp = JUMP(p, keyjmp, LOCAL_JUMP, ALL_TRUE, SHRD);\n+\tif (authdata->keylen)\n+\t\t__gen_auth_key(p, authdata);\n+\tif (cipherdata->keylen)\n+\t\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\tSET_LABEL(p, keyjmp);\n+\tPROTOCOL(p, OP_TYPE_ENCAP_PROTOCOL,\n+\t\t OP_PCLID_IPSEC_NEW,\n+\t\t (uint16_t)(cipherdata->algtype | authdata->algtype));\n+\tPATCH_JUMP(p, pkeyjmp, keyjmp);\n+\tPATCH_HDR(p, phdr, hdr);\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * IPSEC_NEW_DEC_BASE_DESC_LEN - IPsec new mode decap shared descriptor length\n+ *\n+ * Accounts only for the \"base\" commands and is intended to be used by upper\n+ * layers to determine whether keys can be inlined or not. To be used as first\n+ * parameter of rta_inline_query().\n+ */\n+#define IPSEC_NEW_DEC_BASE_DESC_LEN\t(5 * CAAM_CMD_SZ + \\\n+\t\t\t\t\t sizeof(struct ipsec_decap_pdb))\n+\n+/**\n+ * IPSEC_NEW_NULL_DEC_BASE_DESC_LEN - IPsec new mode decap shared descriptor\n+ *                                    length for the case of\n+ *                                    NULL decryption / authentication\n+ *\n+ * Accounts only for the \"base\" commands and is intended to be used by upper\n+ * layers to determine whether key can be inlined or not. To be used as first\n+ * parameter of rta_inline_query().\n+ */\n+#define IPSEC_NEW_NULL_DEC_BASE_DESC_LEN\t(4 * CAAM_CMD_SZ + \\\n+\t\t\t\t\t\t sizeof(struct ipsec_decap_pdb))\n+\n+/**\n+ * cnstr_shdsc_ipsec_new_decap - IPSec new mode ESP decapsulation protocol-level\n+ *     shared descriptor.\n+ * @descbuf: pointer to buffer used for descriptor construction\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: must be true when core endianness doesn't match SEC endianness\n+ * @pdb: pointer to the PDB to be used with this descriptor\n+ *       This structure will be copied inline to the descriptor under\n+ *       construction. No error checking will be made. Refer to the\n+ *       block guide for details about the decapsulation PDB.\n+ * @cipherdata: pointer to block cipher transform definitions\n+ *              Valid algorithm values 0 one of OP_PCL_IPSEC_*\n+ * @authdata: pointer to authentication transform definitions.\n+ *            If an authentication key is required by the protocol, a \"normal\"\n+ *            key must be provided; DKP (Derived Key Protocol) will be used to\n+ *            compute MDHA on the fly in HW.\n+ *            Valid algorithm values - one of OP_PCL_IPSEC_*\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_ipsec_new_decap(uint32_t *descbuf, bool ps,\n+\t\t\t\t\t      bool swap,\n+\t\t\t\t\t      struct ipsec_decap_pdb *pdb,\n+\t\t\t\t\t      struct alginfo *cipherdata,\n+\t\t\t\t\t      struct alginfo *authdata)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\n+\tLABEL(keyjmp);\n+\tREFERENCE(pkeyjmp);\n+\tLABEL(hdr);\n+\tREFERENCE(phdr);\n+\n+\tif (rta_sec_era < RTA_SEC_ERA_8) {\n+\t\tpr_err(\"IPsec new mode decap: available only for Era %d or above\\n\",\n+\t\t       USER_SEC_ERA(RTA_SEC_ERA_8));\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\tif (swap)\n+\t\tPROGRAM_SET_BSWAP(p);\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\tphdr = SHR_HDR(p, SHR_SERIAL, hdr, 0);\n+\t__rta_copy_ipsec_decap_pdb(p, pdb, cipherdata->algtype);\n+\tSET_LABEL(p, hdr);\n+\tpkeyjmp = JUMP(p, keyjmp, LOCAL_JUMP, ALL_TRUE, SHRD);\n+\tif (authdata->keylen)\n+\t\t__gen_auth_key(p, authdata);\n+\tif (cipherdata->keylen)\n+\t\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\tSET_LABEL(p, keyjmp);\n+\tPROTOCOL(p, OP_TYPE_DECAP_PROTOCOL,\n+\t\t OP_PCLID_IPSEC_NEW,\n+\t\t (uint16_t)(cipherdata->algtype | authdata->algtype));\n+\tPATCH_JUMP(p, pkeyjmp, keyjmp);\n+\tPATCH_HDR(p, phdr, hdr);\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+/**\n+ * IPSEC_AUTH_VAR_BASE_DESC_LEN - IPsec encap/decap shared descriptor length\n+ *\t\t\t\tfor the case of variable-length authentication\n+ *\t\t\t\tonly data.\n+ *\t\t\t\tNote: Only for SoCs with SEC_ERA >= 3.\n+ *\n+ * Accounts only for the \"base\" commands and is intended to be used by upper\n+ * layers to determine whether keys can be inlined or not. To be used as first\n+ * parameter of rta_inline_query().\n+ */\n+#define IPSEC_AUTH_VAR_BASE_DESC_LEN\t(27 * CAAM_CMD_SZ)\n+\n+/**\n+ * IPSEC_AUTH_VAR_AES_DEC_BASE_DESC_LEN - IPsec AES decap shared descriptor\n+ *                              length for variable-length authentication only\n+ *                              data.\n+ *                              Note: Only for SoCs with SEC_ERA >= 3.\n+ *\n+ * Accounts only for the \"base\" commands and is intended to be used by upper\n+ * layers to determine whether key can be inlined or not. To be used as first\n+ * parameter of rta_inline_query().\n+ */\n+#define IPSEC_AUTH_VAR_AES_DEC_BASE_DESC_LEN\t\\\n+\t\t\t\t(IPSEC_AUTH_VAR_BASE_DESC_LEN + CAAM_CMD_SZ)\n+\n+/**\n+ * IPSEC_AUTH_BASE_DESC_LEN - IPsec encap/decap shared descriptor length\n+ *\n+ * Accounts only for the \"base\" commands and is intended to be used by upper\n+ * layers to determine whether key can be inlined or not. To be used as first\n+ * parameter of rta_inline_query().\n+ */\n+#define IPSEC_AUTH_BASE_DESC_LEN\t(19 * CAAM_CMD_SZ)\n+\n+/**\n+ * IPSEC_AUTH_AES_DEC_BASE_DESC_LEN - IPsec AES decap shared descriptor length\n+ *\n+ * Accounts only for the \"base\" commands and is intended to be used by upper\n+ * layers to determine whether key can be inlined or not. To be used as first\n+ * parameter of rta_inline_query().\n+ */\n+#define IPSEC_AUTH_AES_DEC_BASE_DESC_LEN\t(IPSEC_AUTH_BASE_DESC_LEN + \\\n+\t\t\t\t\t\tCAAM_CMD_SZ)\n+\n+/**\n+ * cnstr_shdsc_authenc - authenc-like descriptor\n+ * @descbuf: pointer to buffer used for descriptor construction\n+ * @ps: if 36/40bit addressing is desired, this parameter must be true\n+ * @swap: if true, perform descriptor byte swapping on a 4-byte boundary\n+ * @cipherdata: ointer to block cipher transform definitions.\n+ *              Valid algorithm values one of OP_ALG_ALGSEL_* {DES, 3DES, AES}\n+ * @authdata: pointer to authentication transform definitions.\n+ *            Valid algorithm values - one of OP_ALG_ALGSEL_* {MD5, SHA1,\n+ *            SHA224, SHA256, SHA384, SHA512}\n+ * Note: The key for authentication is supposed to be given as plain text.\n+ * Note: There's no support for keys longer than the corresponding digest size,\n+ *       according to the selected algorithm.\n+ *\n+ * @ivlen: length of the IV to be read from the input frame, before any data\n+ *         to be processed\n+ * @auth_only_len: length of the data to be authenticated-only (commonly IP\n+ *                 header, IV, Sequence number and SPI)\n+ * Note: Extended Sequence Number processing is NOT supported\n+ *\n+ * @trunc_len: the length of the ICV to be written to the output frame. If 0,\n+ *             then the corresponding length of the digest, according to the\n+ *             selected algorithm shall be used.\n+ * @dir: Protocol direction, encapsulation or decapsulation (DIR_ENC/DIR_DEC)\n+ *\n+ * Note: Here's how the input frame needs to be formatted so that the processing\n+ *       will be done correctly:\n+ * For encapsulation:\n+ *     Input:\n+ * +----+----------------+---------------------------------------------+\n+ * | IV | Auth-only data | Padded data to be authenticated & Encrypted |\n+ * +----+----------------+---------------------------------------------+\n+ *     Output:\n+ * +--------------------------------------+\n+ * | Authenticated & Encrypted data | ICV |\n+ * +--------------------------------+-----+\n+\n+ * For decapsulation:\n+ *     Input:\n+ * +----+----------------+--------------------------------+-----+\n+ * | IV | Auth-only data | Authenticated & Encrypted data | ICV |\n+ * +----+----------------+--------------------------------+-----+\n+ *     Output:\n+ * +----+--------------------------+\n+ * | Decrypted & authenticated data |\n+ * +----+--------------------------+\n+ *\n+ * Note: This descriptor can use per-packet commands, encoded as below in the\n+ *       DPOVRD register:\n+ * 32    24    16               0\n+ * +------+---------------------+\n+ * | 0x80 | 0x00| auth_only_len |\n+ * +------+---------------------+\n+ *\n+ * This mechanism is available only for SoCs having SEC ERA >= 3. In other\n+ * words, this will not work for P4080TO2\n+ *\n+ * Note: The descriptor does not add any kind of padding to the input data,\n+ *       so the upper layer needs to ensure that the data is padded properly,\n+ *       according to the selected cipher. Failure to do so will result in\n+ *       the descriptor failing with a data-size error.\n+ *\n+ * Return: size of descriptor written in words or negative number on error\n+ */\n+static inline int cnstr_shdsc_authenc(uint32_t *descbuf, bool ps, bool swap,\n+\t\t\t\t      struct alginfo *cipherdata,\n+\t\t\t\t      struct alginfo *authdata,\n+\t\t\t\t      uint16_t ivlen, uint16_t auth_only_len,\n+\t\t\t\t      uint8_t trunc_len, uint8_t dir)\n+{\n+\tstruct program prg;\n+\tstruct program *p = &prg;\n+\tconst bool is_aes_dec = (dir == DIR_DEC) &&\n+\t\t\t\t(cipherdata->algtype == OP_ALG_ALGSEL_AES);\n+\n+\tLABEL(skip_patch_len);\n+\tLABEL(keyjmp);\n+\tLABEL(skipkeys);\n+\tLABEL(aonly_len_offset);\n+\tREFERENCE(pskip_patch_len);\n+\tREFERENCE(pkeyjmp);\n+\tREFERENCE(pskipkeys);\n+\tREFERENCE(read_len);\n+\tREFERENCE(write_len);\n+\n+\tPROGRAM_CNTXT_INIT(p, descbuf, 0);\n+\n+\tif (swap)\n+\t\tPROGRAM_SET_BSWAP(p);\n+\tif (ps)\n+\t\tPROGRAM_SET_36BIT_ADDR(p);\n+\n+\t/*\n+\t * Since we currently assume that key length is equal to hash digest\n+\t * size, it's ok to truncate keylen value.\n+\t */\n+\ttrunc_len = trunc_len && (trunc_len < authdata->keylen) ?\n+\t\t\ttrunc_len : (uint8_t)authdata->keylen;\n+\n+\tSHR_HDR(p, SHR_SERIAL, 1, SC);\n+\n+\t/*\n+\t * M0 will contain the value provided by the user when creating\n+\t * the shared descriptor. If the user provided an override in\n+\t * DPOVRD, then M0 will contain that value\n+\t */\n+\tMATHB(p, MATH0, ADD, auth_only_len, MATH0, 4, IMMED2);\n+\n+\tif (rta_sec_era >= RTA_SEC_ERA_3) {\n+\t\t/*\n+\t\t * Check if the user wants to override the auth-only len\n+\t\t */\n+\t\tMATHB(p, DPOVRD, ADD, 0x80000000, MATH2, 4, IMMED2);\n+\n+\t\t/*\n+\t\t * No need to patch the length of the auth-only data read if\n+\t\t * the user did not override it\n+\t\t */\n+\t\tpskip_patch_len = JUMP(p, skip_patch_len, LOCAL_JUMP, ALL_TRUE,\n+\t\t\t\t  MATH_N);\n+\n+\t\t/* Get auth-only len in M0 */\n+\t\tMATHB(p, MATH2, AND, 0xFFFF, MATH0, 4, IMMED2);\n+\n+\t\t/*\n+\t\t * Since M0 is used in calculations, don't mangle it, copy\n+\t\t * its content to M1 and use this for patching.\n+\t\t */\n+\t\tMATHB(p, MATH0, ADD, MATH1, MATH1, 4, 0);\n+\n+\t\tread_len = MOVE(p, DESCBUF, 0, MATH1, 0, 6, WAITCOMP | IMMED);\n+\t\twrite_len = MOVE(p, MATH1, 0, DESCBUF, 0, 8, WAITCOMP | IMMED);\n+\n+\t\tSET_LABEL(p, skip_patch_len);\n+\t}\n+\t/*\n+\t * MATH0 contains the value in DPOVRD w/o the MSB, or the initial\n+\t * value, as provided by the user at descriptor creation time\n+\t */\n+\tif (dir == DIR_ENC)\n+\t\tMATHB(p, MATH0, ADD, ivlen, MATH0, 4, IMMED2);\n+\telse\n+\t\tMATHB(p, MATH0, ADD, ivlen + trunc_len, MATH0, 4, IMMED2);\n+\n+\tpkeyjmp = JUMP(p, keyjmp, LOCAL_JUMP, ALL_TRUE, SHRD);\n+\n+\tKEY(p, KEY2, authdata->key_enc_flags, authdata->key, authdata->keylen,\n+\t    INLINE_KEY(authdata));\n+\n+\t/* Insert Key */\n+\tKEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key,\n+\t    cipherdata->keylen, INLINE_KEY(cipherdata));\n+\n+\t/* Do operation */\n+\tALG_OPERATION(p, authdata->algtype, OP_ALG_AAI_HMAC,\n+\t\t      OP_ALG_AS_INITFINAL,\n+\t\t      dir == DIR_ENC ? ICV_CHECK_DISABLE : ICV_CHECK_ENABLE,\n+\t\t      dir);\n+\n+\tif (is_aes_dec)\n+\t\tALG_OPERATION(p, OP_ALG_ALGSEL_AES, cipherdata->algmode,\n+\t\t\t      OP_ALG_AS_INITFINAL, ICV_CHECK_DISABLE, dir);\n+\tpskipkeys = JUMP(p, skipkeys, LOCAL_JUMP, ALL_TRUE, 0);\n+\n+\tSET_LABEL(p, keyjmp);\n+\n+\tALG_OPERATION(p, authdata->algtype, OP_ALG_AAI_HMAC_PRECOMP,\n+\t\t      OP_ALG_AS_INITFINAL,\n+\t\t      dir == DIR_ENC ? ICV_CHECK_DISABLE : ICV_CHECK_ENABLE,\n+\t\t      dir);\n+\n+\tif (is_aes_dec) {\n+\t\tALG_OPERATION(p, OP_ALG_ALGSEL_AES, cipherdata->algmode |\n+\t\t\t      OP_ALG_AAI_DK, OP_ALG_AS_INITFINAL,\n+\t\t\t      ICV_CHECK_DISABLE, dir);\n+\t\tSET_LABEL(p, skipkeys);\n+\t} else {\n+\t\tSET_LABEL(p, skipkeys);\n+\t\tALG_OPERATION(p, cipherdata->algtype, cipherdata->algmode,\n+\t\t\t      OP_ALG_AS_INITFINAL, ICV_CHECK_DISABLE, dir);\n+\t}\n+\n+\t/*\n+\t * Prepare the length of the data to be both encrypted/decrypted\n+\t * and authenticated/checked\n+\t */\n+\tMATHB(p, SEQINSZ, SUB, MATH0, VSEQINSZ, 4, 0);\n+\n+\tMATHB(p, VSEQINSZ, SUB, MATH3, VSEQOUTSZ, 4, 0);\n+\n+\t/* Prepare for writing the output frame */\n+\tSEQFIFOSTORE(p, MSG, 0, 0, VLF);\n+\n+\tSET_LABEL(p, aonly_len_offset);\n+\n+\t/* Read IV */\n+\tSEQLOAD(p, CONTEXT1, 0, ivlen, 0);\n+\n+\t/*\n+\t * Read data needed only for authentication. This is overwritten above\n+\t * if the user requested it.\n+\t */\n+\tSEQFIFOLOAD(p, MSG2, auth_only_len, 0);\n+\n+\tif (dir == DIR_ENC) {\n+\t\t/*\n+\t\t * Read input plaintext, encrypt and authenticate & write to\n+\t\t * output\n+\t\t */\n+\t\tSEQFIFOLOAD(p, MSGOUTSNOOP, 0, VLF | LAST1 | LAST2 | FLUSH1);\n+\n+\t\t/* Finally, write the ICV */\n+\t\tSEQSTORE(p, CONTEXT2, 0, trunc_len, 0);\n+\t} else {\n+\t\t/*\n+\t\t * Read input ciphertext, decrypt and authenticate & write to\n+\t\t * output\n+\t\t */\n+\t\tSEQFIFOLOAD(p, MSGINSNOOP, 0, VLF | LAST1 | LAST2 | FLUSH1);\n+\n+\t\t/* Read the ICV to check */\n+\t\tSEQFIFOLOAD(p, ICV2, trunc_len, LAST2);\n+\t}\n+\n+\tPATCH_JUMP(p, pkeyjmp, keyjmp);\n+\tPATCH_JUMP(p, pskipkeys, skipkeys);\n+\tPATCH_JUMP(p, pskipkeys, skipkeys);\n+\n+\tif (rta_sec_era >= RTA_SEC_ERA_3) {\n+\t\tPATCH_JUMP(p, pskip_patch_len, skip_patch_len);\n+\t\tPATCH_MOVE(p, read_len, aonly_len_offset);\n+\t\tPATCH_MOVE(p, write_len, aonly_len_offset);\n+\t}\n+\n+\treturn PROGRAM_FINALIZE(p);\n+}\n+\n+#endif /* __DESC_IPSEC_H__ */\n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "03/11"
    ]
}