Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/18179/?format=api
{ "id": 18179, "url": "http://patches.dpdk.org/api/patches/18179/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1482180853-18823-20-git-send-email-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1482180853-18823-20-git-send-email-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1482180853-18823-20-git-send-email-hemant.agrawal@nxp.com", "date": "2016-12-19T20:53:58", "name": "[dpdk-dev,PATCHv2,19/34] net/dpaa2: add queue configuration support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1aa50cab1e391d3dec5ef87225ea7306b5442a97", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1482180853-18823-20-git-send-email-hemant.agrawal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/18179/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/18179/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id A4553FAE7;\n\tMon, 19 Dec 2016 16:22:03 +0100 (CET)", "from NAM02-CY1-obe.outbound.protection.outlook.com\n\t(mail-cys01nam02on0077.outbound.protection.outlook.com\n\t[104.47.37.77]) by dpdk.org (Postfix) with ESMTP id 94244FA4F\n\tfor <dev@dpdk.org>; Mon, 19 Dec 2016 16:21:39 +0100 (CET)", "from BN3PR0301CA0017.namprd03.prod.outlook.com (10.160.180.155) by\n\tDM2PR0301MB0751.namprd03.prod.outlook.com (10.160.97.147) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.771.8; Mon, 19 Dec 2016 15:21:38 +0000", "from BN1AFFO11FD048.protection.gbl (2a01:111:f400:7c10::188) by\n\tBN3PR0301CA0017.outlook.office365.com (2a01:111:e400:4000::27) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.789.14 via\n\tFrontend Transport; Mon, 19 Dec 2016 15:21:38 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBN1AFFO11FD048.mail.protection.outlook.com (10.58.53.63) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.789.10\n\tvia Frontend Transport; Mon, 19 Dec 2016 15:21:37 +0000", "from bf-netperf1.idc ([10.232.134.28])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tuBJFKMhi029110; Mon, 19 Dec 2016 08:21:34 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com;\n\tnxp.com; \n\tdkim=none (message not signed) header.d=none;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,\n\t<shreyansh.jain@nxp.com>, <john.mcnamara@intel.com>,\n\t<ferruh.yigit@intel.com>, <jerin.jacob@caviumnetworks.com>,\n\tHemant Agrawal <hemant.agrawal@nxp.com>", "Date": "Tue, 20 Dec 2016 02:23:58 +0530", "Message-ID": "<1482180853-18823-20-git-send-email-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1482180853-18823-1-git-send-email-hemant.agrawal@nxp.com>", "References": "<1480875447-23680-1-git-send-email-hemant.agrawal@nxp.com>\n\t<1482180853-18823-1-git-send-email-hemant.agrawal@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131266344981503799;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(336005)(7916002)(39400400002)(39850400002)(39840400002)(39410400002)(39860400002)(39380400002)(39450400003)(2980300002)(1110001)(1109001)(339900001)(189002)(199003)(77096006)(575784001)(86362001)(92566002)(38730400001)(110136003)(47776003)(50226002)(8936002)(68736007)(81156014)(81166006)(8676002)(5660300001)(85426001)(189998001)(6916009)(2950100002)(6666003)(97736004)(5003940100001)(48376002)(76176999)(50986999)(33646002)(36756003)(626004)(50466002)(69596002)(305945005)(8666005)(356003)(104016004)(106466001)(105606002)(2906002)(2351001)(4326007)(7059030);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:DM2PR0301MB0751;\n\tH:az84smr01.freescale.net; \n\tFPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; ", "X-Microsoft-Exchange-Diagnostics": [ "1; BN1AFFO11FD048;\n\t1:bPcci2NsNTqDNLdS3o8qGDI5PipC7eVkY5vtKusF4sV2RpPkCx9JzQg0/l+XtXx1yg82dDUVcOlnPX9u46YM6spjHzvlcSX4EMs1Ixoc4RDHSiwwfDzp/6yWqINGXtGxzkFd4oaPE6h/O+meELU2sTEwgY6dv0iQ9s4OvBueSzUgGpsswj27gq1HxWWkmAHaKVC8WSFExXOcS4diFovhmz5XxOJrBPIkbWgiNUmRT4uP3rTNf+rKkVG+oHX5vkwVsJwlY+luqq/2vcd9cqdH+g3rtIX0wurXYheKWcjbyM0q4XVK2Hxf0hBIix+/JEHpRV6L28xdIMAlmsuN97IV0uMgIjzMIQqWqce+y7nOEbANsmKkoiPZZLldRNcQKOyLNhoz7H09Sz595Wzvk7/Dmvv7GTKSI6RnXJlxQ40PvdCknKrLD0NMSh2LnmfCE3ea+3Cd1StEBQybIL2vcpmDW58RwC43qQEsFHi/G0LrGeipIsRJmXH5xbLx0DJNPv1eKWR2jeErQFtrWgU/bHVkXSaC7UM5PrrviGbYtIUgeC/JjVg0vmySrikKqLUHpeBPgrejiyuiNK8JAxzxDmeCjiSYmnlF7AkpQp0Kz1Ir3RqtxEp8E34ArGCPxu7UN6LS25JoeXHgOPou+l+pcmQlAxjhyqXEuKPdXG3SSazlPpJk1iB1TqfPgJ85/1tLzBYM69h32s2uTIPCWcssaoRJKwjh14yYI6kXEP6HTGT+L4S3yzk4GeXb45FNrrFcJN1DOBa0HsRJBky5IliQkR62JA==", "1; DM2PR0301MB0751;\n\t3:HFyjPezye4XVkeutyezrEJDhmjAmmj2h65H5xRSqbo0XcjwLGUUXbLMAXFkFM40pGW3PGWaWu5K1dJsXGst2AdfsyPIbcUlYi4iaDtKstBQe8x4VFKFfKRnihRi9OqLqLakZG4bVcbs1mdwmkuWEwK9IYZJG+r5lCR8DhekPD1h8hXCyUqGyTpZqhd9lGi4G40BFYqz0WXtHXI4l4qwkXjA/Rx85JseXAOWter2ebZvamTD8i0Vr6q2rj9QA5r/JSC3eobvcUgzSl/uN3GgcYFtOI+D7OOT9q6oskkxC1pGK1wJcy+4fRzSV0RowkO7NLN/ksSuATg9+/a8KzBmduxlEZiDDeztwaYvTdYn7hBSMsd6B2BDSI+ohM2i0V0N9", "1; DM2PR0301MB0751;\n\t25:mX9BL9uXoKFNR9wVPOyd+pMQ0zy5mskzSGg4zVdvkzQZnbjofcMz0I4h7bgFtl+mK72msqGF7JE+s73AC2c98HKVY9/yD+iLSTq90KSx9u+e6Lxad8K36RjXEwXrVdLaXuH2f63Y4UyQjbfIL0jwUDtJbvaNK3RfjtkAPQVPqKAB54rUkHnVfW1y04iRSxNAzg7y87t5PSdrauBZegEnAaXk+kS9mhaICqV+NSgU3y1lBzkzkiVX4gSJl/cknY2dcidHzHcWGoo5ut/dwLrj3RoJjH/DdksdzV7WrLVNaMjgSVU301TyvTPkd7Y4pb0dFGqXa2UZhYxrr57wezTPoa6rb44Rl1mAghssw7B20wG/AqTovLJfG/UGmlD4Sz0J2M3CJFYj5sFJvy3LLqQRqbxK8w1smeWSlYejvjOfZogJn8VdycAWK+6NuLAQQ799gEpfS72vf9+Q2P6qhQvA+QBpRBtOXRxjwruKd1wXAOFLFAUhU9bcmrXrvOIvvGninFuhgIfb5VU5Mb7kWXqv/WXTl3XNrLqKXNhtAk/blmrLw3XqRswDLK7wMtuCUqMF/XKl9qe82MXcJXEMOYGZD/M9hRxrpA3Fon/jUl3K6JKJloLGbug8Y4FB5/vnW4zBONYF8caFSKTR4qnJtWkzRYqLSNSFM2zmiURIt46jt/ZvYJJzMyIhvEogoYI9OJvsM7jnA9948AH14cijeuuKC/lhuEyTl3vPk1imLMgC9C1QT1xxfRDgOzurt/Wa2vNqZ8w5BpRFGghtzvSU94fJbyKnnLMkeqN+cOYH7i5GbG2ud1GqtjnW6JpUyt6sDPhY", "1; DM2PR0301MB0751;\n\t31:DwUAvk75+FgJIzEUYFA3FouR9xve2DK3bhxkM6SPs0afUYhCaTqpzNe3b5Hz0IKeRBzcSiWdn0DF2Ue+IaT46ULMcTB2KTGa1mdjNplg79iDCOXvC2LfyLMoFzTWvFq46a/wohSNg50UR0aM5NRo21ehC2TKZPXqxnkyUe5YgNgxfDpdblWWxL656cM9RIYVTmDtglo60lCgM1GkzxVczvP/H0c5oI6VER5sMaG9Of0PRIGmqfThqOr7gCbllrJfl/IRzDZxfxtGJ41OJHX63w==", "1; DM2PR0301MB0751;\n\t4:mOB1KT+1MCpNZ0DuM2K/ul5ee1594Mw/zO+to6XmY45Plh01gLztbaUSeIIJR55Mv4dga1VW8KYlUB+cL1tYBzsGc9bo0rdNsdfBGNS/94geoaBgYcQ3RMsv0T3Z4TRW2hoW05HnPcUYGeMxS3MJHBK0sJL3vinDsywWpkkbGJeFu9U9cv1Y2uHkC+v/W4kU8tobMrmHA10i5SvRABz37SNP2PMKWfteK4LngwcYQBOZyCSVp4+Wvmdv0sy0GxrV+IMbaYB5NN5hYrdjj8RjA4d41uycE4kOTlDy6EzxZofsVzmqjaeJSqv182gb3jTp5KC5WCQFPJlSJwHdq3zJuOYn/yO+MFDrIYJUmzH7Bo7ESIjVsJi4Bqrv3ZTU4HFAHLoYsC4KHihu9M1/TCuIsi08NDC41GaDnRkdWPO/ux8xJ/hCIVb2b+qeBSFWey4+E4jNQy4XZtjvr5JQjd/mog4YBXQs+rlFwP/hPKqk+z+tAdpmGBCf9QIv7CyKGcyMU4hFISx3TdQIJr3Rq204UJwNFAI4hPl3t2Nuz3VkUSDEhM8TY5BJRmV2Q5AvsO2YyjCbXNuiqIr5rmf1ZpMe4N3m5fk051E6Yd9HO3dDFpTVvpZfGMlVmGq3v+OkzgDoG4Ik72yWVH9RaNcnReGV2gGC5ZVsTj8TODfPuroxvPnLoaY9aBzsS+7fpoUgVNaznLhnKwCfSduFVUDfpBVCmD7ZkBEnotlD+mTtN19BORL+Mp7XfxBOMype+xzAdSH8", "=?us-ascii?Q?1; DM2PR0301MB0751;\n\t23:MKVF1JFl78gf57H8ZuY0LBoRrDqd0Ny0fAkfMbq?=\n\t0ADlfDXgW4VoXynDlQyezE2lz3km+Lg332gHeFQt97C3lnPRJsi6c5SRPfnoRD44LHd4777cnR2UVDc6kKZOjRl1f8PZFemxn0bcWR1VLxstlRRahDUdfZWY7JM4ZWSwitzFPrO2XiVJL8ZAbLX303k1mAM5rey7XrdmQlGMyohDTCQiDNp5Foanrd/yT/3njkB66l3aPA7ABiH+EmsENuFiGBN0oDnnK41HmCLkX0wtQsN1DzddOLifx+1hluR/kUWVBG5xVfe2LOHrNkqKObnMSz6IJD1+JUNlWWpwsCH0wxNXuu2Au7BQm7kpgVH6BhQHqMbPak63jf/CWTZaqT4Ch7bC0oiIJQ1yyBUezybDvpb2dAtLkkHhJg2lFCkEsEI0YH/wi9fzI2X2kYmWfzYfvZsBX5g9cqQr9DQNU8eVtkmkV+RCfIPtzamr204tHYNupHoNdzPlznquuHrhcpDUiQ7Kez7Hnb8FZqi9pX1AvXzRP3EgAz+3M5ctOW5+c6Vj4jajOxtXkbwSmVPq7eAcRynOu1lI4REZxbfnoUSNbinBJrUybIETOTdVgubFbrV4I7mUkj9fa4mMMU3SdzIMTnBfIz3Cym3yaFciAW1uIt4oLTzGYVKi2FjboOXNYUpM09/tLoNUWwsfcEvJbfcGNFGfUYI8d4VmWZT3CE0nFPnZgwfNa80t/1oiwg58eSiY1t383ztZTzAKB3HG1yMs98oqQzCDh9LnHb9uE4xDlbj3ON0EW0PbdirhQaVN2C1Sf0Tjm0wPuR5sZMg8ycPOgwgrUHCi+bdsEJDAD5TJOH9Islj53Vkb8xFcE096WJVG6aLBSTh4Aq2vKagVZtvs3IHxWr2uz1vtV9goGuBxwSSCE62GULh/vFTDrza23cn3KShEYo18sswkbzwXW/X55zGQuw/6j9ZxhEAy+Pmtuki5Q7Q6uOTdw03C5NDVVh4mjBvphfltE/WkOJwIhdT1YQ63IPIgPuBrMYHDU9ehG87H/CeNcA9GiJqt+uxl1Y2DMGRqb5xe3M9uhZEbOFm/PGmagMRgePzN4VpCfisrFMZrJbgCVk6lBBAJMiJqLtN4+lj72B7voUFhB9438T3mLCsPLsd2u0eOeI1H0E0Pl2wikWEIDJufj0EgSPgKEO1OZ3mcbmwRUz5CRYGYPTMl1Qdtwkd2vhgmlV+/IDLZJJ8PQEd54cTMxN0BJRTPXUyfr4HqKXNCBMSX1h+mp1WQCeeH+ByzZvuUZBf3jKsNmnH7RmZwVMTsR0pmgpmHdldrtO4bvmIEE5dy+p/gLjTpX", "1; DM2PR0301MB0751;\n\t6:QWs8RBq6hosa290nR7CtOewq2fDJ7kUdhCyUmlvbVhLMzUfkx5ooM1jZUuJz99oc3UcPFRHsOGjB9O34AwIX7XK8KkPPRPIB765jCaV9CfyLhmd6EYMFxM85EkdnHvHbkljhFAuT5ZvZZfo8CT59rCJS9Ytwg9W5HyOU7SZPRoMDxQabJk2Xgj/qoO15UyvE8krJBFhrBJ7h2iikM7IxX4yD/8vGfugJlxVwM5iwfcFRR7iVE3QilK9O4BmmIHmJ2+bTM6A9588FUGoNMBg6/ftn/u8ChPFvbK2kG3kEcnmWADDgC+7ZqVSZokPsXMdu3p5jOWlyf5fvN8aaV6nvfdX12Qzn9nE4awxMrrXsasg0zyN9d8Box7GMlx31tbx2lw9URsERbLLWRyidvYbmDHxFqwfLXAv0thnZeZsupoY6Jcrq/0QIbF3rOwm7B/Lw;\n\t5:8b8wJoWrq/D9L/EI4zVQOac1qNkROmrRkpu6882k1a0Ahb7J31eAbfVAPZMYKHNKe2fGifGSS632pReROCbN3ciqzqYUrimhMtsVQx0XKDKKGAekHk304i9ZAaQBKsgEep00IzVeEL8otmk6ZoWfTd5CFPuuaogmVC5SJ0npbPOEHnCkDW5D3ZCQEYHyfeBb;\n\t24:6WwFzbZlgfpOVmjVPcQi3QzxYHe6y4K79TpOQV6fgwrtjzY8EzbnE+Qq9ELMgQSBHk1wMFuDkdLP1ClGTecXNEVN8pkiWj3Wl693zzhrAJs=", "1; DM2PR0301MB0751;\n\t7:GDtWmGRk+WEOwHkbfdWVPY0u2iWev/99TiOpx4/C2r4XzKlPk6vcQ2RD6/gd31BVuDeXRrI41KDlbO7nNXMYOmfKkmHNPkzOpBYlngrTxa/XVs7kkIlb6zrp0RcOGXRRd51Yen6wakO33RRjfgm/Sgy7/U/aaY1CdfA9e3E3xTCwlScE2tgVE1SGUnSzGM2r1yiOP7BPur+CugSc6O1+dDVeXRYAwN+sQzbXLECKdg+rUYqmmrgQddIV+48VzykCKVA+RlO+O7X+YdyKF1B7oUQ2vhmrteNPXrawI/ORooyxzMvMsFtDGBcecuSTojabP2Dt6KuipR1xvBbfc97VNkB4hnrVtiCyYLzRDqBveM4LC1nU8Cn5NtOo1gSuP0W0K8EVXx64ljIrPNYU/59AO15Hh8BVCmkgYUM4LHpcjmkZ0KTRreivK7+MJ8rK7mx/qlaF0GExbmX+U6C//T+Wig==" ], "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MS-Office365-Filtering-Correlation-Id": "4bfd8d03-7cab-44e5-bdd9-08d42822ba0a", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0; RULEID:(22001);\n\tSRVR:DM2PR0301MB0751; ", "X-Microsoft-Antispam-PRVS": "<DM2PR0301MB07515C4540A3EA922F272B4A89910@DM2PR0301MB0751.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197);", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(6095060)(601004)(2401047)(13023025)(13017025)(13015025)(13018025)(13024025)(8121501046)(5005006)(3002001)(10201501046)(6055026)(6096035)(20161123563025)(20161123561025)(20161123559025)(20161123565025)(20161123556025);\n\tSRVR:DM2PR0301MB0751; BCL:0; PCL:0; RULEID:(400006);\n\tSRVR:DM2PR0301MB0751; ", "X-Forefront-PRVS": "01613DFDC8", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Dec 2016 15:21:37.8851\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.158.2]; \n\tHelo=[az84smr01.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM2PR0301MB0751", "Subject": "[dpdk-dev] [PATCHv2 19/34] net/dpaa2: add queue configuration\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "DPAA2 provide supports for HW queues. Each DPNI contains\na pre-configured number of RX and TX queues.\n\nThis patch reads the DPNI attributes, create the dpaa2_queue\nto be used for RX and TX.\n\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n doc/guides/nics/features/dpaa2.ini | 1 +\n drivers/common/dpaa2/dpio/dpaa2_hw_pvt.h | 20 +++\n drivers/net/dpaa2/dpaa2_ethdev.c | 293 ++++++++++++++++++++++++++++++-\n drivers/net/dpaa2/dpaa2_ethdev.h | 12 ++\n 4 files changed, 324 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/dpaa2.ini b/doc/guides/nics/features/dpaa2.ini\nindex b176208..0b59725 100644\n--- a/doc/guides/nics/features/dpaa2.ini\n+++ b/doc/guides/nics/features/dpaa2.ini\n@@ -4,6 +4,7 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Queue start/stop = Y\n Linux VFIO = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/drivers/common/dpaa2/dpio/dpaa2_hw_pvt.h b/drivers/common/dpaa2/dpio/dpaa2_hw_pvt.h\nindex dda6243..08be96c 100644\n--- a/drivers/common/dpaa2/dpio/dpaa2_hw_pvt.h\n+++ b/drivers/common/dpaa2/dpio/dpaa2_hw_pvt.h\n@@ -37,9 +37,12 @@\n #include <mc/fsl_mc_sys.h>\n #include <fsl_qbman_portal.h>\n \n+#define DPAA2_DQRR_RING_SIZE\t16\n+\t/** <Maximum number of slots available in RX ring*/\n \n #define MC_PORTAL_INDEX\t\t0\n #define NUM_DPIO_REGIONS\t2\n+#define NUM_DQS_PER_QUEUE 2\n \n #define MEMPOOL_F_HW_PKT_POOL 0x8000 /**< mpool flag to check offloaded pool */\n \n@@ -70,6 +73,23 @@ struct dpaa2_dpio_dev {\n \tint32_t hw_id; /**< An unique ID of this DPIO device instance */\n };\n \n+struct queue_storage_info_t {\n+\tstruct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];\n+};\n+\n+struct dpaa2_queue {\n+\tstruct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */\n+\tvoid *dev;\n+\tint32_t eventfd;\t/*!< Event Fd of this queue */\n+\tuint32_t fqid;\t\t/*!< Unique ID of this queue */\n+\tuint8_t tc_index;\t/*!< traffic class identifier */\n+\tuint16_t flow_id;\t/*!< To be used by DPAA2 frmework */\n+\tuint64_t rx_pkts;\n+\tuint64_t tx_pkts;\n+\tuint64_t err_pkts;\n+\tstruct queue_storage_info_t *q_storage;\n+};\n+\n /*! Global MCP list */\n extern void *(*mcp_ptr_list);\n #endif\ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c\nindex c0ace68..d511d7b 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.c\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.c\n@@ -54,6 +54,89 @@\n /* Name of the DPAA2 Net PMD */\n static const char *drivername = \"DPAA2 PMD\";\n \n+static void\n+dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n+{\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tdev_info->if_index = priv->hw_id;\n+\n+\tdev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;\n+\tdev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;\n+\n+\tdev_info->speed_capa = ETH_LINK_SPEED_1G |\n+\t\t\tETH_LINK_SPEED_2_5G |\n+\t\t\tETH_LINK_SPEED_10G;\n+}\n+\n+static int\n+dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)\n+{\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\tuint16_t dist_idx;\n+\tuint32_t vq_id;\n+\tstruct dpaa2_queue *mc_q, *mcq;\n+\tuint32_t tot_queues;\n+\tint i;\n+\tstruct dpaa2_queue *dpaa2_q;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttot_queues = priv->nb_rx_queues + priv->nb_tx_queues;\n+\tmc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,\n+\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!mc_q) {\n+\t\tPMD_INIT_LOG(ERR, \"malloc failed for rx/tx queues\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tfor (i = 0; i < priv->nb_rx_queues; i++) {\n+\t\tmc_q->dev = dev;\n+\t\tpriv->rx_vq[i] = mc_q++;\n+\t\tdpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];\n+\t\tdpaa2_q->q_storage = rte_malloc(\"dq_storage\",\n+\t\t\t\t\tsizeof(struct queue_storage_info_t),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\t\tif (!dpaa2_q->q_storage)\n+\t\t\tgoto fail;\n+\n+\t\tmemset(dpaa2_q->q_storage, 0,\n+\t\t sizeof(struct queue_storage_info_t));\n+\t\tdpaa2_q->q_storage->dq_storage[0] = rte_malloc(NULL,\n+\t\t\tDPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\t}\n+\n+\tfor (i = 0; i < priv->nb_tx_queues; i++) {\n+\t\tmc_q->dev = dev;\n+\t\tmc_q->flow_id = DPNI_NEW_FLOW_ID;\n+\t\tpriv->tx_vq[i] = mc_q++;\n+\t}\n+\n+\tvq_id = 0;\n+\tfor (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {\n+\t\tmcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];\n+\t\tmcq->tc_index = DPAA2_DEF_TC;\n+\t\tmcq->flow_id = dist_idx;\n+\t\tvq_id++;\n+\t}\n+\n+\treturn 0;\n+fail:\n+\ti -= 1;\n+\tmc_q = priv->rx_vq[0];\n+\twhile (i >= 0) {\n+\t\tdpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];\n+\t\trte_free(dpaa2_q->q_storage->dq_storage[0]);\n+\t\trte_free(dpaa2_q->q_storage);\n+\t\tpriv->rx_vq[i--] = NULL;\n+\t}\n+\trte_free(mc_q);\n+\treturn -1;\n+}\n+\n static int\n dpaa2_eth_dev_configure(struct rte_eth_dev *dev)\n {\n@@ -73,15 +156,134 @@\n \treturn 0;\n }\n \n+/* Function to setup RX flow information. It contains traffic class ID,\n+ * flow ID, destination configuration etc.\n+ */\n static int\n-dpaa2_dev_start(struct rte_eth_dev *dev)\n+dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,\n+\t\t\t uint16_t rx_queue_id,\n+\t\t\t uint16_t nb_rx_desc __rte_unused,\n+\t\t\t unsigned int socket_id __rte_unused,\n+\t\t\t const struct rte_eth_rxconf *rx_conf __rte_unused,\n+\t\t\t struct rte_mempool *mb_pool)\n {\n \tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n \tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tstruct dpaa2_queue *dpaa2_q;\n+\tstruct dpni_queue cfg;\n+\tuint8_t options = 0;\n+\tuint8_t flow_id;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tPMD_INIT_LOG(DEBUG, \"dev =%p, queue =%d, pool = %p, conf =%p\",\n+\t\t dev, rx_queue_id, mb_pool, rx_conf);\n+\n+\tdpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];\n+\tdpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */\n+\n+\t/*Get the tc id and flow id from given VQ id*/\n+\tflow_id = rx_queue_id;\n+\tmemset(&cfg, 0, sizeof(struct dpni_queue));\n+\n+\toptions = options | DPNI_QUEUE_OPT_USER_CTX;\n+\tcfg.user_context = (uint64_t)(dpaa2_q);\n+\n+\tret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,\n+\t\t\t dpaa2_q->tc_index, flow_id, options, &cfg);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Error in setting the rx flow: = %d\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\tdev->data->rx_queues[rx_queue_id] = dpaa2_q;\n+\treturn 0;\n+}\n+\n+static int\n+dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,\n+\t\t\t uint16_t tx_queue_id,\n+\t\t\t uint16_t nb_tx_desc __rte_unused,\n+\t\t\t unsigned int socket_id __rte_unused,\n+\t\t\t const struct rte_eth_txconf *tx_conf __rte_unused)\n+{\n+\tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n+\tstruct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)\n+\t\tpriv->tx_vq[tx_queue_id];\n+\tstruct fsl_mc_io *dpni = priv->hw;\n+\tstruct dpni_queue tx_conf_cfg;\n+\tstruct dpni_queue tx_flow_cfg;\n+\tuint8_t options = 0, flow_id;\n+\tuint32_t tc_id;\n \tint ret;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\t/* Return if queue already configured */\n+\tif (dpaa2_q->flow_id != DPNI_NEW_FLOW_ID)\n+\t\treturn 0;\n+\n+\tmemset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));\n+\tmemset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));\n+\n+\ttc_id = 0;\n+\tflow_id = tx_queue_id;\n+\n+\tret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,\n+\t\t\t tc_id, flow_id, options, &tx_flow_cfg);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Error in setting the tx flow: \"\n+\t\t\t \"tc_id=%d, flow =%d ErrorCode = %x\\n\",\n+\t\t\t tc_id, flow_id, -ret);\n+\t\t\treturn -1;\n+\t}\n+\n+\tdpaa2_q->flow_id = flow_id;\n+\n+\tif (tx_queue_id == 0) {\n+\t\t/*Set tx-conf and error configuration*/\n+\t\tret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,\n+\t\t\t\t\t\t priv->token,\n+\t\t\t\t\t\t DPNI_CONF_DISABLE);\n+\t\tif (ret) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Error in set tx conf mode settings\"\n+\t\t\t\t \" ErrorCode = %x\", ret);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\tdpaa2_q->tc_index = tc_id;\n+\n+\tdev->data->tx_queues[tx_queue_id] = dpaa2_q;\n+\treturn 0;\n+}\n+\n+static void\n+dpaa2_dev_rx_queue_release(void *q __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+}\n+\n+static void\n+dpaa2_dev_tx_queue_release(void *q __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+}\n+\n+static int\n+dpaa2_dev_start(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_eth_dev_data *data = dev->data;\n+\tstruct dpaa2_dev_priv *priv = data->dev_private;\n+\tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tstruct dpni_queue cfg;\n+\tuint16_t qdid;\n+\tstruct dpni_queue_id qid;\n+\tstruct dpaa2_queue *dpaa2_q;\n+\tint ret, i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n \tret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);\n \tif (ret) {\n \t\tPMD_INIT_LOG(ERR, \"Failure %d in enabling dpni %d device\\n\",\n@@ -89,6 +291,27 @@\n \t\treturn ret;\n \t}\n \n+\tret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t DPNI_QUEUE_TX, &qdid);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Error to get qdid:ErrorCode = %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tpriv->qdid = qdid;\n+\n+\tfor (i = 0; i < data->nb_rx_queues; i++) {\n+\t\tdpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];\n+\t\tret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t\t DPNI_QUEUE_RX, dpaa2_q->tc_index,\n+\t\t\t\t dpaa2_q->flow_id, &cfg, &qid);\n+\t\tif (ret) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Error to get flow \"\n+\t\t\t\t \"information Error code = %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tdpaa2_q->fqid = qid.fqid;\n+\t}\n+\n \treturn 0;\n }\n \n@@ -136,6 +359,11 @@\n \t.dev_start\t = dpaa2_dev_start,\n \t.dev_stop\t = dpaa2_dev_stop,\n \t.dev_close\t = dpaa2_dev_close,\n+\t.dev_infos_get\t = dpaa2_dev_info_get,\n+\t.rx_queue_setup = dpaa2_dev_rx_queue_setup,\n+\t.rx_queue_release = dpaa2_dev_rx_queue_release,\n+\t.tx_queue_setup = dpaa2_dev_tx_queue_setup,\n+\t.tx_queue_release = dpaa2_dev_tx_queue_release,\n };\n \n static int\n@@ -144,6 +372,7 @@\n \tstruct rte_device *dev = eth_dev->device;\n \tstruct rte_dpaa2_device *dpaa2_dev;\n \tstruct fsl_mc_io *dpni_dev;\n+\tstruct dpni_attr attr;\n \tstruct dpaa2_dev_priv *priv = eth_dev->data->dev_private;\n \tint ret, hw_id;\n \n@@ -179,8 +408,30 @@\n \t\treturn -1;\n \t}\n \n+\tret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure in getting dpni@%d attribute, \"\n+\t\t\t\" error code %d\\n\", hw_id, ret);\n+\t\treturn -1;\n+\t}\n+\n+\tpriv->num_tc = attr.num_tcs;\n+\tpriv->nb_rx_queues = attr.num_queues;\n+\tpriv->nb_tx_queues = attr.num_queues;\n+\n+\teth_dev->data->nb_rx_queues = priv->nb_rx_queues;\n+\teth_dev->data->nb_tx_queues = priv->nb_tx_queues;\n+\n \tpriv->hw = dpni_dev;\n \tpriv->hw_id = hw_id;\n+\tpriv->flags = 0;\n+\n+\tret = dpaa2_alloc_rx_tx_queues(eth_dev);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"dpaa2_alloc_rx_tx_queuesFailed\\n\");\n+\t\treturn -ret;\n+\t}\n+\n \teth_dev->dev_ops = &dpaa2_ethdev_ops;\n \teth_dev->data->drv_name = drivername;\n \n@@ -188,13 +439,51 @@\n }\n \n static int\n-dpaa2_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused)\n+dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)\n {\n+\tstruct dpaa2_dev_priv *priv = eth_dev->data->dev_private;\n+\tstruct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw;\n+\tint i, ret;\n+\tstruct dpaa2_queue *dpaa2_q;\n+\n \tPMD_INIT_FUNC_TRACE();\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn -EPERM;\n \n+\tif (!dpni) {\n+\t\tPMD_INIT_LOG(WARNING, \"Already closed or not started\");\n+\t\treturn -1;\n+\t}\n+\n+\tdpaa2_dev_close(eth_dev);\n+\n+\tif (priv->rx_vq[0]) {\n+\t\t/* cleaning up queue storage */\n+\t\tfor (i = 0; i < priv->nb_rx_queues; i++) {\n+\t\t\tdpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];\n+\t\t\tif (dpaa2_q->q_storage)\n+\t\t\t\trte_free(dpaa2_q->q_storage);\n+\t\t}\n+\t\t/*free the all queue memory */\n+\t\trte_free(priv->rx_vq[0]);\n+\t\tpriv->rx_vq[0] = NULL;\n+\t}\n+\n+\n+\t/*Close the device at underlying layer*/\n+\tret = dpni_close(dpni, CMD_PRI_LOW, priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure closing dpni device with\"\n+\t\t\t\" error code %d\\n\", ret);\n+\t}\n+\n+\t/*Free the allocated memory for ethernet private data and dpni*/\n+\tpriv->hw = NULL;\n+\tfree(dpni);\n+\n+\teth_dev->dev_ops = NULL;\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h\nindex 840b688..5f599a7 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.h\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.h\n@@ -37,11 +37,23 @@\n #include <mc/fsl_dpni.h>\n #include <mc/fsl_mc_sys.h>\n \n+#define MAX_RX_QUEUES\t\t16\n+#define MAX_TX_QUEUES\t\t16\n+\n+/*default tc to be used for ,congestion, distribution etc configuration. */\n+#define DPAA2_DEF_TC\t\t0\n+\n struct dpaa2_dev_priv {\n \tvoid *hw;\n \tint32_t hw_id;\n+\tint32_t qdid;\n \tuint16_t token;\n+\tuint8_t nb_tx_queues;\n+\tuint8_t nb_rx_queues;\n+\tvoid *rx_vq[MAX_RX_QUEUES];\n+\tvoid *tx_vq[MAX_TX_QUEUES];\n \n+\tuint8_t num_tc;\n \tuint8_t flags; /*dpaa2 config flags */\n };\n #endif /* _DPAA2_ETHDEV_H */\n", "prefixes": [ "dpdk-dev", "PATCHv2", "19/34" ] }