Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/18170/?format=api
{ "id": 18170, "url": "http://patches.dpdk.org/api/patches/18170/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1482180853-18823-11-git-send-email-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1482180853-18823-11-git-send-email-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1482180853-18823-11-git-send-email-hemant.agrawal@nxp.com", "date": "2016-12-19T20:53:49", "name": "[dpdk-dev,PATCHv2,10/34] bus/fslmc: add mc dpseci object support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6afbba9e4df2f3aeb85d1aa822c04643a17600b7", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1482180853-18823-11-git-send-email-hemant.agrawal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/18170/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/18170/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 5A216FA74;\n\tMon, 19 Dec 2016 16:21:37 +0100 (CET)", "from NAM03-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam03on0080.outbound.protection.outlook.com [104.47.42.80])\n\tby dpdk.org (Postfix) with ESMTP id 6FFFBFA31\n\tfor <dev@dpdk.org>; Mon, 19 Dec 2016 16:21:10 +0100 (CET)", "from CY1PR03CA0036.namprd03.prod.outlook.com (10.174.128.46) by\n\tBN1PR0301MB0738.namprd03.prod.outlook.com (10.160.78.145) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.789.14; Mon, 19 Dec 2016 15:21:08 +0000", "from BN1AFFO11FD021.protection.gbl (2a01:111:f400:7c10::109) by\n\tCY1PR03CA0036.outlook.office365.com (2603:10b6:600::46) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.789.14 via Frontend Transport; Mon, 19 Dec 2016 15:21:07 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBN1AFFO11FD021.mail.protection.outlook.com (10.58.52.81) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.789.10\n\tvia Frontend Transport; Mon, 19 Dec 2016 15:21:06 +0000", "from bf-netperf1.idc ([10.232.134.28])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tuBJFKMhZ029110; Mon, 19 Dec 2016 08:21:03 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com;\n\tnxp.com; \n\tdkim=none (message not signed) header.d=none;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,\n\t<shreyansh.jain@nxp.com>, <john.mcnamara@intel.com>,\n\t<ferruh.yigit@intel.com>, <jerin.jacob@caviumnetworks.com>,\n\tCristian Sovaiala\n\t<cristian.sovaiala@nxp.com>, Hemant Agrawal <hemant.agrawal@nxp.com>", "Date": "Tue, 20 Dec 2016 02:23:49 +0530", "Message-ID": "<1482180853-18823-11-git-send-email-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1482180853-18823-1-git-send-email-hemant.agrawal@nxp.com>", "References": "<1480875447-23680-1-git-send-email-hemant.agrawal@nxp.com>\n\t<1482180853-18823-1-git-send-email-hemant.agrawal@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131266344671477849;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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\n\tHelo=[az84smr01.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN1PR0301MB0738", "Subject": "[dpdk-dev] [PATCHv2 10/34] bus/fslmc: add mc dpseci object support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "dpseci represent a instance of SEC HW in DPAA2.\n\nSigned-off-by: Cristian Sovaiala <cristian.sovaiala@nxp.com>\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n drivers/bus/fslmc/Makefile | 1 +\n drivers/bus/fslmc/mc/dpseci.c | 527 +++++++++++++++++++++++++++\n drivers/bus/fslmc/mc/fsl_dpseci.h | 661 ++++++++++++++++++++++++++++++++++\n drivers/bus/fslmc/mc/fsl_dpseci_cmd.h | 248 +++++++++++++\n 4 files changed, 1437 insertions(+)\n create mode 100644 drivers/bus/fslmc/mc/dpseci.c\n create mode 100644 drivers/bus/fslmc/mc/fsl_dpseci.h\n create mode 100644 drivers/bus/fslmc/mc/fsl_dpseci_cmd.h", "diff": "diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile\nindex a53e3f4..f5da4e0 100644\n--- a/drivers/bus/fslmc/Makefile\n+++ b/drivers/bus/fslmc/Makefile\n@@ -50,6 +50,7 @@ LIBABIVER := 1\n \n SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += \\\n mc/dpni.c \\\n+ mc/dpseci.c \\\n mc/dpbp.c \\\n mc/dpio.c \\\n mc/mc_sys.c\ndiff --git a/drivers/bus/fslmc/mc/dpseci.c b/drivers/bus/fslmc/mc/dpseci.c\nnew file mode 100644\nindex 0000000..173a40c\n--- /dev/null\n+++ b/drivers/bus/fslmc/mc/dpseci.c\n@@ -0,0 +1,527 @@\n+/* Copyright 2013-2016 Freescale Semiconductor Inc.\n+ * Copyright (c) 2016 NXP.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <fsl_mc_sys.h>\n+#include <fsl_mc_cmd.h>\n+#include <fsl_dpseci.h>\n+#include <fsl_dpseci_cmd.h>\n+\n+int dpseci_open(struct fsl_mc_io *mc_io,\n+\t\tuint32_t cmd_flags,\n+\t\tint dpseci_id,\n+\t\tuint16_t *token)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_OPEN,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t 0);\n+\tDPSECI_CMD_OPEN(cmd, dpseci_id);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\t*token = MC_CMD_HDR_READ_TOKEN(cmd.header);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_close(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLOSE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_create(struct fsl_mc_io\t*mc_io,\n+\t\t uint16_t\tdprc_token,\n+\t\t uint32_t\tcmd_flags,\n+\t\t const struct dpseci_cfg\t*cfg,\n+\t\t uint32_t\t*obj_id)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_CREATE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t dprc_token);\n+\tDPSECI_CMD_CREATE(cmd, cfg);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tCMD_CREATE_RSP_GET_OBJ_ID_PARAM0(cmd, *obj_id);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_destroy(struct fsl_mc_io\t*mc_io,\n+\t\t uint16_t\tdprc_token,\n+\t\t uint32_t\tcmd_flags,\n+\t\t uint32_t\tobject_id)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_DESTROY,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t dprc_token);\n+\t/* set object id to destroy */\n+\tCMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id);\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_enable(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_ENABLE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_disable(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_DISABLE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_is_enabled(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token,\n+\t\t int *en)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_IS_ENABLED,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_IS_ENABLED(cmd, *en);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_reset(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_RESET,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_get_irq(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token,\n+\t\t uint8_t irq_index,\n+\t\t int *type,\n+\t\t struct dpseci_irq_cfg *irq_cfg)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_GET_IRQ(cmd, irq_index);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_GET_IRQ(cmd, *type, irq_cfg);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_set_irq(struct fsl_mc_io *mc_io,\n+\t\t uint32_t cmd_flags,\n+\t\t uint16_t token,\n+\t\t uint8_t irq_index,\n+\t\t struct dpseci_irq_cfg *irq_cfg)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_SET_IRQ(cmd, irq_index, irq_cfg);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_get_irq_enable(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t token,\n+\t\t\t uint8_t irq_index,\n+\t\t\t uint8_t *en)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_ENABLE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_GET_IRQ_ENABLE(cmd, irq_index);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_GET_IRQ_ENABLE(cmd, *en);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_set_irq_enable(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t token,\n+\t\t\t uint8_t irq_index,\n+\t\t\t uint8_t en)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_ENABLE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_SET_IRQ_ENABLE(cmd, irq_index, en);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_get_irq_mask(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t irq_index,\n+\t\t\tuint32_t *mask)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_MASK,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_GET_IRQ_MASK(cmd, irq_index);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_GET_IRQ_MASK(cmd, *mask);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_set_irq_mask(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t irq_index,\n+\t\t\tuint32_t mask)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_MASK,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_SET_IRQ_MASK(cmd, irq_index, mask);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_get_irq_status(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t token,\n+\t\t\t uint8_t irq_index,\n+\t\t\t uint32_t *status)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_STATUS,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_GET_IRQ_STATUS(cmd, irq_index, *status);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_GET_IRQ_STATUS(cmd, *status);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_clear_irq_status(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t token,\n+\t\t\t uint8_t irq_index,\n+\t\t\t uint32_t status)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLEAR_IRQ_STATUS,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_get_attributes(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t token,\n+\t\t\t struct dpseci_attr *attr)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_ATTR,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_GET_ATTR(cmd, attr);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_set_rx_queue(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t queue,\n+\t\t\tconst struct dpseci_rx_queue_cfg *cfg)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_RX_QUEUE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_SET_RX_QUEUE(cmd, queue, cfg);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpseci_get_rx_queue(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t queue,\n+\t\t\tstruct dpseci_rx_queue_attr *attr)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_RX_QUEUE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_GET_RX_QUEUE(cmd, queue);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_GET_RX_QUEUE(cmd, attr);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_get_tx_queue(struct fsl_mc_io *mc_io,\n+\t\t\tuint32_t cmd_flags,\n+\t\t\tuint16_t token,\n+\t\t\tuint8_t queue,\n+\t\t\tstruct dpseci_tx_queue_attr *attr)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_TX_QUEUE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tDPSECI_CMD_GET_TX_QUEUE(cmd, queue);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_GET_TX_QUEUE(cmd, attr);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_get_sec_attr(struct fsl_mc_io\t\t*mc_io,\n+\t\t\tuint32_t\t\t\tcmd_flags,\n+\t\t\tuint16_t\t\t\ttoken,\n+\t\t\tstruct dpseci_sec_attr *attr)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_ATTR,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_GET_SEC_ATTR(cmd, attr);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_get_sec_counters(struct fsl_mc_io\t\t*mc_io,\n+\t\t\t uint32_t\t\t\tcmd_flags,\n+\t\tuint16_t\t\t\ttoken,\n+\t\tstruct dpseci_sec_counters *counters)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_COUNTERS,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\n+\t/* send command to mc*/\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* retrieve response parameters */\n+\tDPSECI_RSP_GET_SEC_COUNTERS(cmd, counters);\n+\n+\treturn 0;\n+}\n+\n+int dpseci_get_api_version(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t *major_ver,\n+\t\t\t uint16_t *minor_ver)\n+{\n+\tstruct mc_command cmd = { 0 };\n+\tint err;\n+\n+\tcmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_API_VERSION,\n+\t\t\t\t\tcmd_flags,\n+\t\t\t\t\t0);\n+\n+\terr = mc_send_command(mc_io, &cmd);\n+\tif (err)\n+\t\treturn err;\n+\n+\tDPSECI_RSP_GET_API_VERSION(cmd, *major_ver, *minor_ver);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/bus/fslmc/mc/fsl_dpseci.h b/drivers/bus/fslmc/mc/fsl_dpseci.h\nnew file mode 100644\nindex 0000000..644e30c\n--- /dev/null\n+++ b/drivers/bus/fslmc/mc/fsl_dpseci.h\n@@ -0,0 +1,661 @@\n+/* Copyright 2013-2016 Freescale Semiconductor Inc.\n+ * Copyright (c) 2016 NXP.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __FSL_DPSECI_H\n+#define __FSL_DPSECI_H\n+\n+/* Data Path SEC Interface API\n+ * Contains initialization APIs and runtime control APIs for DPSECI\n+ */\n+\n+struct fsl_mc_io;\n+\n+/**\n+ * General DPSECI macros\n+ */\n+\n+/**\n+ * Maximum number of Tx/Rx priorities per DPSECI object\n+ */\n+#define DPSECI_PRIO_NUM\t\t8\n+\n+/**\n+ * All queues considered; see dpseci_set_rx_queue()\n+ */\n+#define DPSECI_ALL_QUEUES\t(uint8_t)(-1)\n+\n+/**\n+ * dpseci_open() - Open a control session for the specified object\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @dpseci_id:\tDPSECI unique ID\n+ * @token:\tReturned token; use in subsequent API calls\n+ *\n+ * This function can be used to open a control session for an\n+ * already created object; an object may have been declared in\n+ * the DPL or by calling the dpseci_create() function.\n+ * This function returns a unique authentication token,\n+ * associated with the specific object ID and the specific MC\n+ * portal; this token must be used in all subsequent commands for\n+ * this specific object.\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_open(struct fsl_mc_io\t*mc_io,\n+\t\tuint32_t\t\tcmd_flags,\n+\t\tint\t\t\tdpseci_id,\n+\t\tuint16_t\t\t*token);\n+\n+/**\n+ * dpseci_close() - Close the control session of the object\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ *\n+ * After this function is called, no further operations are\n+ * allowed on the object without opening a new control session.\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_close(struct fsl_mc_io\t*mc_io,\n+\t\t uint32_t\t\tcmd_flags,\n+\t\t uint16_t\t\ttoken);\n+\n+/**\n+ * struct dpseci_cfg - Structure representing DPSECI configuration\n+ * @num_tx_queues: num of queues towards the SEC\n+ * @num_rx_queues: num of queues back from the SEC\n+ * @priorities: Priorities for the SEC hardware processing;\n+ *\t\teach place in the array is the priority of the tx queue\n+ *\t\ttowards the SEC,\n+ *\t\tvalid priorities are configured with values 1-8;\n+ */\n+struct dpseci_cfg {\n+\tuint8_t num_tx_queues;\n+\tuint8_t num_rx_queues;\n+\tuint8_t priorities[DPSECI_PRIO_NUM];\n+};\n+\n+/**\n+ * dpseci_create() - Create the DPSECI object\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @dprc_token:\tParent container token; '0' for default container\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @cfg:\tConfiguration structure\n+ * @obj_id: returned object id\n+ *\n+ * Create the DPSECI object, allocate required resources and\n+ * perform required initialization.\n+ *\n+ * The object can be created either by declaring it in the\n+ * DPL file, or by calling this function.\n+ *\n+ * The function accepts an authentication token of a parent\n+ * container that this object should be assigned to. The token\n+ * can be '0' so the object will be assigned to the default container.\n+ * The newly created object can be opened with the returned\n+ * object id and using the container's associated tokens and MC portals.\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_create(struct fsl_mc_io\t\t*mc_io,\n+\t\t uint16_t\t\t\tdprc_token,\n+\t\t uint32_t\t\t\tcmd_flags,\n+\t\t const struct dpseci_cfg\t*cfg,\n+\t\t uint32_t\t\t\t*obj_id);\n+\n+/**\n+ * dpseci_destroy() - Destroy the DPSECI object and release all its resources.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @dprc_token: Parent container token; '0' for default container\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @object_id:\tThe object id; it must be a valid id within the container that\n+ * created this object;\n+ *\n+ * The function accepts the authentication token of the parent container that\n+ * created the object (not the one that currently owns the object). The object\n+ * is searched within parent using the provided 'object_id'.\n+ * All tokens to the object must be closed before calling destroy.\n+ *\n+ * Return:\t'0' on Success; error code otherwise.\n+ */\n+int dpseci_destroy(struct fsl_mc_io\t*mc_io,\n+\t\t uint16_t\t\tdprc_token,\n+\t\t uint32_t\t\tcmd_flags,\n+\t\t uint32_t\t\tobject_id);\n+\n+/**\n+ * dpseci_enable() - Enable the DPSECI, allow sending and receiving frames.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_enable(struct fsl_mc_io\t*mc_io,\n+\t\t uint32_t\t\tcmd_flags,\n+\t\t uint16_t\t\ttoken);\n+\n+/**\n+ * dpseci_disable() - Disable the DPSECI, stop sending and receiving frames.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_disable(struct fsl_mc_io\t*mc_io,\n+\t\t uint32_t\t\tcmd_flags,\n+\t\t uint16_t\t\ttoken);\n+\n+/**\n+ * dpseci_is_enabled() - Check if the DPSECI is enabled.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ * @en:\t\tReturns '1' if object is enabled; '0' otherwise\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_is_enabled(struct fsl_mc_io\t*mc_io,\n+\t\t uint32_t\t\tcmd_flags,\n+\t\t uint16_t\t\ttoken,\n+\t\t int\t\t*en);\n+\n+/**\n+ * dpseci_reset() - Reset the DPSECI, returns the object to initial state.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_reset(struct fsl_mc_io\t*mc_io,\n+\t\t uint32_t\t\tcmd_flags,\n+\t\t uint16_t\t\ttoken);\n+\n+/**\n+ * struct dpseci_irq_cfg - IRQ configuration\n+ * @addr:\tAddress that must be written to signal a message-based interrupt\n+ * @val:\tValue to write into irq_addr address\n+ * @irq_num: A user defined number associated with this IRQ\n+ */\n+struct dpseci_irq_cfg {\n+\t uint64_t\t\taddr;\n+\t uint32_t\t\tval;\n+\t int\t\tirq_num;\n+};\n+\n+/**\n+ * dpseci_set_irq() - Set IRQ information for the DPSECI to trigger an interrupt\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ * @irq_index:\tIdentifies the interrupt index to configure\n+ * @irq_cfg:\tIRQ configuration\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_set_irq(struct fsl_mc_io\t\t*mc_io,\n+\t\t uint32_t\t\t\tcmd_flags,\n+\t\t uint16_t\t\t\ttoken,\n+\t\t uint8_t\t\t\tirq_index,\n+\t\t struct dpseci_irq_cfg\t*irq_cfg);\n+\n+/**\n+ * dpseci_get_irq() - Get IRQ information from the DPSECI\n+ *\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @type:\tInterrupt type: 0 represents message interrupt\n+ *\t\ttype (both irq_addr and irq_val are valid)\n+ * @irq_cfg:\tIRQ attributes\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_irq(struct fsl_mc_io\t\t*mc_io,\n+\t\t uint32_t\t\t\tcmd_flags,\n+\t\t uint16_t\t\t\ttoken,\n+\t\t uint8_t\t\t\tirq_index,\n+\t\t int\t\t\t\t*type,\n+\t\t struct dpseci_irq_cfg\t*irq_cfg);\n+\n+/**\n+ * dpseci_set_irq_enable() - Set overall interrupt state.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\t\tToken of DPSECI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @en:\t\t\tInterrupt state - enable = 1, disable = 0\n+ *\n+ * Allows GPP software to control when interrupts are generated.\n+ * Each interrupt can have up to 32 causes. The enable/disable control's the\n+ * overall interrupt state. if the interrupt is disabled no causes will cause\n+ * an interrupt\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_set_irq_enable(struct fsl_mc_io\t*mc_io,\n+\t\t\t uint32_t\t\tcmd_flags,\n+\t\t\t uint16_t\t\ttoken,\n+\t\t\t uint8_t\t\tirq_index,\n+\t\t\t uint8_t\t\ten);\n+\n+/**\n+ * dpseci_get_irq_enable() - Get overall interrupt state\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\t\tToken of DPSECI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @en:\t\t\tReturned Interrupt state - enable = 1, disable = 0\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_irq_enable(struct fsl_mc_io\t*mc_io,\n+\t\t\t uint32_t\t\tcmd_flags,\n+\t\t\t uint16_t\t\ttoken,\n+\t\t\t uint8_t\t\tirq_index,\n+\t\t\t uint8_t\t\t*en);\n+\n+/**\n+ * dpseci_set_irq_mask() - Set interrupt mask.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\t\tToken of DPSECI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @mask:\t\tevent mask to trigger interrupt;\n+ *\t\t\t\teach bit:\n+ *\t\t\t\t\t0 = ignore event\n+ *\t\t\t\t\t1 = consider event for asserting IRQ\n+ *\n+ * Every interrupt can have up to 32 causes and the interrupt model supports\n+ * masking/unmasking each cause independently\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_set_irq_mask(struct fsl_mc_io\t*mc_io,\n+\t\t\tuint32_t\t\tcmd_flags,\n+\t\t\tuint16_t\t\ttoken,\n+\t\t\tuint8_t\t\t\tirq_index,\n+\t\t\tuint32_t\t\tmask);\n+\n+/**\n+ * dpseci_get_irq_mask() - Get interrupt mask.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\t\tToken of DPSECI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @mask:\t\tReturned event mask to trigger interrupt\n+ *\n+ * Every interrupt can have up to 32 causes and the interrupt model supports\n+ * masking/unmasking each cause independently\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_irq_mask(struct fsl_mc_io\t*mc_io,\n+\t\t\tuint32_t\t\tcmd_flags,\n+\t\t\tuint16_t\t\ttoken,\n+\t\t\tuint8_t\t\t\tirq_index,\n+\t\t\tuint32_t\t\t*mask);\n+\n+/**\n+ * dpseci_get_irq_status() - Get the current status of any pending interrupts\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\t\tToken of DPSECI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @status:\t\tReturned interrupts status - one bit per cause:\n+ *\t\t\t\t\t0 = no interrupt pending\n+ *\t\t\t\t\t1 = interrupt pending\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_irq_status(struct fsl_mc_io\t*mc_io,\n+\t\t\t uint32_t\t\tcmd_flags,\n+\t\t\t uint16_t\t\ttoken,\n+\t\t\t uint8_t\t\tirq_index,\n+\t\t\t uint32_t\t\t*status);\n+\n+/**\n+ * dpseci_clear_irq_status() - Clear a pending interrupt's status\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\t\tToken of DPSECI object\n+ * @irq_index:\tThe interrupt index to configure\n+ * @status:\t\tbits to clear (W1C) - one bit per cause:\n+ *\t\t\t\t\t0 = don't change\n+ *\t\t\t\t\t1 = clear status bit\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_clear_irq_status(struct fsl_mc_io\t*mc_io,\n+\t\t\t uint32_t\t\tcmd_flags,\n+\t\t\t uint16_t\t\ttoken,\n+\t\t\t uint8_t\t\tirq_index,\n+\t\t\t uint32_t\t\tstatus);\n+\n+/**\n+ * struct dpseci_attr - Structure representing DPSECI attributes\n+ * @id: DPSECI object ID\n+ * @num_tx_queues: number of queues towards the SEC\n+ * @num_rx_queues: number of queues back from the SEC\n+ */\n+struct dpseci_attr {\n+\tint\tid;\n+\tuint8_t\tnum_tx_queues;\n+\tuint8_t\tnum_rx_queues;\n+};\n+\n+/**\n+ * dpseci_get_attributes() - Retrieve DPSECI attributes.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ * @attr:\tReturned object's attributes\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_attributes(struct fsl_mc_io\t*mc_io,\n+\t\t\t uint32_t\t\tcmd_flags,\n+\t\t\t uint16_t\t\ttoken,\n+\t\t\t struct dpseci_attr\t*attr);\n+\n+/**\n+ * enum dpseci_dest - DPSECI destination types\n+ * @DPSECI_DEST_NONE: Unassigned destination; The queue is set in parked mode\n+ *\t\tand does not generate FQDAN notifications; user is expected to\n+ *\t\tdequeue from the queue based on polling or other user-defined\n+ *\t\tmethod\n+ * @DPSECI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN\n+ *\t\tnotifications to the specified DPIO; user is expected to dequeue\n+ *\t\tfrom the queue only after notification is received\n+ * @DPSECI_DEST_DPCON: The queue is set in schedule mode and does not generate\n+ *\t\tFQDAN notifications, but is connected to the specified DPCON\n+ *\t\tobject; user is expected to dequeue from the DPCON channel\n+ */\n+enum dpseci_dest {\n+\tDPSECI_DEST_NONE = 0,\n+\tDPSECI_DEST_DPIO = 1,\n+\tDPSECI_DEST_DPCON = 2\n+};\n+\n+/**\n+ * struct dpseci_dest_cfg - Structure representing DPSECI destination parameters\n+ * @dest_type: Destination type\n+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type\n+ * @priority: Priority selection within the DPIO or DPCON channel; valid values\n+ *\tare 0-1 or 0-7, depending on the number of priorities in that\n+ *\tchannel; not relevant for 'DPSECI_DEST_NONE' option\n+ */\n+struct dpseci_dest_cfg {\n+\tenum dpseci_dest\tdest_type;\n+\tint\t\t\tdest_id;\n+\tuint8_t\t\t\tpriority;\n+};\n+\n+/**\n+ * DPSECI queue modification options\n+ */\n+\n+/**\n+ * Select to modify the user's context associated with the queue\n+ */\n+#define DPSECI_QUEUE_OPT_USER_CTX\t\t0x00000001\n+\n+/**\n+ * Select to modify the queue's destination\n+ */\n+#define DPSECI_QUEUE_OPT_DEST\t\t\t0x00000002\n+\n+/**\n+ * Select to modify the queue's order preservation\n+ */\n+#define DPSECI_QUEUE_OPT_ORDER_PRESERVATION\t0x00000004\n+\n+/**\n+ * struct dpseci_rx_queue_cfg - DPSECI RX queue configuration\n+ * @options: Flags representing the suggested modifications to the queue;\n+ *\tUse any combination of 'DPSECI_QUEUE_OPT_<X>' flags\n+ * @order_preservation_en: order preservation configuration for the rx queue\n+ * valid only if 'DPSECI_QUEUE_OPT_ORDER_PRESERVATION' is contained in 'options'\n+ * @user_ctx: User context value provided in the frame descriptor of each\n+ *\tdequeued frame;\n+ *\tvalid only if 'DPSECI_QUEUE_OPT_USER_CTX' is contained in 'options'\n+ * @dest_cfg: Queue destination parameters;\n+ *\tvalid only if 'DPSECI_QUEUE_OPT_DEST' is contained in 'options'\n+ */\n+struct dpseci_rx_queue_cfg {\n+\tuint32_t options;\n+\tint order_preservation_en;\n+\tuint64_t user_ctx;\n+\tstruct dpseci_dest_cfg dest_cfg;\n+};\n+\n+/**\n+ * dpseci_set_rx_queue() - Set Rx queue configuration\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ * @queue:\tSelect the queue relative to number of\n+ *\t\tpriorities configured at DPSECI creation; use\n+ *\t\tDPSECI_ALL_QUEUES to configure all Rx queues identically.\n+ * @cfg:\tRx queue configuration\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_set_rx_queue(struct fsl_mc_io\t\t\t*mc_io,\n+\t\t\tuint32_t\t\t\t\tcmd_flags,\n+\t\t\tuint16_t\t\t\t\ttoken,\n+\t\t\tuint8_t\t\t\t\t\tqueue,\n+\t\t\tconst struct dpseci_rx_queue_cfg\t*cfg);\n+\n+/**\n+ * struct dpseci_rx_queue_attr - Structure representing attributes of Rx queues\n+ * @user_ctx: User context value provided in the frame descriptor of each\n+ *\tdequeued frame\n+ * @order_preservation_en: Status of the order preservation configuration\n+ *\t\t\t\ton the queue\n+ * @dest_cfg: Queue destination configuration\n+ * @fqid: Virtual FQID value to be used for dequeue operations\n+ */\n+struct dpseci_rx_queue_attr {\n+\tuint64_t\t\tuser_ctx;\n+\tint\t\t\torder_preservation_en;\n+\tstruct dpseci_dest_cfg\tdest_cfg;\n+\tuint32_t\t\tfqid;\n+};\n+\n+/**\n+ * dpseci_get_rx_queue() - Retrieve Rx queue attributes.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ * @queue:\tSelect the queue relative to number of\n+ *\t\t\t\tpriorities configured at DPSECI creation\n+ * @attr:\tReturned Rx queue attributes\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_rx_queue(struct fsl_mc_io\t\t*mc_io,\n+\t\t\tuint32_t\t\t\tcmd_flags,\n+\t\t\tuint16_t\t\t\ttoken,\n+\t\t\tuint8_t\t\t\t\tqueue,\n+\t\t\tstruct dpseci_rx_queue_attr\t*attr);\n+\n+/**\n+ * struct dpseci_tx_queue_attr - Structure representing attributes of Tx queues\n+ * @fqid: Virtual FQID to be used for sending frames to SEC hardware\n+ * @priority: SEC hardware processing priority for the queue\n+ */\n+struct dpseci_tx_queue_attr {\n+\tuint32_t fqid;\n+\tuint8_t priority;\n+};\n+\n+/**\n+ * dpseci_get_tx_queue() - Retrieve Tx queue attributes.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ * @queue:\tSelect the queue relative to number of\n+ *\t\t\t\tpriorities configured at DPSECI creation\n+ * @attr:\tReturned Tx queue attributes\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_tx_queue(struct fsl_mc_io\t\t*mc_io,\n+\t\t\tuint32_t\t\t\tcmd_flags,\n+\t\t\tuint16_t\t\t\ttoken,\n+\t\t\tuint8_t\t\t\t\tqueue,\n+\t\t\tstruct dpseci_tx_queue_attr\t*attr);\n+\n+/**\n+ * struct dpseci_sec_attr - Structure representing attributes of the SEC\n+ *\t\t\thardware accelerator\n+ * @ip_id:\tID for SEC.\n+ * @major_rev: Major revision number for SEC.\n+ * @minor_rev: Minor revision number for SEC.\n+ * @era: SEC Era.\n+ * @deco_num: The number of copies of the DECO that are implemented in\n+ * this version of SEC.\n+ * @zuc_auth_acc_num: The number of copies of ZUCA that are implemented\n+ * in this version of SEC.\n+ * @zuc_enc_acc_num: The number of copies of ZUCE that are implemented\n+ * in this version of SEC.\n+ * @snow_f8_acc_num: The number of copies of the SNOW-f8 module that are\n+ * implemented in this version of SEC.\n+ * @snow_f9_acc_num: The number of copies of the SNOW-f9 module that are\n+ * implemented in this version of SEC.\n+ * @crc_acc_num: The number of copies of the CRC module that are implemented\n+ * in this version of SEC.\n+ * @pk_acc_num: The number of copies of the Public Key module that are\n+ * implemented in this version of SEC.\n+ * @kasumi_acc_num: The number of copies of the Kasumi module that are\n+ * implemented in this version of SEC.\n+ * @rng_acc_num: The number of copies of the Random Number Generator that are\n+ * implemented in this version of SEC.\n+ * @md_acc_num: The number of copies of the MDHA (Hashing module) that are\n+ * implemented in this version of SEC.\n+ * @arc4_acc_num: The number of copies of the ARC4 module that are implemented\n+ * in this version of SEC.\n+ * @des_acc_num: The number of copies of the DES module that are implemented\n+ * in this version of SEC.\n+ * @aes_acc_num: The number of copies of the AES module that are implemented\n+ * in this version of SEC.\n+ **/\n+\n+struct dpseci_sec_attr {\n+\tuint16_t\tip_id;\n+\tuint8_t\tmajor_rev;\n+\tuint8_t\tminor_rev;\n+\tuint8_t\tera;\n+\tuint8_t\tdeco_num;\n+\tuint8_t\tzuc_auth_acc_num;\n+\tuint8_t\tzuc_enc_acc_num;\n+\tuint8_t\tsnow_f8_acc_num;\n+\tuint8_t\tsnow_f9_acc_num;\n+\tuint8_t\tcrc_acc_num;\n+\tuint8_t\tpk_acc_num;\n+\tuint8_t\tkasumi_acc_num;\n+\tuint8_t\trng_acc_num;\n+\tuint8_t\tmd_acc_num;\n+\tuint8_t\tarc4_acc_num;\n+\tuint8_t\tdes_acc_num;\n+\tuint8_t\taes_acc_num;\n+};\n+\n+/**\n+ * dpseci_get_sec_attr() - Retrieve SEC accelerator attributes.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ * @attr:\tReturned SEC attributes\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_sec_attr(struct fsl_mc_io\t\t*mc_io,\n+\t\t\tuint32_t\t\t\tcmd_flags,\n+\t\t\tuint16_t\t\t\ttoken,\n+\t\t\tstruct dpseci_sec_attr\t\t*attr);\n+\n+/**\n+ * struct dpseci_sec_counters - Structure representing global SEC counters and\n+ *\t\t\t\tnot per dpseci counters\n+ * @dequeued_requests:\tNumber of Requests Dequeued\n+ * @ob_enc_requests:\tNumber of Outbound Encrypt Requests\n+ * @ib_dec_requests:\tNumber of Inbound Decrypt Requests\n+ * @ob_enc_bytes:\t\tNumber of Outbound Bytes Encrypted\n+ * @ob_prot_bytes:\t\tNumber of Outbound Bytes Protected\n+ * @ib_dec_bytes:\t\tNumber of Inbound Bytes Decrypted\n+ * @ib_valid_bytes:\t\tNumber of Inbound Bytes Validated\n+ */\n+struct dpseci_sec_counters {\n+\tuint64_t\tdequeued_requests;\n+\tuint64_t\tob_enc_requests;\n+\tuint64_t\tib_dec_requests;\n+\tuint64_t\tob_enc_bytes;\n+\tuint64_t\tob_prot_bytes;\n+\tuint64_t\tib_dec_bytes;\n+\tuint64_t\tib_valid_bytes;\n+};\n+\n+/**\n+ * dpseci_get_sec_counters() - Retrieve SEC accelerator counters.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPSECI object\n+ * @counters:\tReturned SEC counters\n+ *\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_sec_counters(struct fsl_mc_io\t\t*mc_io,\n+\t\t\t uint32_t\t\t\tcmd_flags,\n+\t\t\t uint16_t\t\t\ttoken,\n+\t\t\t struct dpseci_sec_counters\t*counters);\n+\n+/**\n+ * dpseci_get_api_version() - Get Data Path SEC Interface API version\n+ * @mc_io: Pointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @major_ver:\tMajor version of data path sec API\n+ * @minor_ver:\tMinor version of data path sec API\n+ *\n+ * Return: '0' on Success; Error code otherwise.\n+ */\n+int dpseci_get_api_version(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t *major_ver,\n+\t\t\t uint16_t *minor_ver);\n+\n+#endif /* __FSL_DPSECI_H */\ndiff --git a/drivers/bus/fslmc/mc/fsl_dpseci_cmd.h b/drivers/bus/fslmc/mc/fsl_dpseci_cmd.h\nnew file mode 100644\nindex 0000000..a2fb071\n--- /dev/null\n+++ b/drivers/bus/fslmc/mc/fsl_dpseci_cmd.h\n@@ -0,0 +1,248 @@\n+/* Copyright 2013-2016 Freescale Semiconductor Inc.\n+ * Copyright (c) 2016 NXP.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef _FSL_DPSECI_CMD_H\n+#define _FSL_DPSECI_CMD_H\n+\n+/* DPSECI Version */\n+#define DPSECI_VER_MAJOR\t\t\t\t5\n+#define DPSECI_VER_MINOR\t\t\t\t0\n+\n+/* Command IDs */\n+#define DPSECI_CMDID_CLOSE ((0x800 << 4) | (0x1))\n+#define DPSECI_CMDID_OPEN ((0x809 << 4) | (0x1))\n+#define DPSECI_CMDID_CREATE ((0x909 << 4) | (0x1))\n+#define DPSECI_CMDID_DESTROY ((0x989 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_API_VERSION ((0xa09 << 4) | (0x1))\n+\n+#define DPSECI_CMDID_ENABLE ((0x002 << 4) | (0x1))\n+#define DPSECI_CMDID_DISABLE ((0x003 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_ATTR ((0x004 << 4) | (0x1))\n+#define DPSECI_CMDID_RESET ((0x005 << 4) | (0x1))\n+#define DPSECI_CMDID_IS_ENABLED ((0x006 << 4) | (0x1))\n+\n+#define DPSECI_CMDID_SET_IRQ ((0x010 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_IRQ ((0x011 << 4) | (0x1))\n+#define DPSECI_CMDID_SET_IRQ_ENABLE ((0x012 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_IRQ_ENABLE ((0x013 << 4) | (0x1))\n+#define DPSECI_CMDID_SET_IRQ_MASK ((0x014 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_IRQ_MASK ((0x015 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_IRQ_STATUS ((0x016 << 4) | (0x1))\n+#define DPSECI_CMDID_CLEAR_IRQ_STATUS ((0x017 << 4) | (0x1))\n+\n+#define DPSECI_CMDID_SET_RX_QUEUE ((0x194 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_RX_QUEUE ((0x196 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_TX_QUEUE ((0x197 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_SEC_ATTR ((0x198 << 4) | (0x1))\n+#define DPSECI_CMDID_GET_SEC_COUNTERS ((0x199 << 4) | (0x1))\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_OPEN(cmd, dpseci_id) \\\n+\tMC_CMD_OP(cmd, 0, 0, 32, int, dpseci_id)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_CREATE(cmd, cfg) \\\n+do { \\\n+\tMC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->priorities[0]);\\\n+\tMC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->priorities[1]);\\\n+\tMC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->priorities[2]);\\\n+\tMC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->priorities[3]);\\\n+\tMC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->priorities[4]);\\\n+\tMC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->priorities[5]);\\\n+\tMC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->priorities[6]);\\\n+\tMC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->priorities[7]);\\\n+\tMC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->num_tx_queues);\\\n+\tMC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->num_rx_queues);\\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_IS_ENABLED(cmd, en) \\\n+\tMC_RSP_OP(cmd, 0, 0, 1, int,\t en)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \\\n+do { \\\n+\tMC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\\\n+\tMC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\\\n+\tMC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\\\n+\tMC_CMD_OP(cmd, 2, 0, 32, int,\t irq_cfg->irq_num); \\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_GET_IRQ(cmd, irq_index) \\\n+\tMC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_IRQ(cmd, type, irq_cfg) \\\n+do { \\\n+\tMC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \\\n+\tMC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\\\n+\tMC_RSP_OP(cmd, 2, 0, 32, int,\t irq_cfg->irq_num); \\\n+\tMC_RSP_OP(cmd, 2, 32, 32, int,\t type); \\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_SET_IRQ_ENABLE(cmd, irq_index, enable_state) \\\n+do { \\\n+\tMC_CMD_OP(cmd, 0, 0, 8, uint8_t, enable_state); \\\n+\tMC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_GET_IRQ_ENABLE(cmd, irq_index) \\\n+\tMC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_IRQ_ENABLE(cmd, enable_state) \\\n+\tMC_RSP_OP(cmd, 0, 0, 8, uint8_t, enable_state)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \\\n+do { \\\n+\tMC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \\\n+\tMC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_GET_IRQ_MASK(cmd, irq_index) \\\n+\tMC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_IRQ_MASK(cmd, mask) \\\n+\tMC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \\\n+do { \\\n+\tMC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\\\n+\tMC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_IRQ_STATUS(cmd, status) \\\n+\tMC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \\\n+do { \\\n+\tMC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \\\n+\tMC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_ATTR(cmd, attr) \\\n+do { \\\n+\tMC_RSP_OP(cmd, 0, 0, 32, int,\t attr->id); \\\n+\tMC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->num_tx_queues); \\\n+\tMC_RSP_OP(cmd, 1, 8, 8, uint8_t, attr->num_rx_queues); \\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_SET_RX_QUEUE(cmd, queue, cfg) \\\n+do { \\\n+\tMC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \\\n+\tMC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority); \\\n+\tMC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue); \\\n+\tMC_CMD_OP(cmd, 0, 48, 4, enum dpseci_dest, cfg->dest_cfg.dest_type); \\\n+\tMC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \\\n+\tMC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\\\n+\tMC_CMD_OP(cmd, 2, 32, 1, int,\t\tcfg->order_preservation_en);\\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_GET_RX_QUEUE(cmd, queue) \\\n+\tMC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_RX_QUEUE(cmd, attr) \\\n+do { \\\n+\tMC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id);\\\n+\tMC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\\\n+\tMC_RSP_OP(cmd, 0, 48, 4, enum dpseci_dest, attr->dest_cfg.dest_type);\\\n+\tMC_RSP_OP(cmd, 1, 0, 8, uint64_t, attr->user_ctx);\\\n+\tMC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->fqid);\\\n+\tMC_RSP_OP(cmd, 2, 32, 1, int,\t\t attr->order_preservation_en);\\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_CMD_GET_TX_QUEUE(cmd, queue) \\\n+\tMC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_TX_QUEUE(cmd, attr) \\\n+do { \\\n+\tMC_RSP_OP(cmd, 0, 32, 32, uint32_t, attr->fqid);\\\n+\tMC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->priority);\\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_SEC_ATTR(cmd, attr) \\\n+do { \\\n+\tMC_RSP_OP(cmd, 0, 0, 16, uint16_t, attr->ip_id);\\\n+\tMC_RSP_OP(cmd, 0, 16, 8, uint8_t, attr->major_rev);\\\n+\tMC_RSP_OP(cmd, 0, 24, 8, uint8_t, attr->minor_rev);\\\n+\tMC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->era);\\\n+\tMC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->deco_num);\\\n+\tMC_RSP_OP(cmd, 1, 8, 8, uint8_t, attr->zuc_auth_acc_num);\\\n+\tMC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->zuc_enc_acc_num);\\\n+\tMC_RSP_OP(cmd, 1, 32, 8, uint8_t, attr->snow_f8_acc_num);\\\n+\tMC_RSP_OP(cmd, 1, 40, 8, uint8_t, attr->snow_f9_acc_num);\\\n+\tMC_RSP_OP(cmd, 1, 48, 8, uint8_t, attr->crc_acc_num);\\\n+\tMC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->pk_acc_num);\\\n+\tMC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->kasumi_acc_num);\\\n+\tMC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->rng_acc_num);\\\n+\tMC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->md_acc_num);\\\n+\tMC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->arc4_acc_num);\\\n+\tMC_RSP_OP(cmd, 2, 48, 8, uint8_t, attr->des_acc_num);\\\n+\tMC_RSP_OP(cmd, 2, 56, 8, uint8_t, attr->aes_acc_num);\\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_SEC_COUNTERS(cmd, counters) \\\n+do { \\\n+\tMC_RSP_OP(cmd, 0, 0, 64, uint64_t, counters->dequeued_requests);\\\n+\tMC_RSP_OP(cmd, 1, 0, 64, uint64_t, counters->ob_enc_requests);\\\n+\tMC_RSP_OP(cmd, 2, 0, 64, uint64_t, counters->ib_dec_requests);\\\n+\tMC_RSP_OP(cmd, 3, 0, 64, uint64_t, counters->ob_enc_bytes);\\\n+\tMC_RSP_OP(cmd, 4, 0, 64, uint64_t, counters->ob_prot_bytes);\\\n+\tMC_RSP_OP(cmd, 5, 0, 64, uint64_t, counters->ib_dec_bytes);\\\n+\tMC_RSP_OP(cmd, 6, 0, 64, uint64_t, counters->ib_valid_bytes);\\\n+} while (0)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define DPSECI_RSP_GET_API_VERSION(cmd, major, minor) \\\n+do { \\\n+\tMC_RSP_OP(cmd, 0, 0, 16, uint16_t, major);\\\n+\tMC_RSP_OP(cmd, 0, 16, 16, uint16_t, minor);\\\n+} while (0)\n+\n+#endif /* _FSL_DPSECI_CMD_H */\n", "prefixes": [ "dpdk-dev", "PATCHv2", "10/34" ] }