Patch Detail
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Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/18166/?format=api
{ "id": 18166, "url": "http://patches.dpdk.org/api/patches/18166/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1482180853-18823-7-git-send-email-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1482180853-18823-7-git-send-email-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1482180853-18823-7-git-send-email-hemant.agrawal@nxp.com", "date": "2016-12-19T20:53:45", "name": "[dpdk-dev,PATCHv2,06/34] bus/fslmc: introduce mc object functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d3376c19a98f307fb0ad68cfdcec0bd397734dc4", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1482180853-18823-7-git-send-email-hemant.agrawal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/18166/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/18166/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id E6451F938;\n\tMon, 19 Dec 2016 16:21:22 +0100 (CET)", "from NAM02-BL2-obe.outbound.protection.outlook.com\n\t(mail-bl2nam02on0051.outbound.protection.outlook.com [104.47.38.51])\n\tby dpdk.org (Postfix) with ESMTP id A541FF96F\n\tfor <dev@dpdk.org>; Mon, 19 Dec 2016 16:20:54 +0100 (CET)", "from BY2PR03CA072.namprd03.prod.outlook.com (10.141.249.45) by\n\tBN1PR0301MB0737.namprd03.prod.outlook.com (10.160.78.144) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.789.14; Mon, 19 Dec 2016 15:20:52 +0000", "from BL2FFO11FD046.protection.gbl (2a01:111:f400:7c09::176) by\n\tBY2PR03CA072.outlook.office365.com (2a01:111:e400:2c5d::45) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.789.14 via\n\tFrontend Transport; Mon, 19 Dec 2016 15:20:52 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBL2FFO11FD046.mail.protection.outlook.com (10.173.161.208) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.1.771.7 via Frontend Transport; Mon, 19 Dec 2016 15:20:51 +0000", "from bf-netperf1.idc ([10.232.134.28])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tuBJFKMhV029110; Mon, 19 Dec 2016 08:20:47 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com;\n\tnxp.com; \n\tdkim=none (message not signed) header.d=none;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "X-IncomingTopHeaderMarker": "OriginalChecksum:; UpperCasedChecksum:;\n\tSizeAsReceived:930; Count:10", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,\n\t<shreyansh.jain@nxp.com>, <john.mcnamara@intel.com>,\n\t<ferruh.yigit@intel.com>, <jerin.jacob@caviumnetworks.com>,\n\tCristian Sovaiala\n\t<cristian.sovaiala@nxp.com>, Hemant Agrawal <hemant.agrawal@nxp.com>", "Date": "Tue, 20 Dec 2016 02:23:45 +0530", "Message-ID": "<1482180853-18823-7-git-send-email-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1482180853-18823-1-git-send-email-hemant.agrawal@nxp.com>", "References": "<1480875447-23680-1-git-send-email-hemant.agrawal@nxp.com>\n\t<1482180853-18823-1-git-send-email-hemant.agrawal@nxp.com>", "X-IncomingHeaderCount": "10", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131266344520532709;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0; RULEID:(22001);\n\tSRVR:BN1PR0301MB0737; ", "X-Microsoft-Antispam-PRVS": "<BN1PR0301MB0737FC026B9EBBF7C4FFBFE389910@BN1PR0301MB0737.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197)(275809806118684); ", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(6095060)(601004)(2401047)(8121501046)(13018025)(13015025)(5005006)(13024025)(13023025)(13017025)(3002001)(10201501046)(6055026)(6096035)(20161123561025)(20161123559025)(20161123565025)(20161123556025)(20161123563025);\n\tSRVR:BN1PR0301MB0737; BCL:0; PCL:0; RULEID:(400006);\n\tSRVR:BN1PR0301MB0737; ", "X-Forefront-PRVS": "01613DFDC8", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Dec 2016 15:20:51.8192\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.158.2]; \n\tHelo=[az84smr01.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN1PR0301MB0737", "Subject": "[dpdk-dev] [PATCHv2 06/34] bus/fslmc: introduce mc object functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch intoduces the DPAA2 MC(Management complex Driver).\n\nThis is a minimal set of low level functions to send and\nreceive commands to the fsl-mc. It includes support for basic\nmanagement commands and commands to manipulate MC objects.\n\nThis is common to be used by various DPAA2 PMDs. e.g.net, crypto\nand other drivers.\n\nThis is a low level library also used in kernel.\n\nSigned-off-by: Cristian Sovaiala <cristian.sovaiala@nxp.com>\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n drivers/bus/fslmc/Makefile | 7 ++\n drivers/bus/fslmc/mc/fsl_mc_cmd.h | 231 ++++++++++++++++++++++++++++++++++++++\n drivers/bus/fslmc/mc/fsl_mc_sys.h | 98 ++++++++++++++++\n drivers/bus/fslmc/mc/mc_sys.c | 107 ++++++++++++++++++\n 4 files changed, 443 insertions(+)\n create mode 100644 drivers/bus/fslmc/mc/fsl_mc_cmd.h\n create mode 100644 drivers/bus/fslmc/mc/fsl_mc_sys.h\n create mode 100644 drivers/bus/fslmc/mc/mc_sys.c", "diff": "diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile\nindex be5e9ce..0cfe464 100644\n--- a/drivers/bus/fslmc/Makefile\n+++ b/drivers/bus/fslmc/Makefile\n@@ -37,6 +37,10 @@ LIB = librte_pmd_fslmcbus.a\n \n CFLAGS += -O3\n CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += \"-Wno-strict-aliasing\"\n+\n+CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc\n+CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc\n \n # versioning export map\n EXPORT_MAP := rte_pmd_fslmcbus_version.map\n@@ -44,6 +48,9 @@ EXPORT_MAP := rte_pmd_fslmcbus_version.map\n # library version\n LIBABIVER := 1\n \n+SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += \\\n+ mc/mc_sys.c\n+\n SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc_bus.c\n \n # library dependencies\ndiff --git a/drivers/bus/fslmc/mc/fsl_mc_cmd.h b/drivers/bus/fslmc/mc/fsl_mc_cmd.h\nnew file mode 100644\nindex 0000000..cbd3995\n--- /dev/null\n+++ b/drivers/bus/fslmc/mc/fsl_mc_cmd.h\n@@ -0,0 +1,231 @@\n+/* Copyright 2013-2016 Freescale Semiconductor Inc.\n+ * Copyright (c) 2016 NXP.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef __FSL_MC_CMD_H\n+#define __FSL_MC_CMD_H\n+\n+#define MC_CMD_NUM_OF_PARAMS\t7\n+\n+#define MAKE_UMASK64(_width) \\\n+\t((uint64_t)((_width) < 64 ? ((uint64_t)1 << (_width)) - 1 : \\\n+\t\t (uint64_t)-1))\n+\n+static inline uint64_t mc_enc(int lsoffset, int width, uint64_t val)\n+{\n+\treturn (uint64_t)(((uint64_t)val & MAKE_UMASK64(width)) << lsoffset);\n+}\n+\n+static inline uint64_t mc_dec(uint64_t val, int lsoffset, int width)\n+{\n+\treturn (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width));\n+}\n+\n+struct mc_command {\n+\tuint64_t header;\n+\tuint64_t params[MC_CMD_NUM_OF_PARAMS];\n+};\n+\n+/**\n+ * enum mc_cmd_status - indicates MC status at command response\n+ * @MC_CMD_STATUS_OK: Completed successfully\n+ * @MC_CMD_STATUS_READY: Ready to be processed\n+ * @MC_CMD_STATUS_AUTH_ERR: Authentication error\n+ * @MC_CMD_STATUS_NO_PRIVILEGE: No privilege\n+ * @MC_CMD_STATUS_DMA_ERR: DMA or I/O error\n+ * @MC_CMD_STATUS_CONFIG_ERR: Configuration error\n+ * @MC_CMD_STATUS_TIMEOUT: Operation timed out\n+ * @MC_CMD_STATUS_NO_RESOURCE: No resources\n+ * @MC_CMD_STATUS_NO_MEMORY: No memory available\n+ * @MC_CMD_STATUS_BUSY: Device is busy\n+ * @MC_CMD_STATUS_UNSUPPORTED_OP: Unsupported operation\n+ * @MC_CMD_STATUS_INVALID_STATE: Invalid state\n+ */\n+enum mc_cmd_status {\n+\tMC_CMD_STATUS_OK = 0x0,\n+\tMC_CMD_STATUS_READY = 0x1,\n+\tMC_CMD_STATUS_AUTH_ERR = 0x3,\n+\tMC_CMD_STATUS_NO_PRIVILEGE = 0x4,\n+\tMC_CMD_STATUS_DMA_ERR = 0x5,\n+\tMC_CMD_STATUS_CONFIG_ERR = 0x6,\n+\tMC_CMD_STATUS_TIMEOUT = 0x7,\n+\tMC_CMD_STATUS_NO_RESOURCE = 0x8,\n+\tMC_CMD_STATUS_NO_MEMORY = 0x9,\n+\tMC_CMD_STATUS_BUSY = 0xA,\n+\tMC_CMD_STATUS_UNSUPPORTED_OP = 0xB,\n+\tMC_CMD_STATUS_INVALID_STATE = 0xC\n+};\n+\n+/* MC command flags */\n+\n+/**\n+ * High priority flag\n+ */\n+#define MC_CMD_FLAG_PRI\t\t0x00008000\n+/**\n+ * Command completion flag\n+ */\n+#define MC_CMD_FLAG_INTR_DIS\t0x01000000\n+\n+/**\n+ * Command ID field offset\n+ */\n+#define MC_CMD_HDR_CMDID_O\t48\n+/**\n+ * Command ID field size\n+ */\n+#define MC_CMD_HDR_CMDID_S\t16\n+/**\n+ * Token field offset\n+ */\n+#define MC_CMD_HDR_TOKEN_O\t32\n+/**\n+ * Token field size\n+ */\n+#define MC_CMD_HDR_TOKEN_S\t16\n+/**\n+ * Status field offset\n+ */\n+#define MC_CMD_HDR_STATUS_O\t16\n+/**\n+ * Status field size\n+ */\n+#define MC_CMD_HDR_STATUS_S\t8\n+/**\n+ * Flags field offset\n+ */\n+#define MC_CMD_HDR_FLAGS_O\t0\n+/**\n+ * Flags field size\n+ */\n+#define MC_CMD_HDR_FLAGS_S\t32\n+/**\n+ * Command flags mask\n+ */\n+#define MC_CMD_HDR_FLAGS_MASK\t0xFF00FF00\n+\n+#define MC_CMD_HDR_READ_STATUS(_hdr) \\\n+\t((enum mc_cmd_status)mc_dec((_hdr), \\\n+\t\tMC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S))\n+\n+#define MC_CMD_HDR_READ_TOKEN(_hdr) \\\n+\t((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S))\n+\n+#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \\\n+\t((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg)))\n+\n+#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \\\n+\t(_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width)))\n+\n+#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \\\n+\t((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))\n+\n+#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \\\n+\t(_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width)))\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define CMD_CREATE_RSP_GET_OBJ_ID_PARAM0(cmd, object_id) \\\n+\tMC_RSP_OP(cmd, 0, 0, 32, uint32_t, object_id)\n+\n+/* cmd, param, offset, width, type, arg_name */\n+#define CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id) \\\n+\tMC_CMD_OP(cmd, 0, 0, 32, uint32_t, object_id)\n+\n+static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id,\n+\t\t\t\t\t uint32_t cmd_flags,\n+\t\t\t\t\t uint16_t token)\n+{\n+\tuint64_t hdr;\n+\n+\thdr = mc_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id);\n+\thdr |= mc_enc(MC_CMD_HDR_FLAGS_O, MC_CMD_HDR_FLAGS_S,\n+\t\t (cmd_flags & MC_CMD_HDR_FLAGS_MASK));\n+\thdr |= mc_enc(MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S, token);\n+\thdr |= mc_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S,\n+\t\t MC_CMD_STATUS_READY);\n+\n+\treturn hdr;\n+}\n+\n+/**\n+ * mc_write_command - writes a command to a Management Complex (MC) portal\n+ *\n+ * @portal: pointer to an MC portal\n+ * @cmd: pointer to a filled command\n+ */\n+static inline void mc_write_command(struct mc_command __iomem *portal,\n+\t\t\t\t struct mc_command *cmd)\n+{\n+\tint i;\n+\tuint32_t word;\n+\n+\t/* copy command parameters into the portal */\n+\tfor (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)\n+\t\tiowrite64(cmd->params[i], &portal->params[i]);\n+\n+\t/* submit the command by writing the header */\n+\tword = (uint32_t)mc_dec(cmd->header, 32, 32);\n+\tiowrite32(word, (((uint32_t *)&portal->header) + 1));\n+\n+\tword = (uint32_t)mc_dec(cmd->header, 0, 32);\n+\tiowrite32(word, (uint32_t *)&portal->header);\n+}\n+\n+/**\n+ * mc_read_response - reads the response for the last MC command from a\n+ * Management Complex (MC) portal\n+ *\n+ * @portal: pointer to an MC portal\n+ * @resp: pointer to command response buffer\n+ *\n+ * Returns MC_CMD_STATUS_OK on Success; Error code otherwise.\n+ */\n+static inline enum mc_cmd_status mc_read_response(\n+\t\t\t\t\tstruct mc_command __iomem *portal,\n+\t\t\t\t\tstruct mc_command *resp)\n+{\n+\tint i;\n+\tenum mc_cmd_status status;\n+\n+\t/* Copy command response header from MC portal: */\n+\tresp->header = ioread64(&portal->header);\n+\tstatus = MC_CMD_HDR_READ_STATUS(resp->header);\n+\tif (status != MC_CMD_STATUS_OK)\n+\t\treturn status;\n+\n+\t/* Copy command response data from MC portal: */\n+\tfor (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)\n+\t\tresp->params[i] = ioread64(&portal->params[i]);\n+\n+\treturn status;\n+}\n+\n+#endif /* __FSL_MC_CMD_H */\ndiff --git a/drivers/bus/fslmc/mc/fsl_mc_sys.h b/drivers/bus/fslmc/mc/fsl_mc_sys.h\nnew file mode 100644\nindex 0000000..d9d43e5\n--- /dev/null\n+++ b/drivers/bus/fslmc/mc/fsl_mc_sys.h\n@@ -0,0 +1,98 @@\n+/* Copyright 2013-2015 Freescale Semiconductor Inc.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#ifndef _FSL_MC_SYS_H\n+#define _FSL_MC_SYS_H\n+\n+#ifdef __linux_driver__\n+\n+#include <linux/errno.h>\n+#include <asm/io.h>\n+#include <linux/slab.h>\n+\n+struct fsl_mc_io {\n+\tvoid *regs;\n+};\n+\n+#ifndef ENOTSUP\n+#define ENOTSUP\t\t95\n+#endif\n+\n+#define ioread64(_p)\t readq(_p)\n+#define iowrite64(_v, _p) writeq(_v, _p)\n+\n+#else /* __linux_driver__ */\n+\n+#include <stdio.h>\n+#include <libio.h>\n+#include <stdint.h>\n+#include <errno.h>\n+#include <sys/uio.h>\n+#include <linux/byteorder/little_endian.h>\n+\n+#define cpu_to_le64(x) __cpu_to_le64(x)\n+#ifndef dmb\n+#define dmb() {__asm__ __volatile__(\"\" : : : \"memory\"); }\n+#endif\n+#define __iormb() dmb()\n+#define __iowmb() dmb()\n+#define __arch_getq(a) (*(volatile unsigned long *)(a))\n+#define __arch_putq(v, a) (*(volatile unsigned long *)(a) = (v))\n+#define __arch_putq32(v, a) (*(volatile unsigned int *)(a) = (v))\n+#define readq(c) \\\n+\t({ uint64_t __v = __arch_getq(c); __iormb(); __v; })\n+#define writeq(v, c) \\\n+\t({ uint64_t __v = v; __iowmb(); __arch_putq(__v, c); __v; })\n+#define writeq32(v, c) \\\n+\t({ uint32_t __v = v; __iowmb(); __arch_putq32(__v, c); __v; })\n+#define ioread64(_p)\t readq(_p)\n+#define iowrite64(_v, _p) writeq(_v, _p)\n+#define iowrite32(_v, _p) writeq32(_v, _p)\n+#define __iomem\n+\n+struct fsl_mc_io {\n+\tvoid *regs;\n+};\n+\n+#ifndef ENOTSUP\n+#define ENOTSUP\t\t95\n+#endif\n+\n+/*GPP is supposed to use MC commands with low priority*/\n+#define CMD_PRI_LOW 0 /*!< Low Priority command indication */\n+\n+struct mc_command;\n+\n+int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd);\n+\n+#endif /* __linux_driver__ */\n+\n+#endif /* _FSL_MC_SYS_H */\ndiff --git a/drivers/bus/fslmc/mc/mc_sys.c b/drivers/bus/fslmc/mc/mc_sys.c\nnew file mode 100644\nindex 0000000..c428624\n--- /dev/null\n+++ b/drivers/bus/fslmc/mc/mc_sys.c\n@@ -0,0 +1,107 @@\n+/* Copyright 2013-2015 Freescale Semiconductor Inc.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <fsl_mc_sys.h>\n+#include <fsl_mc_cmd.h>\n+\n+#include <rte_spinlock.h>\n+\n+/** User space framework uses MC Portal in shared mode. Following change\n+ * introduces lock in MC FLIB\n+ */\n+\n+/**\n+ * A static spinlock initializer.\n+ */\n+static rte_spinlock_t mc_portal_lock = RTE_SPINLOCK_INITIALIZER;\n+\n+static int mc_status_to_error(enum mc_cmd_status status)\n+{\n+\tswitch (status) {\n+\tcase MC_CMD_STATUS_OK:\n+\t\treturn 0;\n+\tcase MC_CMD_STATUS_AUTH_ERR:\n+\t\treturn -EACCES; /* Token error */\n+\tcase MC_CMD_STATUS_NO_PRIVILEGE:\n+\t\treturn -EPERM; /* Permission denied */\n+\tcase MC_CMD_STATUS_DMA_ERR:\n+\t\treturn -EIO; /* Input/Output error */\n+\tcase MC_CMD_STATUS_CONFIG_ERR:\n+\t\treturn -EINVAL; /* Device not configured */\n+\tcase MC_CMD_STATUS_TIMEOUT:\n+\t\treturn -ETIMEDOUT; /* Operation timed out */\n+\tcase MC_CMD_STATUS_NO_RESOURCE:\n+\t\treturn -ENAVAIL; /* Resource temporarily unavailable */\n+\tcase MC_CMD_STATUS_NO_MEMORY:\n+\t\treturn -ENOMEM; /* Cannot allocate memory */\n+\tcase MC_CMD_STATUS_BUSY:\n+\t\treturn -EBUSY; /* Device busy */\n+\tcase MC_CMD_STATUS_UNSUPPORTED_OP:\n+\t\treturn -ENOTSUP; /* Operation not supported by device */\n+\tcase MC_CMD_STATUS_INVALID_STATE:\n+\t\treturn -ENODEV; /* Invalid device state */\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/* Not expected to reach here */\n+\treturn -EINVAL;\n+}\n+\n+int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd)\n+{\n+\tenum mc_cmd_status status;\n+\n+\tif (!mc_io || !mc_io->regs)\n+\t\treturn -EACCES;\n+\n+\t/* --- Call lock function here in case portal is shared --- */\n+\trte_spinlock_lock(&mc_portal_lock);\n+\n+\tmc_write_command(mc_io->regs, cmd);\n+\n+\t/* Spin until status changes */\n+\tdo {\n+\t\tstatus = MC_CMD_HDR_READ_STATUS(ioread64(mc_io->regs));\n+\n+\t\t/* --- Call wait function here to prevent blocking ---\n+\t\t * Change the loop condition accordingly to exit on timeout.\n+\t\t */\n+\t} while (status == MC_CMD_STATUS_READY);\n+\n+\t/* Read the response back into the command buffer */\n+\tmc_read_response(mc_io->regs, cmd);\n+\n+\t/* --- Call unlock function here in case portal is shared --- */\n+\trte_spinlock_unlock(&mc_portal_lock);\n+\n+\treturn mc_status_to_error(status);\n+}\n", "prefixes": [ "dpdk-dev", "PATCHv2", "06/34" ] }