Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/17677/?format=api
{ "id": 17677, "url": "http://patches.dpdk.org/api/patches/17677/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20161205125540.6419-7-akhil.goyal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20161205125540.6419-7-akhil.goyal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20161205125540.6419-7-akhil.goyal@nxp.com", "date": "2016-12-05T12:55:38", "name": "[dpdk-dev,6/8] crypto/dpaa2_sec: add sec procssing functionality", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "97359f4b46da1aa448daf816ea0bee07aa60db0a", "submitter": { "id": 517, "url": "http://patches.dpdk.org/api/people/517/?format=api", "name": "Akhil Goyal", "email": "akhil.goyal@nxp.com" }, "delegate": { "id": 22, "url": "http://patches.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20161205125540.6419-7-akhil.goyal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/17677/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/17677/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 861AAFA4C;\n\tMon, 5 Dec 2016 08:29:45 +0100 (CET)", "from NAM02-CY1-obe.outbound.protection.outlook.com\n\t(mail-cys01nam02on0087.outbound.protection.outlook.com\n\t[104.47.37.87]) by dpdk.org (Postfix) with ESMTP id D2444FA3C\n\tfor <dev@dpdk.org>; Mon, 5 Dec 2016 08:29:04 +0100 (CET)", "from CY1PR03CA0002.namprd03.prod.outlook.com (10.174.128.12) by\n\tMWHPR03MB2479.namprd03.prod.outlook.com (10.169.200.149) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.761.9; Mon, 5 Dec 2016 07:29:03 +0000", "from BY2FFO11FD017.protection.gbl (2a01:111:f400:7c0c::105) by\n\tCY1PR03CA0002.outlook.office365.com (2603:10b6:600::12) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.761.9 via Frontend Transport; Mon, 5 Dec 2016 07:29:02 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBY2FFO11FD017.mail.protection.outlook.com (10.1.14.105) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.734.4\n\tvia Frontend Transport; Mon, 5 Dec 2016 07:29:02 +0000", "from netperf2.ap.freescale.net ([10.232.133.164])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tuB57SdmY016006; Mon, 5 Dec 2016 00:28:59 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com;\n\tnxp.com; \n\tdkim=none (message not signed) header.d=none;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "X-IncomingTopHeaderMarker": "OriginalChecksum:; UpperCasedChecksum:;\n\tSizeAsReceived:713; Count:10", "From": "Akhil Goyal <akhil.goyal@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <eclan.doherty@intel.com>,\n\t<pablo.de.lara.guarch@intel.com>, <hemant.agrawal@nxp.com>, Akhil Goyal\n\t<akhil.goyal@nxp.com>", "Date": "Mon, 5 Dec 2016 18:25:38 +0530", "Message-ID": "<20161205125540.6419-7-akhil.goyal@nxp.com>", "X-Mailer": "git-send-email 2.9.3", "In-Reply-To": "<20161205125540.6419-1-akhil.goyal@nxp.com>", "References": "<20161205125540.6419-1-akhil.goyal@nxp.com>", "X-IncomingHeaderCount": "10", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131253965428627852;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(7916002)(2980300002)(1110001)(1109001)(336004)(339900001)(189002)(199003)(2950100002)(92566002)(6916009)(110136003)(6666003)(356003)(8666005)(36756003)(104016004)(5660300001)(77096006)(626004)(97736004)(85426001)(39840400001)(39860400001)(50226002)(7846002)(305945005)(33646002)(5003940100001)(575784001)(50466002)(50986999)(48376002)(4326007)(81156014)(2906002)(81166006)(189998001)(1076002)(8936002)(86362001)(47776003)(2351001)(39450400002)(39400400001)(39850400001)(38730400001)(39410400001)(39380400001)(106466001)(68736007)(105606002)(76176999)(5890100001)(8676002)(7059030)(569005);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR03MB2479;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; ", "X-Microsoft-Exchange-Diagnostics": [ "1; BY2FFO11FD017;\n\t1:l6npL12ukKBTYhuMMDsNK2SC8acPUm6vFxgO3MyHtkWx5pW5SLwM20oebyh6gd78mTjLt97jQ146C1m5eH4uqOu8PC3KR8eHLNIr5zXCgoVyPc8r5IrWWLER1IxyDVY4L6rbsypP8H+EwDAxUbfvAkLOVqL7z+tE1glTmYCPnAfHkelHGZXv3zrKtJoAZtIEHHAvJt3cUPFqQvaca06D44VAl6GroEdrgy1J4wDd33sxk76WrTcYpjz5WAcWRwM2Nor8qg9JJdXWSmaAsVQux9UQXVINbd19CvCxvAbu1mf/DaePWhdP2rUUZf1RCGBqWt2Qdq1QdSl9lbxRrqVINoqnDFvoaL7+QOS9Nxj/j7SZ0oWnQgK8QeyaWHEU7p1O/PVMa1aFyevHlkRi55PjTpbR8wsmG1tmT4nqvY0R+o7tQzs4hhF8BeA/4NyV+0KqwgRAHU7i5NZGfrUH12d4KvZJlIWNuq12lh2WwMrC2ZTF0l/2rwA9f291aC887RWL2W1VNOLuFN1Igzad8RFqSoRQh1Unj9vUICVX0TT58VODL/am3AwNlacvz9bhPARnwYD9BsKQbiR8dsrJfLAI6fXtE4CbX0ekzo0+eQoYaYFmnsTT38esyUVcASnX63VKM1PhEIlKFVNnGqZBwNS6LClt3V6DDpl9/5puyJ5XrJSGVJ9dOtMYvnNhaXR8Mhp4iN5NK65s6tueyIO2ru876+ByiYMUs+MwfM5OYfsr44EH9IfZMwee1ywABGBUWJ9lhYvIoDQTPn3c9pHlu1rYSw==", "1; MWHPR03MB2479;\n\t3:vYcov6TDgnRMKSrgdXa5Y99st25j+N5R2Io60Kdj4Zo6xfnpjAkzy6xbYUJLUseuhdd74TOtxjmDwxGnzkb0LBQ32009qQ9nfiQ58qEo2AyM0b3MUBxL9FF06c9hZ422UNGH4+BWVkjGmd8Uh+Z4fBag59jWcHHO3GlOZOLoMUF4JiTDIjjrYJQs31BPaqLV5wZVDsY4vmdcJcQXsufi3rhHuzQvYHnCPYvpdI8qqx3xn3JgxTJXMZfK3FchiUH5HdCUz3iBJuiZhYrc9VxYvgIMonw2wPjygD4uBUjIpE3CO4O1d4kPJFLZuXO+duuNOFbfJn4gHFiPWjtr3dRbdsUKUhBiw6OPQu1FHRv4vrBDgpbjMXxGH/yX65PKulvH", "1; MWHPR03MB2479;\n\t25:M+QLMxfhfpFtigU6SLN7dI2jjyk7466gDEq0I2D0CFmyHUIS5jj5VgbUu187w0dPlxa23dcY3mVvvqmIqzR1aZER4Tx3UbCbT41ytCaEX+5sQYWwSTbzH9g5o2qe8NCxDCtnYF63cBOd0Kb42br1M6JxqU0K/2ST/OnkbbYYWxQOuuvRLrMGQ2TTR7BPkoZ6kdF5MtNt3JDTdN+M11tNsNFlWsSYPg+t1iJVocRlOLixWl6DR5Wgv+RUg0Q8UjawamIBwpzdUuFCjvwAxMbtjd6PVNQLYn/BQoRVuxtzoJP52bNdQI3gzAYYE3xOS3LsdTADWf0X3pZqK4dg0ZOCsArSetrF1+tS0Helg9DHr61iNzdWy0+6MI2iZ3Ro9FyQJKjldQbULHICibRHGQ+9Aea325Fa50aaS7CVG8hQWRmuGex+Js5Ft9M8Dfyb9FxyxelMGqppHZlD0NHvx+tTlTTm6rmVgSJQkUd5Lpj1t07EJMO0LJnImFK4q3K2L0BJJ4J3M7fJmrw7eeAna/kIl08sYJtxJG48jYHTKtzc+WaA0txI6yaK19uQOOogB8LZugp1vRq3dzmo5UCcLuF3ogFs/HKT1f+ju6rydd1hQDtBpATnoFZiNXkpu5bb/gBAKggi7VDLLvPbbnFo3pEE9kPOoyYUXuiCkpKGbNWP3RHw1y3G8njXlFItDw1le/cDgH4HGNgdm2czFKeal8yoKU4AT+1q6U+S9n8QFdPkWEvT5K92dm2OmQU0TE3Pfe3IvGFlR4+uNQt/PgV4WKUQkIfxQBo047N/eiRt0l8yfu8=", "1; MWHPR03MB2479;\n\t31:77hyRuo5o9+SnOL5Xj6hToZ9MATQnlVuQ/fF/garqWLz3RRRyty56lNIwrnUJ8X4XYH95InX0ykd8+vgY++Q1MvCNVdAbu5Luf4ZRzwAAcXc+/Mcgi0s7NNwZD8D/RQLMeCdfawgH6XuQWZj5vPpl5ra6ntyGJH/gYFlDNAN/BzJnhPKueUUU9XES/395hwdyBLc9vZD3V6g7RAUL6OFJXZjdzxsGbIwcVOPDtL/tw77HUwrTO8wHaPufKvgtkWy9cd/xqsGQWiPQypkdIYoaV8lc4N6Dfrc/piKOVpRrNc=", "1; MWHPR03MB2479;\n\t4:jHis7K1Ar6aBjrXCO4N395VacsM4VfWgnXf7WuQI1fRsSaXmYQa6wNKkxSOBejfczspjJEH8zmb7DDD4C4izr6zCFIScBD/o6aj3bqJGl5lFnqrZUqJxjOyVCBn2ztZljPUIo8Mm5BH0DSaOl0XCXjTn6ZZoDR/0w/bvWnnUYmEOJV7k67Z4mRxTJOUrJw9JeKuOL8nbNmA2hWM2bfxiavA9rVLgwalpSqkOoYVvelDq6gw3bZmLtcNLmvzVU1ZlL+wfzlDTkApX1P7Ot5fKNdlzNS82ud+ovNs4O7pJsfku5oYxwGnvjFhtCXWuqh4zBN2yqRQ5hTvSz5tQm+pDqtqNjUj7qrXOzR6H2hOQY4FUPifkAb1O6bZjcjfo1KVenE88uV8GYyxfluGfLBlDF5Gh3oxuXA9JPquhQHktq94TzZVSVnq/oQOur2wiKQ1bLT1MyKUjdCSdRzlw7guNfK7m/BjzDbkdclsrVl6FdG6X2C11qpdeb7vkk8g501y9CuP6Tc3yMaxEwPudZDaGBgai8fjkgJtjVkbe6mpBAoYnHzW5f+G9Ln/v4CggBbfVe7DaJyDmAO14E6X5c4UD26gdX49yAmXzrXDYwssy/1552gjoO8uhldzCNpYl1bftwrwa22EMIANXVo+uFpj5rJMerUH3wo5pPYxyBF57uO0atmCIruzZEc64mnC3SAkloodDH+y9o/P/mXCApJ5c9AOKy05e/CglwKvrjP1KWPp+ggrIZ7UzPyWMKlL4QXvzNaO0ebmxVCONUSr2HiGMMA==", "=?us-ascii?Q?1; MWHPR03MB2479;\n\t23:i9Mhnzwml4Cs8RcLpJkzOZpOREpS5M6hGawpFLTxR?=\n\t=?us-ascii?Q?t0F6BUK74Qe9KpWBwW3E+fX5kQXkB069wAQdjLW0izuRVkMMQJ1Ij50bgiNx?=\n\t=?us-ascii?Q?ZccSBN9oMiAKXngaxBdQb5Fiunr+4HJPnVTwYkh23XB/80yJMTZCDsISbJSy?=\n\t=?us-ascii?Q?CR72eKsAWeMXJUCTc6lSngifjayuKYSSIUCFulbkoJU8p8QsVQKbqBa+AhmD?=\n\t=?us-ascii?Q?qhyoflkqgL4X+Fnjuy+VciCKADjWLOnQRKoil/4WVSipO8Qp/r380lpuQTCn?=\n\t=?us-ascii?Q?CUCbrOZLI2TBj9Vwo/2rxw4ugxaBYCpGfprsaJDkZhaoXw0Cxr51sbjg+1jf?=\n\t=?us-ascii?Q?77UcvWTn6jtup10KlCBDtKE0yhtda1WDWIbxmFDYhFDbjHj8HY13PvYXElO1?=\n\t=?us-ascii?Q?EuSn0AahUu8qhGnZkY5YVyJic5pMkvDu+7YEG2TBMELR7ZFmFCqxlOfkOhNb?=\n\t=?us-ascii?Q?uok+OKwsXLeJW5aNx4hZBDQ4wMzLcU9XjL7aH+m2MhOmie4uCI/mDOgqWZ7G?=\n\t=?us-ascii?Q?OhrBWP+FT8tRU1/4RpVVnd5fRNg3uh7yXQ60lkbvyIkckDeu5tHOPudQRFIU?=\n\t=?us-ascii?Q?X6AKvYJMB0bNbJuQTlBw0ED8DWX34HNRdNovGeKYLN8BwCfSMlmggwK0KUNp?=\n\t=?us-ascii?Q?fN7SXbgGDe7+IIyWnSbmGzExzvDH8Wy5vAS/KmfPrQzR2N2FbSrjfeHHmJWE?=\n\t=?us-ascii?Q?6pRduCajFzv0fpbCPvU1XDsgHsUm3OSdML8hzHCLJ/AAazdFgSf6T1ntOFya?=\n\t=?us-ascii?Q?3WuMQfAIAFnxAzNZIu8CiTulyAaQdeAFIAABz+OjdsFrkgymtS3Ra9UkrwrM?=\n\t=?us-ascii?Q?URT6oxm6NT+Z2H7uQ0WWY6who8R8dt9Cybxdl/9H8qZCoanGRWdSNQPHUEXE?=\n\t=?us-ascii?Q?sKpcnABnxCunIf/YgkkTwlnWFtJIlWNp1f4c4Vfz+Hcx0T1jkf5he8ojwFb/?=\n\t=?us-ascii?Q?OFsdXbCsUeCqO762ntLod2ylRwbl7N5VZATNsaNmVr1uhPPhw/oJ+DFxO8fm?=\n\t=?us-ascii?Q?aHJxmnx8lc03WWPHsHSeU25thfHN01gWoaTtgN4tcIlNC/w13GLIIUr4WMic?=\n\t=?us-ascii?Q?j/LZsoCoK45zvniOXZdMf0qciurILx/nQO82qAIfX8p7lhSVHz1LybXCTvtH?=\n\t=?us-ascii?Q?bZqoAKQJ9gV6aYI1QhE3fdYtBC4xH2CaOyWhgPEETA8LTGT/P5nzWf5rGkuJ?=\n\t=?us-ascii?Q?eC+S8yz5wI8eb/ZwsrnZD9UR703S71gXgekVCM6BUzkkjsbLdjHjnHqaKnLu?=\n\t=?us-ascii?Q?FLNzN4tBQirhGv0OD6aOBpONaRHm7zXAamvWtlgbGPJCaYB/1kgBHfyQSM52?=\n\t=?us-ascii?Q?KBhPGQWOpez81AiYaonajwAL5D+LxH8PLhm5h+RpiEdUqeoAknMoZhi87Zgn?=\n\t=?us-ascii?Q?7bmci9XJoXX/V9kL+q3rM5bUj7ikMJCHs2GV2z5DV1aXuw2?=", "1; MWHPR03MB2479;\n\t6:zM2Grai6etPPeRHB1ikTKEsoo6URN1aA8d30k3pXVc+y47ECdf0/e6MkW85PvgUL6oP78HDsTcJc0/aIQBJsS7acol1YA/RAE+cKxApCEHImuXFDwpIQ6QChw+f7IIiNrxTpeUml/aIDkByII0XNLfV9ryVB03e+mB+cLC3lVZwTD7zeoVXFtzFxA3xhdBGU8zOE89KHkSIQyXfbJMqH+ZyGgcz5RvwaBgwzub5r3b/DxYBwvL8KPswRJtvjHgZHM8gPhhqhJW+zBZ5geKWySVHiD2hIz2U5rXRhg95znJHFVjwFti7MNSj2qpHU+xqep26AJHTkP7ahQbcQQfSlB7bwayYrFcHVHUUgUUbhnor6Ttd1mZdnRnwbSN3/881vvbLVU+PtJc5VtgXvUYSFMBrbww9sF8/hFVtsgvVu/fZJfhQ6dOJit6Jd/224HS2u;\n\t5:oIciNHvrc8TxeBpdR2mNcyJUsUWkcLNJivu2Vg8xvbJXEbESmGj/pwZTZNxH/tcTYeVAK2/IvKJFO9eT1UUYz0M1UqDWabW82PLrHhayLLUc/x6xkg9i+mOuxbRSe5qOuHWTCCGltd2q+0bOjVa19jmldEH00Liywi/NxkVW2zOPLdLctT5HxyfgYF7IiL/v;\n\t24:PPR0HNuE74e/26Yxj4E/HAKdZwGTT0KIOtvi5IRi6uAjeqVkpMB68TrQgfE3n4t6mCvl6iaEKFJc+MmyXnQPCQZR2xsyejMUZIIbsceNsJo=", "1; MWHPR03MB2479;\n\t7:yTpoEvZrlA5FwlOLvjme0TWibAVMpGtTmGDm3FmvsW6M+vDafVfMLSwoDX6p2jGbOfEPKQIGYPo819ad3QWu/VFscaftJSLnwXMpXqIv1JO56/5EIfjuzTVHDyEj7ZiCuD7/Zn3g1vm/ZScdm35/tSNP3XRLPIv0EX8Xde1RX2mLnFNSAKWjh5ycJRMRrJHksDCJ4mxhDPK4BMGu+yWDaAjqGDlxx+8Yf/fZ0NQIt2bMdsz6GxM/iD2BPol4pVEanew4o1KVD8z0B9HgGc7YaFgTDax9Dyf0BHAUZ5Fhog9W6qMZZT6aW+QPZg0jyyeNQ68NyOuVVkR+Ip8Wg51y74ciGdjZnd/GGP+BdyHPEuJoycfIzBdVPJoJXU9kIsdx2zrLHyj5E5h1dK5rtSiBbmEjQtrpwS5Zarsk1fEk5Q7lX4mtM4ls7CgJ3TJUFIqQiUEUNImSWGdyYYupAolxcw==" ], "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MS-Office365-Filtering-Correlation-Id": "a5d993d0-3856-4ce8-b82b-08d41ce06330", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0; RULEID:(22001);\n\tSRVR:MWHPR03MB2479; ", "X-Microsoft-Antispam-PRVS": "<MWHPR03MB2479D6A06FA09DEA1000418BE6830@MWHPR03MB2479.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197)(275809806118684); ", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(6095060)(601004)(2401047)(13024025)(13023025)(13018025)(13017025)(13015025)(5005006)(8121501046)(3002001)(10201501046)(6055026)(6096035)(20161123565025)(20161123563025)(20161123556025)(20161123561025)(20161123559025);\n\tSRVR:MWHPR03MB2479; BCL:0; PCL:0; RULEID:(400006); SRVR:MWHPR03MB2479;", "X-Forefront-PRVS": "0147E151B5", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Dec 2016 07:29:02.6599\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR03MB2479", "Subject": "[dpdk-dev] [PATCH 6/8] crypto/dpaa2_sec: add sec procssing\n\tfunctionality", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>\nReviewed-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n config/defconfig_arm64-dpaa2-linuxapp-gcc | 6 +\n drivers/crypto/dpaa2_sec/Makefile | 1 -\n drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 1337 +++++++++++++++++++++++++++\n drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 516 +++++++++++\n drivers/net/dpaa2/base/dpaa2_hw_pvt.h | 25 +\n 5 files changed, 1884 insertions(+), 1 deletion(-)\n create mode 100644 drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h", "diff": "diff --git a/config/defconfig_arm64-dpaa2-linuxapp-gcc b/config/defconfig_arm64-dpaa2-linuxapp-gcc\nindex 5338010..5a79374 100644\n--- a/config/defconfig_arm64-dpaa2-linuxapp-gcc\n+++ b/config/defconfig_arm64-dpaa2-linuxapp-gcc\n@@ -59,3 +59,9 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y\n CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_INIT=n\n CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_DRIVER=n\n CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_RX=n\n+\n+#\n+# Number of sessions to create in the session memory pool\n+# on a single DPAA2 SEC device.\n+#\n+CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048\ndiff --git a/drivers/crypto/dpaa2_sec/Makefile b/drivers/crypto/dpaa2_sec/Makefile\nindex 2cb0611..f8da122 100644\n--- a/drivers/crypto/dpaa2_sec/Makefile\n+++ b/drivers/crypto/dpaa2_sec/Makefile\n@@ -45,7 +45,6 @@ CFLAGS += -O3\n CFLAGS += $(WERROR_FLAGS)\n endif\n CFLAGS += -D _GNU_SOURCE\n-CFLAGS +=-Wno-unused-function\n \n CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/\n CFLAGS += -I$(RTE_SDK)/drivers/common/dpaa2/mc\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\nindex 83b9b61..f249e48 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n@@ -48,12 +48,1322 @@\n #include <fsl_dpseci.h>\n \n #include <base/dpaa2_hw_pvt.h>\n+#include <base/dpaa2_hw_dpbp.h>\n+#include <base/dpaa2_hw_dpio.h>\n+\n+#include \"dpaa2_sec_priv.h\"\n #include \"dpaa2_sec_logs.h\"\n+\n+/* RTA header files */\n+#include <flib/desc/ipsec.h>\n+#include <flib/desc/algo.h>\n+\n #define FSL_VENDOR_ID 0x1957\n #define FSL_DEVICE_ID 0x410\n #define FSL_SUBSYSTEM_SEC 1\n #define FSL_MC_DPSECI_DEVID 3\n \n+#define NO_PREFETCH 0\n+#define TDES_CBC_IV_LEN 8\n+#define AES_CBC_IV_LEN 16\n+enum rta_sec_era rta_sec_era = RTA_SEC_ERA_8;\n+extern struct dpaa2_bp_info bpid_info[MAX_BPID];\n+\n+static inline void print_fd(const struct qbman_fd *fd)\n+{\n+\tprintf(\"addr_lo: %u\\n\", fd->simple.addr_lo);\n+\tprintf(\"addr_hi: %u\\n\", fd->simple.addr_hi);\n+\tprintf(\"len: %u\\n\", fd->simple.len);\n+\tprintf(\"bpid: %u\\n\", DPAA2_GET_FD_BPID(fd));\n+\tprintf(\"fi_bpid_off: %u\\n\", fd->simple.bpid_offset);\n+\tprintf(\"frc: %u\\n\", fd->simple.frc);\n+\tprintf(\"ctrl: %u\\n\", fd->simple.ctrl);\n+\tprintf(\"flc_lo: %u\\n\", fd->simple.flc_lo);\n+\tprintf(\"flc_hi: %u\\n\\n\", fd->simple.flc_hi);\n+}\n+\n+static inline void print_fle(const struct qbman_fle *fle)\n+{\n+\tprintf(\"addr_lo: %u\\n\", fle->addr_lo);\n+\tprintf(\"addr_hi: %u\\n\", fle->addr_hi);\n+\tprintf(\"len: %u\\n\", fle->length);\n+\tprintf(\"fi_bpid_off: %u\\n\", fle->fin_bpid_offset);\n+\tprintf(\"frc: %u\\n\", fle->frc);\n+}\n+\n+static inline int build_authenc_fd(dpaa2_sec_session *sess,\n+\t\t\t\t struct rte_crypto_op *op,\n+\t\tstruct qbman_fd *fd, uint16_t bpid)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\tstruct ctxt_priv *priv = sess->ctxt;\n+\tstruct qbman_fle *fle, *sge;\n+\tstruct sec_flow_context *flc;\n+\tuint32_t auth_only_len = sym_op->auth.data.length -\n+\t\t\t\tsym_op->cipher.data.length;\n+\tint icv_len = sym_op->auth.digest.length;\n+\tuint8_t *old_icv;\n+\tuint32_t mem_len = (7 * sizeof(struct qbman_fle)) + icv_len;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* TODO we are using the first FLE entry to store Mbuf.\n+\t Currently we donot know which FLE has the mbuf stored.\n+\t So while retreiving we can go back 1 FLE from the FD -ADDR\n+\t to get the MBUF Addr from the previous FLE.\n+\t We can have a better approach to use the inline Mbuf*/\n+\t/* todo - we can use some mempool to avoid malloc here */\n+\tfle = rte_zmalloc(NULL, mem_len, RTE_CACHE_LINE_SIZE);\n+\tif (!fle) {\n+\t\tRTE_LOG(ERR, PMD, \"Memory alloc failed for SGE\\n\");\n+\t\treturn -1;\n+\t}\n+\tDPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));\n+\tfle = fle + 1;\n+\tsge = fle + 2;\n+\tif (likely(bpid < MAX_BPID)) {\n+\t\tDPAA2_SET_FD_BPID(fd, bpid);\n+\t\tDPAA2_SET_FLE_BPID(fle, bpid);\n+\t\tDPAA2_SET_FLE_BPID(fle + 1, bpid);\n+\t\tDPAA2_SET_FLE_BPID(sge, bpid);\n+\t\tDPAA2_SET_FLE_BPID(sge + 1, bpid);\n+\t\tDPAA2_SET_FLE_BPID(sge + 2, bpid);\n+\t\tDPAA2_SET_FLE_BPID(sge + 3, bpid);\n+\t} else {\n+\t\tDPAA2_SET_FD_IVP(fd);\n+\t\tDPAA2_SET_FLE_IVP(fle);\n+\t\tDPAA2_SET_FLE_IVP((fle + 1));\n+\t\tDPAA2_SET_FLE_IVP(sge);\n+\t\tDPAA2_SET_FLE_IVP((sge + 1));\n+\t\tDPAA2_SET_FLE_IVP((sge + 2));\n+\t\tDPAA2_SET_FLE_IVP((sge + 3));\n+\t}\n+\n+\t/* Save the shared descriptor */\n+\tflc = &priv->flc_desc[0].flc;\n+\t/* Configure FD as a FRAME LIST */\n+\tDPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle));\n+\tDPAA2_SET_FD_COMPOUND_FMT(fd);\n+\tDPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));\n+\n+\tPMD_TX_LOG(DEBUG, \"auth_off: 0x%x/length %d, digest-len=%d\\n\"\n+\t\t \"cipher_off: 0x%x/length %d, iv-len=%d data_off: 0x%x\\n\",\n+\t\t sym_op->auth.data.offset,\n+\t\t sym_op->auth.data.length,\n+\t\t sym_op->auth.digest.length,\n+\t\t sym_op->cipher.data.offset,\n+\t\t sym_op->cipher.data.length,\n+\t\t sym_op->cipher.iv.length,\n+\t\t sym_op->m_src->data_off);\n+\n+\t/* Configure Output FLE with Scatter/Gather Entry */\n+\tDPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge));\n+\tif (auth_only_len)\n+\t\tDPAA2_SET_FLE_INTERNAL_JD(fle, auth_only_len);\n+\tfle->length = (sess->dir == DIR_ENC) ?\n+\t\t(sym_op->cipher.data.length + icv_len) : sym_op->cipher.data.length;\n+\n+\tDPAA2_SET_FLE_SG_EXT(fle);\n+\n+\t/* Configure Output SGE for Encap/Decap */\n+\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n+\tDPAA2_SET_FLE_OFFSET(sge, sym_op->cipher.data.offset + sym_op->m_src->data_off);\n+\tsge->length = sym_op->cipher.data.length;\n+\n+\tif (sess->dir == DIR_ENC) {\n+\t\tsge++;\n+\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(sym_op->auth.digest.data));\n+\t\tsge->length = sym_op->auth.digest.length;\n+\t\tDPAA2_SET_FD_LEN(fd, (sym_op->auth.data.length + sym_op->cipher.iv.length));\n+\t}\n+\tDPAA2_SET_FLE_FIN(sge);\n+\n+\tsge++;\n+\tfle++;\n+\n+\t/* Configure Input FLE with Scatter/Gather Entry */\n+\tDPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge));\n+\tDPAA2_SET_FLE_SG_EXT(fle);\n+\tDPAA2_SET_FLE_FIN(fle);\n+\tfle->length = (sess->dir == DIR_ENC) ?\n+\t\t\t(sym_op->auth.data.length + sym_op->cipher.iv.length) :\n+\t\t\t(sym_op->auth.data.length + sym_op->cipher.iv.length +\n+\t\t\t sym_op->auth.digest.length);\n+\n+\t/* Configure Input SGE for Encap/Decap */\n+\tDPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(sym_op->cipher.iv.data));\n+\tsge->length = sym_op->cipher.iv.length;\n+\tsge++;\n+\n+\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n+\tDPAA2_SET_FLE_OFFSET(sge, sym_op->auth.data.offset + sym_op->m_src->data_off);\n+\tsge->length = sym_op->auth.data.length;\n+\tif (sess->dir == DIR_DEC) {\n+\t\tsge++;\n+\t\told_icv = (uint8_t *)(sge + 1);\n+\t\tmemcpy(old_icv,\tsym_op->auth.digest.data, sym_op->auth.digest.length);\n+\t\tmemset(sym_op->auth.digest.data, 0, sym_op->auth.digest.length);\n+\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(old_icv));\n+\t\tsge->length = sym_op->auth.digest.length;\n+\t\tDPAA2_SET_FD_LEN(fd, (sym_op->auth.data.length +\n+\t\t\tsym_op->auth.digest.length + sym_op->cipher.iv.length));\n+\t}\n+\tDPAA2_SET_FLE_FIN(sge);\n+\tif (auth_only_len) {\n+\t\tDPAA2_SET_FLE_INTERNAL_JD(fle, auth_only_len);\n+\t\tDPAA2_SET_FD_INTERNAL_JD(fd, auth_only_len);\n+\t}\n+\treturn 0;\n+}\n+\n+static inline int build_auth_fd(\n+\t\tdpaa2_sec_session *sess,\n+\t\tstruct rte_crypto_op *op,\n+\t\tstruct qbman_fd *fd,\n+\t\tuint16_t bpid)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\tstruct qbman_fle *fle, *sge;\n+\tuint32_t mem_len = (sess->dir == DIR_ENC) ? (3 * sizeof(struct qbman_fle)) :\n+\t\t\t(5 * sizeof(struct qbman_fle) + sym_op->auth.digest.length);\n+\tstruct sec_flow_context *flc;\n+\tstruct ctxt_priv *priv = sess->ctxt;\n+\tuint8_t *old_digest;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tfle = rte_zmalloc(NULL, mem_len, RTE_CACHE_LINE_SIZE);\n+\tif (!fle) {\n+\t\tRTE_LOG(ERR, PMD, \"Memory alloc failed for FLE\\n\");\n+\t\treturn -1;\n+\t}\n+\t/* TODO we are using the first FLE entry to store Mbuf.\n+\t Currently we donot know which FLE has the mbuf stored.\n+\t So while retreiving we can go back 1 FLE from the FD -ADDR\n+\t to get the MBUF Addr from the previous FLE.\n+\t We can have a better approach to use the inline Mbuf*/\n+\tDPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));\n+\tfle = fle + 1;\n+\n+\tif (likely(bpid < MAX_BPID)) {\n+\t\tDPAA2_SET_FD_BPID(fd, bpid);\n+\t\tDPAA2_SET_FLE_BPID(fle, bpid);\n+\t\tDPAA2_SET_FLE_BPID(fle + 1, bpid);\n+\t} else {\n+\t\tDPAA2_SET_FD_IVP(fd);\n+\t\tDPAA2_SET_FLE_IVP(fle);\n+\t\tDPAA2_SET_FLE_IVP((fle + 1));\n+\t}\n+\tflc = &priv->flc_desc[DESC_INITFINAL].flc;\n+\tDPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));\n+\n+\tDPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sym_op->auth.digest.data));\n+\tfle->length = sym_op->auth.digest.length;\n+\n+\tDPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle));\n+\tDPAA2_SET_FD_COMPOUND_FMT(fd);\n+\tfle++;\n+\n+\tif (sess->dir == DIR_ENC) {\n+\t\tDPAA2_SET_FLE_ADDR(fle, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n+\t\tDPAA2_SET_FLE_OFFSET(fle, sym_op->auth.data.offset + sym_op->m_src->data_off);\n+\t\tDPAA2_SET_FD_LEN(fd, sym_op->auth.data.length);\n+\t\tfle->length = sym_op->auth.data.length;\n+\t} else {\n+\t\tsge = fle + 2;\n+\t\tDPAA2_SET_FLE_SG_EXT(fle);\n+\t\tDPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge));\n+\n+\t\tif (likely(bpid < MAX_BPID)) {\n+\t\t\tDPAA2_SET_FLE_BPID(sge, bpid);\n+\t\t\tDPAA2_SET_FLE_BPID(sge + 1, bpid);\n+\t\t} else {\n+\t\t\tDPAA2_SET_FLE_IVP(sge);\n+\t\t\tDPAA2_SET_FLE_IVP((sge + 1));\n+\t\t}\n+\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n+\t\tDPAA2_SET_FLE_OFFSET(sge, sym_op->auth.data.offset +\n+\t\t\t\t sym_op->m_src->data_off);\n+\n+\t\tDPAA2_SET_FD_LEN(fd, sym_op->auth.data.length +\n+\t\t\t\t sym_op->auth.digest.length);\n+\t\tsge->length = sym_op->auth.data.length;\n+\t\tsge++;\n+\t\told_digest = (uint8_t *)(sge + 1);\n+\t\trte_memcpy(old_digest, sym_op->auth.digest.data,\n+\t\t\t sym_op->auth.digest.length);\n+\t\tmemset(sym_op->auth.digest.data, 0, sym_op->auth.digest.length);\n+\t\tDPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(old_digest));\n+\t\tsge->length = sym_op->auth.digest.length;\n+\t\tfle->length = sym_op->auth.data.length +\n+\t\t\t\tsym_op->auth.digest.length;\n+\t\tDPAA2_SET_FLE_FIN(sge);\n+\t}\n+\tDPAA2_SET_FLE_FIN(fle);\n+\n+\treturn 0;\n+}\n+\n+static int build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,\n+\t\t\t struct qbman_fd *fd, uint16_t bpid)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\tstruct qbman_fle *fle, *sge;\n+\tuint32_t mem_len = (5 * sizeof(struct qbman_fle));\n+\tstruct sec_flow_context *flc;\n+\tstruct ctxt_priv *priv = sess->ctxt;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* todo - we can use some mempool to avoid malloc here */\n+\tfle = rte_zmalloc(NULL, mem_len, RTE_CACHE_LINE_SIZE);\n+\tif (!fle) {\n+\t\tRTE_LOG(ERR, PMD, \"Memory alloc failed for SGE\\n\");\n+\t\treturn -1;\n+\t}\n+\t/* TODO we are using the first FLE entry to store Mbuf.\n+\t Currently we donot know which FLE has the mbuf stored.\n+\t So while retreiving we can go back 1 FLE from the FD -ADDR\n+\t to get the MBUF Addr from the previous FLE.\n+\t We can have a better approach to use the inline Mbuf*/\n+\tDPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));\n+\tfle = fle + 1;\n+\tsge = fle + 2;\n+\n+\tif (likely(bpid < MAX_BPID)) {\n+\t\tDPAA2_SET_FD_BPID(fd, bpid);\n+\t\tDPAA2_SET_FLE_BPID(fle, bpid);\n+\t\tDPAA2_SET_FLE_BPID(fle + 1, bpid);\n+\t\tDPAA2_SET_FLE_BPID(sge, bpid);\n+\t\tDPAA2_SET_FLE_BPID(sge + 1, bpid);\n+\t} else {\n+\t\tDPAA2_SET_FD_IVP(fd);\n+\t\tDPAA2_SET_FLE_IVP(fle);\n+\t\tDPAA2_SET_FLE_IVP((fle + 1));\n+\t\tDPAA2_SET_FLE_IVP(sge);\n+\t\tDPAA2_SET_FLE_IVP((sge + 1));\n+\t}\n+\n+\tflc = &priv->flc_desc[0].flc;\n+\tDPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle));\n+\tDPAA2_SET_FD_LEN(fd, sym_op->cipher.data.length + sym_op->cipher.iv.length);\n+\tDPAA2_SET_FD_COMPOUND_FMT(fd);\n+\tDPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));\n+\n+\tPMD_TX_LOG(DEBUG, \"cipher_off: 0x%x/length %d,ivlen=%d data_off: 0x%x\",\n+\t\t sym_op->cipher.data.offset,\n+\t\t sym_op->cipher.data.length,\n+\t\t sym_op->cipher.iv.length,\n+\t\t sym_op->m_src->data_off);\n+\n+\tDPAA2_SET_FLE_ADDR(fle, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n+\tDPAA2_SET_FLE_OFFSET(fle, sym_op->cipher.data.offset + sym_op->m_src->data_off);\n+\n+\t/*todo - check the length stuff, idealy this should be only cipher data length */\n+\tfle->length = sym_op->cipher.data.length + sym_op->cipher.iv.length;\n+\n+\tPMD_TX_LOG(DEBUG, \"1 - flc = %p, fle = %p FLEaddr = %x-%x, length %d\",\n+\t\t flc, fle, fle->addr_hi, fle->addr_lo, fle->length);\n+\n+\tfle++;\n+\n+\tDPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge));\n+\tfle->length = sym_op->cipher.data.length + sym_op->cipher.iv.length;\n+\n+\tDPAA2_SET_FLE_SG_EXT(fle);\n+\n+\tDPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(sym_op->cipher.iv.data));\n+\tsge->length = sym_op->cipher.iv.length;\n+\n+\tsge++;\n+\tDPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));\n+\tDPAA2_SET_FLE_OFFSET(sge, sym_op->cipher.data.offset + sym_op->m_src->data_off);\n+\n+\tsge->length = sym_op->cipher.data.length;\n+\tDPAA2_SET_FLE_FIN(sge);\n+\tDPAA2_SET_FLE_FIN(fle);\n+\n+\tPMD_TX_LOG(DEBUG, \"fdaddr =%p bpid =%d meta =%d off =%d, len =%d\",\n+\t\t (void *)DPAA2_GET_FD_ADDR(fd),\n+\t\t DPAA2_GET_FD_BPID(fd),\n+\t\t bpid_info[bpid].meta_data_size,\n+\t\t DPAA2_GET_FD_OFFSET(fd),\n+\t\t DPAA2_GET_FD_LEN(fd));\n+\n+\treturn 0;\n+}\n+\n+static inline int\n+build_sec_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,\n+\t struct qbman_fd *fd, uint16_t bpid)\n+{\n+\tint ret = -1;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tswitch (sess->ctxt_type) {\n+\tcase DPAA2_SEC_CIPHER:\n+\t\tret = build_cipher_fd(sess, op, fd, bpid);\n+\t\tbreak;\n+\tcase DPAA2_SEC_AUTH:\n+\t\tret = build_auth_fd(sess, op, fd, bpid);\n+\t\tbreak;\n+\tcase DPAA2_SEC_CIPHER_HASH:\n+\t\tret = build_authenc_fd(sess, op, fd, bpid);\n+\t\tbreak;\n+\tcase DPAA2_SEC_HASH_CIPHER:\n+\tdefault:\n+\t\tRTE_LOG(ERR, PMD, \"error: Unsupported session\\n\");\n+\t}\n+\treturn ret;\n+}\n+\n+static uint16_t\n+dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n+\t\t\tuint16_t nb_ops)\n+{\n+\t/* Function to transmit the frames to given device and VQ*/\n+\tuint32_t loop;\n+\tint32_t ret;\n+\tstruct qbman_fd fd_arr[MAX_TX_RING_SLOTS];\n+\tuint32_t frames_to_send;\n+\tstruct qbman_eq_desc eqdesc;\n+\tstruct dpaa2_sec_qp *dpaa2_qp = (struct dpaa2_sec_qp *)qp;\n+\tstruct qbman_swp *swp;\n+\tuint16_t num_tx = 0;\n+\t/*todo - need to support multiple buffer pools */\n+\tuint16_t bpid;\n+\tstruct rte_mempool *mb_pool;\n+\tdpaa2_sec_session *sess;\n+\n+\tif (unlikely(nb_ops == 0))\n+\t\treturn 0;\n+\n+\tif (ops[0]->sym->sess_type != RTE_CRYPTO_SYM_OP_WITH_SESSION) {\n+\t\tRTE_LOG(ERR, PMD, \"sessionless crypto op not supported\\n\");\n+\t\treturn 0;\n+\t}\n+\t/*Prepare enqueue descriptor*/\n+\tqbman_eq_desc_clear(&eqdesc);\n+\tqbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);\n+\tqbman_eq_desc_set_response(&eqdesc, 0, 0);\n+\tqbman_eq_desc_set_fq(&eqdesc, dpaa2_qp->tx_vq.fqid);\n+\n+\tif (!DPAA2_PER_LCORE_SEC_DPIO) {\n+\t\tret = dpaa2_affine_qbman_swp_sec();\n+\t\tif (ret) {\n+\t\t\tRTE_LOG(ERR, PMD, \"Failure in affining portal\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\tswp = DPAA2_PER_LCORE_SEC_PORTAL;\n+\n+\twhile (nb_ops) {\n+\t\tframes_to_send = (nb_ops >> 3) ? MAX_TX_RING_SLOTS : nb_ops;\n+\n+\t\tfor (loop = 0; loop < frames_to_send; loop++) {\n+\t\t\t/*Clear the unused FD fields before sending*/\n+\t\t\tmemset(&fd_arr[loop], 0, sizeof(struct qbman_fd));\n+\t\t\tsess = (dpaa2_sec_session *)(*ops)->sym->session->_private;\n+\t\t\tmb_pool = (*ops)->sym->m_src->pool;\n+\t\t\tbpid = mempool_to_bpid(mb_pool);\n+\t\t\tret = build_sec_fd(sess, *ops, &fd_arr[loop], bpid);\n+\t\t\tif (ret) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"error: Improper packet\"\n+\t\t\t\t\t \" contents for crypto operation\\n\");\n+\t\t\t\tgoto skip_tx;\n+\t\t\t}\n+\t\t\tops++;\n+\t\t}\n+\t\tloop = 0;\n+\t\twhile (loop < frames_to_send) {\n+\t\t\tloop += qbman_swp_send_multiple(swp, &eqdesc,\n+\t\t\t\t\t\t\t&fd_arr[loop],\n+\t\t\t\t\t\t\tframes_to_send - loop);\n+\t\t}\n+\n+\t\tnum_tx += frames_to_send;\n+\t\tnb_ops -= frames_to_send;\n+\t}\n+skip_tx:\n+\tdpaa2_qp->tx_vq.tx_pkts += num_tx;\n+\tdpaa2_qp->tx_vq.err_pkts += nb_ops;\n+\treturn num_tx;\n+}\n+\n+static inline\n+struct rte_crypto_op *sec_fd_to_mbuf(\n+\tconst struct qbman_fd *fd)\n+{\n+\tstruct qbman_fle *fle;\n+\tstruct rte_crypto_op *op;\n+\n+\tfle = (struct qbman_fle *)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));\n+\n+\tPMD_RX_LOG(DEBUG, \"FLE addr = %x - %x, offset = %x\",\n+\t\t fle->addr_hi, fle->addr_lo, fle->fin_bpid_offset);\n+\n+\t/* TODO we are using the first FLE entry to store Mbuf.\n+\t Currently we donot know which FLE has the mbuf stored.\n+\t So while retreiving we can go back 1 FLE from the FD -ADDR\n+\t to get the MBUF Addr from the previous FLE.\n+\t We can have a better approach to use the inline Mbuf*/\n+\n+\tif (unlikely(DPAA2_GET_FD_IVP(fd))) {\n+\t\t/* TODO complete it. */\n+\t\tRTE_LOG(ERR, PMD, \"error: Non inline buffer - WHAT to DO?\");\n+\t\treturn NULL;\n+\t}\n+\top = (struct rte_crypto_op *)DPAA2_IOVA_TO_VADDR(\n+\t\t\tDPAA2_GET_FLE_ADDR((fle - 1)));\n+\n+\t/* Prefeth op */\n+\trte_prefetch0(op->sym->m_src);\n+\n+\tPMD_RX_LOG(DEBUG, \"mbuf %p BMAN buf addr %p\",\n+\t\t (void *)op->sym->m_src, op->sym->m_src->buf_addr);\n+\n+\tPMD_RX_LOG(DEBUG, \"fdaddr =%p bpid =%d meta =%d off =%d, len =%d\",\n+\t\t (void *)DPAA2_GET_FD_ADDR(fd),\n+\t\t DPAA2_GET_FD_BPID(fd),\n+\t\t bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,\n+\t\t DPAA2_GET_FD_OFFSET(fd),\n+\t\t DPAA2_GET_FD_LEN(fd));\n+\n+\t/* free the fle memory */\n+\trte_free(fle - 1);\n+\n+\treturn op;\n+}\n+\n+static uint16_t\n+dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops,\n+\t\t\tuint16_t nb_ops)\n+{\n+\t/* Function is responsible to receive frames for a given device and VQ*/\n+\tstruct dpaa2_sec_qp *dpaa2_qp = (struct dpaa2_sec_qp *)qp;\n+\tstruct qbman_result *dq_storage;\n+\tuint32_t fqid = dpaa2_qp->rx_vq.fqid;\n+\tint ret, num_rx = 0;\n+\tuint8_t is_last = 0, status;\n+\tstruct qbman_swp *swp;\n+\tconst struct qbman_fd *fd;\n+\tstruct qbman_pull_desc pulldesc;\n+\n+\tif (!DPAA2_PER_LCORE_SEC_DPIO) {\n+\t\tret = dpaa2_affine_qbman_swp_sec();\n+\t\tif (ret) {\n+\t\t\tRTE_LOG(ERR, PMD, \"Failure in affining portal\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\tswp = DPAA2_PER_LCORE_SEC_PORTAL;\n+\tdq_storage = dpaa2_qp->rx_vq.q_storage->dq_storage[0];\n+\n+\tqbman_pull_desc_clear(&pulldesc);\n+\tqbman_pull_desc_set_numframes(&pulldesc,\n+\t\t\t\t (nb_ops > DPAA2_DQRR_RING_SIZE) ?\n+\t\t\t\t DPAA2_DQRR_RING_SIZE : nb_ops);\n+\tqbman_pull_desc_set_fq(&pulldesc, fqid);\n+\tqbman_pull_desc_set_storage(&pulldesc, dq_storage,\n+\t\t\t\t (dma_addr_t)DPAA2_VADDR_TO_IOVA(dq_storage), 1);\n+\n+\t/*Issue a volatile dequeue command. */\n+\twhile (1) {\n+\t\tif (qbman_swp_pull(swp, &pulldesc)) {\n+\t\t\tRTE_LOG(WARNING, PMD, \"SEC VDQ command is not issued.\"\n+\t\t\t\t\"QBMAN is busy\\n\");\n+\t\t\t/* Portal was busy, try again */\n+\t\t\tcontinue;\n+\t\t}\n+\t\tbreak;\n+\t};\n+\n+\t/* Receive the packets till Last Dequeue entry is found with\n+\t respect to the above issues PULL command.\n+\t */\n+\twhile (!is_last) {\n+\t\t/*Check if the previous issued command is completed.\n+\t\t*Also seems like the SWP is shared between the Ethernet Driver\n+\t\t*and the SEC driver.*/\n+\t\twhile (!qbman_check_command_complete(swp, dq_storage))\n+\t\t\t;\n+\n+\t\t/* Loop until the dq_storage is updated with\n+\t\t * new token by QBMAN */\n+\t\twhile (!qbman_result_has_new_result(swp, dq_storage))\n+\t\t\t;\n+\t\t/* Check whether Last Pull command is Expired and\n+\t\tsetting Condition for Loop termination */\n+\t\tif (qbman_result_DQ_is_pull_complete(dq_storage)) {\n+\t\t\tis_last = 1;\n+\t\t\t/* Check for valid frame. */\n+\t\t\tstatus = (uint8_t)qbman_result_DQ_flags(dq_storage);\n+\t\t\tif (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0)) {\n+\t\t\t\tPMD_RX_LOG(DEBUG, \"No frame is delivered\");\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfd = qbman_result_DQ_fd(dq_storage);\n+\t\tops[num_rx] = sec_fd_to_mbuf(fd);\n+\n+\t\tif (unlikely(fd->simple.frc)) {\n+\t\t\t/* TODO Parse SEC errors */\n+\t\t\tRTE_LOG(ERR, PMD, \"SEC returned Error - %x\\n\", fd->simple.frc);\n+\t\t\tops[num_rx]->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t} else {\n+\t\t\tops[num_rx]->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t}\n+\n+\t\tnum_rx++;\n+\t\tdq_storage++;\n+\t} /* End of Packet Rx loop */\n+\n+\tdpaa2_qp->rx_vq.rx_pkts += num_rx;\n+\n+\tPMD_RX_LOG(DEBUG, \"SEC Received %d Packets\", num_rx);\n+\t/*Return the total number of packets received to DPAA2 app*/\n+\treturn num_rx;\n+}\n+/** Release queue pair */\n+static int\n+dpaa2_sec_queue_pair_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)\n+{\n+\tstruct dpaa2_sec_qp *qp =\n+\t\t(struct dpaa2_sec_qp *)dev->data->queue_pairs[queue_pair_id];\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (qp->rx_vq.q_storage) {\n+\t\tdpaa2_free_dq_storage(qp->rx_vq.q_storage);\n+\t\trte_free(qp->rx_vq.q_storage);\n+\t}\n+\trte_free(qp);\n+\n+\tdev->data->queue_pairs[queue_pair_id] = NULL;\n+\n+\treturn 0;\n+}\n+\n+/** Setup a queue pair */\n+static int\n+dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n+\t\t\t __rte_unused const struct rte_cryptodev_qp_conf *qp_conf,\n+\t\t__rte_unused int socket_id)\n+{\n+\tstruct dpaa2_sec_dev_private *priv = dev->data->dev_private;\n+\tstruct dpaa2_sec_qp *qp;\n+\tstruct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;\n+\tstruct dpseci_rx_queue_cfg cfg;\n+\tint32_t retcode;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* If qp is already in use free ring memory and qp metadata. */\n+\tif (dev->data->queue_pairs[qp_id] != NULL) {\n+\t\tPMD_DRV_LOG(INFO, \"QP already setup\");\n+\t\treturn 0;\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"dev =%p, queue =%d, conf =%p\",\n+\t\t dev, qp_id, qp_conf);\n+\n+\tmemset(&cfg, 0, sizeof(struct dpseci_rx_queue_cfg));\n+\n+\tqp = rte_malloc(NULL, sizeof(struct dpaa2_sec_qp),\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (!qp) {\n+\t\tRTE_LOG(ERR, PMD, \"malloc failed for rx/tx queues\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tqp->rx_vq.dev = dev;\n+\tqp->tx_vq.dev = dev;\n+\tqp->rx_vq.q_storage = rte_malloc(\"sec dq storage\",\n+\t\tsizeof(struct queue_storage_info_t),\n+\t\tRTE_CACHE_LINE_SIZE);\n+\tif (!qp->rx_vq.q_storage) {\n+\t\tRTE_LOG(ERR, PMD, \"malloc failed for q_storage\\n\");\n+\t\treturn -1;\n+\t}\n+\tmemset(qp->rx_vq.q_storage, 0, sizeof(struct queue_storage_info_t));\n+\n+\tif (dpaa2_alloc_dq_storage(qp->rx_vq.q_storage)) {\n+\t\tRTE_LOG(ERR, PMD, \"dpaa2_alloc_dq_storage failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tdev->data->queue_pairs[qp_id] = qp;\n+\n+\tcfg.options = cfg.options | DPSECI_QUEUE_OPT_USER_CTX;\n+\tcfg.user_ctx = (uint64_t)(&qp->rx_vq);\n+\tretcode = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token,\n+\t\t\t\t qp_id, &cfg);\n+\treturn retcode;\n+}\n+\n+/** Start queue pair */\n+static int\n+dpaa2_sec_queue_pair_start(__rte_unused struct rte_cryptodev *dev,\n+\t\t\t __rte_unused uint16_t queue_pair_id)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\treturn 0;\n+}\n+\n+/** Stop queue pair */\n+static int\n+dpaa2_sec_queue_pair_stop(__rte_unused struct rte_cryptodev *dev,\n+\t\t\t __rte_unused uint16_t queue_pair_id)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\treturn 0;\n+}\n+\n+/** Return the number of allocated queue pairs */\n+static uint32_t\n+dpaa2_sec_queue_pair_count(struct rte_cryptodev *dev)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\treturn dev->data->nb_queue_pairs;\n+}\n+\n+/** Returns the size of the aesni gcm session structure */\n+static unsigned\n+dpaa2_sec_session_get_size(struct rte_cryptodev *dev __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\treturn sizeof(dpaa2_sec_session);\n+}\n+\n+static void\n+dpaa2_sec_session_initialize(struct rte_mempool *mp __rte_unused,\n+\t\t\t void *sess __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+}\n+\n+static int dpaa2_sec_cipher_init(struct rte_cryptodev *dev,\n+\t\t\t\t struct rte_crypto_sym_xform *xform,\n+\t\tdpaa2_sec_session *session)\n+{\n+\tstruct dpaa2_sec_cipher_ctxt *ctxt = &session->ext_params.cipher_ctxt;\n+\tstruct alginfo cipherdata;\n+\tunsigned int bufsize, i;\n+\tstruct ctxt_priv *priv;\n+\tstruct sec_flow_context *flc;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* For SEC CIPHER only one descriptor is required. */\n+\tpriv = (struct ctxt_priv *)rte_zmalloc(NULL,\n+\t\t\tsizeof(struct ctxt_priv) + sizeof(struct sec_flc_desc),\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (priv == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"No Memory for priv CTXT\");\n+\t\treturn -1;\n+\t}\n+\n+\tflc = &priv->flc_desc[0].flc;\n+\n+\tsession->cipher_key.data = rte_zmalloc(NULL, xform->cipher.key.length,\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (session->cipher_key.data == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"No Memory for cipher key\");\n+\t\treturn -1;\n+\t}\n+\tsession->cipher_key.length = xform->cipher.key.length;\n+\n+\tmemcpy(session->cipher_key.data, xform->cipher.key.data, xform->cipher.key.length);\n+\tcipherdata.key = (uint64_t)session->cipher_key.data;\n+\tcipherdata.keylen = session->cipher_key.length;\n+\tcipherdata.key_enc_flags = 0;\n+\tcipherdata.key_type = RTA_DATA_IMM;\n+\n+\tswitch (xform->cipher.algo) {\n+\tcase RTE_CRYPTO_CIPHER_AES_CBC:\n+\t\tcipherdata.algtype = OP_ALG_ALGSEL_AES;\n+\t\tcipherdata.algmode = OP_ALG_AAI_CBC;\n+\t\tsession->cipher_alg = RTE_CRYPTO_CIPHER_AES_CBC;\n+\t\tctxt->iv.length = AES_CBC_IV_LEN;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_3DES_CBC:\n+\t\tcipherdata.algtype = OP_ALG_ALGSEL_3DES;\n+\t\tcipherdata.algmode = OP_ALG_AAI_CBC;\n+\t\tsession->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CBC;\n+\t\tctxt->iv.length = TDES_CBC_IV_LEN;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_AES_CTR:\n+\tcase RTE_CRYPTO_CIPHER_3DES_CTR:\n+\tcase RTE_CRYPTO_CIPHER_AES_GCM:\n+\tcase RTE_CRYPTO_CIPHER_AES_CCM:\n+\tcase RTE_CRYPTO_CIPHER_AES_ECB:\n+\tcase RTE_CRYPTO_CIPHER_3DES_ECB:\n+\tcase RTE_CRYPTO_CIPHER_AES_XTS:\n+\tcase RTE_CRYPTO_CIPHER_AES_F8:\n+\tcase RTE_CRYPTO_CIPHER_ARC4:\n+\tcase RTE_CRYPTO_CIPHER_KASUMI_F8:\n+\tcase RTE_CRYPTO_CIPHER_SNOW3G_UEA2:\n+\tcase RTE_CRYPTO_CIPHER_ZUC_EEA3:\n+\tcase RTE_CRYPTO_CIPHER_NULL:\n+\t\tRTE_LOG(ERR, PMD, \"Crypto: Unsupported Cipher alg %u\",\n+\t\t\txform->cipher.algo);\n+\t\tgoto error_out;\n+\tdefault:\n+\t\tRTE_LOG(ERR, PMD, \"Crypto: Undefined Cipher specified %u\\n\",\n+\t\t\txform->cipher.algo);\n+\t\tgoto error_out;\n+\t}\n+\tsession->dir = (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?\n+\t\t\t\tDIR_ENC : DIR_DEC;\n+\n+\tbufsize = cnstr_shdsc_blkcipher(priv->flc_desc[0].desc, 1, 0,\n+\t\t\t\t\t&cipherdata, NULL, ctxt->iv.length,\n+\t\t\tsession->dir);\n+\tflc->dhr = 0;\n+\tflc->bpv0 = 0x1;\n+\tflc->mode_bits = 0x8000;\n+\n+\tflc->word1_sdl = (uint8_t)bufsize;\n+\tflc->word2_rflc_31_0 = lower_32_bits(\n+\t\t\t(uint64_t)&(((struct dpaa2_sec_qp *)\n+\t\t\tdev->data->queue_pairs[0])->rx_vq));\n+\tflc->word3_rflc_63_32 = upper_32_bits(\n+\t\t\t(uint64_t)&(((struct dpaa2_sec_qp *)\n+\t\t\tdev->data->queue_pairs[0])->rx_vq));\n+\tsession->ctxt = priv;\n+\n+\tfor (i = 0; i < bufsize; i++)\n+\t\tPMD_DRV_LOG(DEBUG, \"DESC[%d]:0x%x\\n\",\n+\t\t\t i, priv->flc_desc[0].desc[i]);\n+\n+\treturn 0;\n+\n+error_out:\n+\trte_free(session->cipher_key.data);\n+\treturn -1;\n+}\n+\n+static int dpaa2_sec_auth_init(struct rte_cryptodev *dev,\n+\t\t\t struct rte_crypto_sym_xform *xform,\n+\t\tdpaa2_sec_session *session)\n+{\n+\tstruct dpaa2_sec_auth_ctxt *ctxt = &session->ext_params.auth_ctxt;\n+\tstruct alginfo authdata;\n+\tunsigned int bufsize;\n+\tstruct ctxt_priv *priv;\n+\tstruct sec_flow_context *flc;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* For SEC AUTH three descriptors are required for various stages */\n+\tpriv = (struct ctxt_priv *)rte_zmalloc(NULL,\n+\t\t\tsizeof(struct ctxt_priv) + 3 *\n+\t\t\tsizeof(struct sec_flc_desc),\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (priv == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"No Memory for priv CTXT\");\n+\t\treturn -1;\n+\t}\n+\n+\tflc = &priv->flc_desc[DESC_INITFINAL].flc;\n+\n+\tsession->auth_key.data = rte_zmalloc(NULL, xform->auth.key.length,\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\tsession->auth_key.length = xform->auth.key.length;\n+\n+\tmemcpy(session->auth_key.data, xform->auth.key.data,\n+\t xform->auth.key.length);\n+\tauthdata.key = (uint64_t)session->auth_key.data;\n+\tauthdata.keylen = session->auth_key.length;\n+\tauthdata.key_enc_flags = 0;\n+\tauthdata.key_type = RTA_DATA_IMM;\n+\n+\tswitch (xform->auth.algo) {\n+\tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA1;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA1_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_MD5;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_MD5_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA256;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA256_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA384;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA384_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA512;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA512_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA224_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA224;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA224_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_AES_XCBC_MAC:\n+\tcase RTE_CRYPTO_AUTH_AES_GCM:\n+\tcase RTE_CRYPTO_AUTH_SNOW3G_UIA2:\n+\tcase RTE_CRYPTO_AUTH_NULL:\n+\tcase RTE_CRYPTO_AUTH_SHA1:\n+\tcase RTE_CRYPTO_AUTH_SHA256:\n+\tcase RTE_CRYPTO_AUTH_SHA512:\n+\tcase RTE_CRYPTO_AUTH_SHA224:\n+\tcase RTE_CRYPTO_AUTH_SHA384:\n+\tcase RTE_CRYPTO_AUTH_MD5:\n+\tcase RTE_CRYPTO_AUTH_AES_CCM:\n+\tcase RTE_CRYPTO_AUTH_AES_GMAC:\n+\tcase RTE_CRYPTO_AUTH_KASUMI_F9:\n+\tcase RTE_CRYPTO_AUTH_AES_CMAC:\n+\tcase RTE_CRYPTO_AUTH_AES_CBC_MAC:\n+\tcase RTE_CRYPTO_AUTH_ZUC_EIA3:\n+\t\tRTE_LOG(ERR, PMD, \"Crypto: Unsupported auth alg %u\",\n+\t\t\txform->auth.algo);\n+\t\tgoto error_out;\n+\tdefault:\n+\t\tRTE_LOG(ERR, PMD, \"Crypto: Undefined Auth specified %u\\n\",\n+\t\t\txform->auth.algo);\n+\t\tgoto error_out;\n+\t}\n+\tsession->dir = (xform->auth.op == RTE_CRYPTO_AUTH_OP_GENERATE) ?\n+\t\t\t\tDIR_ENC : DIR_DEC;\n+\n+\tbufsize = cnstr_shdsc_hmac(priv->flc_desc[DESC_INITFINAL].desc,\n+\t\t\t\t 1, 0, &authdata, !session->dir, ctxt->trunc_len);\n+\n+\tflc->word1_sdl = (uint8_t)bufsize;\n+\tflc->word2_rflc_31_0 = lower_32_bits(\n+\t\t\t(uint64_t)&(((struct dpaa2_sec_qp *)\n+\t\t\tdev->data->queue_pairs[0])->rx_vq));\n+\tflc->word3_rflc_63_32 = upper_32_bits(\n+\t\t\t(uint64_t)&(((struct dpaa2_sec_qp *)\n+\t\t\tdev->data->queue_pairs[0])->rx_vq));\n+\tsession->ctxt = priv;\n+\n+\treturn 0;\n+\n+error_out:\n+\trte_free(session->auth_key.data);\n+\treturn -1;\n+}\n+\n+static int dpaa2_sec_aead_init(struct rte_cryptodev *dev,\n+\t\t\t struct rte_crypto_sym_xform *xform,\n+\t\tdpaa2_sec_session *session)\n+{\n+\tstruct dpaa2_sec_aead_ctxt *ctxt = &session->ext_params.aead_ctxt;\n+\tstruct alginfo authdata, cipherdata;\n+\tunsigned int bufsize;\n+\tstruct ctxt_priv *priv;\n+\tstruct sec_flow_context *flc;\n+\tstruct rte_crypto_cipher_xform *cipher_xform;\n+\tstruct rte_crypto_auth_xform *auth_xform;\n+\tint err;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (session->ext_params.aead_ctxt.auth_cipher_text) {\n+\t\tcipher_xform = &xform->cipher;\n+\t\tauth_xform = &xform->next->auth;\n+\t\tsession->ctxt_type =\n+\t\t\t(cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?\n+\t\t\tDPAA2_SEC_CIPHER_HASH : DPAA2_SEC_HASH_CIPHER;\n+\t} else {\n+\t\tcipher_xform = &xform->next->cipher;\n+\t\tauth_xform = &xform->auth;\n+\t\tsession->ctxt_type =\n+\t\t\t(cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?\n+\t\t\tDPAA2_SEC_HASH_CIPHER : DPAA2_SEC_CIPHER_HASH;\n+\t}\n+\t/* For SEC AEAD only one descriptor is required */\n+\tpriv = (struct ctxt_priv *)rte_zmalloc(NULL,\n+\t\t\tsizeof(struct ctxt_priv) + sizeof(struct sec_flc_desc),\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (priv == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"No Memory for priv CTXT\");\n+\t\treturn -1;\n+\t}\n+\n+\tflc = &priv->flc_desc[0].flc;\n+\n+\tsession->cipher_key.data = rte_zmalloc(NULL, cipher_xform->key.length,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (session->cipher_key.data == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"No Memory for cipher key\");\n+\t\treturn -1;\n+\t}\n+\tsession->cipher_key.length = cipher_xform->key.length;\n+\tsession->auth_key.data = rte_zmalloc(NULL, auth_xform->key.length,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (session->auth_key.data == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"No Memory for auth key\");\n+\t\tgoto error_out;\n+\t}\n+\tsession->auth_key.length = auth_xform->key.length;\n+\tmemcpy(session->cipher_key.data, cipher_xform->key.data,\n+\t cipher_xform->key.length);\n+\tmemcpy(session->auth_key.data, auth_xform->key.data,\n+\t auth_xform->key.length);\n+\n+\tctxt->trunc_len = auth_xform->digest_length;\n+\tauthdata.key = (uint64_t)session->auth_key.data;\n+\tauthdata.keylen = session->auth_key.length;\n+\tauthdata.key_enc_flags = 0;\n+\tauthdata.key_type = RTA_DATA_IMM;\n+\n+\tswitch (auth_xform->algo) {\n+\tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA1;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA1_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_MD5;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_MD5_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA224_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA224;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA224_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA256;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA256_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA384;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA384_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n+\t\tauthdata.algtype = OP_ALG_ALGSEL_SHA512;\n+\t\tauthdata.algmode = OP_ALG_AAI_HMAC;\n+\t\tsession->auth_alg = RTE_CRYPTO_AUTH_SHA512_HMAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_AUTH_AES_XCBC_MAC:\n+\tcase RTE_CRYPTO_AUTH_AES_GCM:\n+\tcase RTE_CRYPTO_AUTH_SNOW3G_UIA2:\n+\tcase RTE_CRYPTO_AUTH_NULL:\n+\tcase RTE_CRYPTO_AUTH_SHA1:\n+\tcase RTE_CRYPTO_AUTH_SHA256:\n+\tcase RTE_CRYPTO_AUTH_SHA512:\n+\tcase RTE_CRYPTO_AUTH_SHA224:\n+\tcase RTE_CRYPTO_AUTH_SHA384:\n+\tcase RTE_CRYPTO_AUTH_MD5:\n+\tcase RTE_CRYPTO_AUTH_AES_CCM:\n+\tcase RTE_CRYPTO_AUTH_AES_GMAC:\n+\tcase RTE_CRYPTO_AUTH_KASUMI_F9:\n+\tcase RTE_CRYPTO_AUTH_AES_CMAC:\n+\tcase RTE_CRYPTO_AUTH_AES_CBC_MAC:\n+\tcase RTE_CRYPTO_AUTH_ZUC_EIA3:\n+\t\tRTE_LOG(ERR, PMD, \"Crypto: Unsupported auth alg %u\",\n+\t\t\tauth_xform->algo);\n+\t\tgoto error_out;\n+\tdefault:\n+\t\tRTE_LOG(ERR, PMD, \"Crypto: Undefined Auth specified %u\\n\",\n+\t\t\tauth_xform->algo);\n+\t\tgoto error_out;\n+\t}\n+\tcipherdata.key = (uint64_t)session->cipher_key.data;\n+\tcipherdata.keylen = session->cipher_key.length;\n+\tcipherdata.key_enc_flags = 0;\n+\tcipherdata.key_type = RTA_DATA_IMM;\n+\n+\tswitch (cipher_xform->algo) {\n+\tcase RTE_CRYPTO_CIPHER_AES_CBC:\n+\t\tcipherdata.algtype = OP_ALG_ALGSEL_AES;\n+\t\tcipherdata.algmode = OP_ALG_AAI_CBC;\n+\t\tsession->cipher_alg = RTE_CRYPTO_CIPHER_AES_CBC;\n+\t\tctxt->iv.length = AES_CBC_IV_LEN;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_3DES_CBC:\n+\t\tcipherdata.algtype = OP_ALG_ALGSEL_3DES;\n+\t\tcipherdata.algmode = OP_ALG_AAI_CBC;\n+\t\tsession->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CBC;\n+\t\tctxt->iv.length = TDES_CBC_IV_LEN;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_AES_GCM:\n+\tcase RTE_CRYPTO_CIPHER_SNOW3G_UEA2:\n+\tcase RTE_CRYPTO_CIPHER_NULL:\n+\tcase RTE_CRYPTO_CIPHER_3DES_ECB:\n+\tcase RTE_CRYPTO_CIPHER_AES_ECB:\n+\tcase RTE_CRYPTO_CIPHER_AES_CTR:\n+\tcase RTE_CRYPTO_CIPHER_AES_CCM:\n+\tcase RTE_CRYPTO_CIPHER_KASUMI_F8:\n+\t\tRTE_LOG(ERR, PMD, \"Crypto: Unsupported Cipher alg %u\",\n+\t\t\tcipher_xform->algo);\n+\t\tgoto error_out;\n+\tdefault:\n+\t\tRTE_LOG(ERR, PMD, \"Crypto: Undefined Cipher specified %u\\n\",\n+\t\t\tcipher_xform->algo);\n+\t\tgoto error_out;\n+\t}\n+\tsession->dir = (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?\n+\t\t\t\tDIR_ENC : DIR_DEC;\n+\n+\tpriv->flc_desc[0].desc[0] = authdata.keylen;\n+\tpriv->flc_desc[0].desc[1] = cipherdata.keylen;\n+\terr = rta_inline_query(IPSEC_AUTH_VAR_BASE_DESC_LEN,\n+\t\t\t0, (unsigned *)priv->flc_desc[0].desc,\n+\t\t\t&priv->flc_desc[0].desc[2], 2);\n+\n+\tif (err < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Crypto: Incorrect key lengths\");\n+\t\tgoto error_out;\n+\t}\n+\n+\tif (priv->flc_desc[0].desc[2] & 1)\n+\t\tauthdata.key_type = RTA_DATA_PTR;\n+\telse\n+\t\tauthdata.key_type = RTA_DATA_IMM;\n+\n+\tif (priv->flc_desc[0].desc[2] & (1<<1))\n+\t\tcipherdata.key_type = RTA_DATA_PTR;\n+\telse\n+\t\tcipherdata.key_type = RTA_DATA_IMM;\n+\tpriv->flc_desc[0].desc[0] = 0;\n+\tpriv->flc_desc[0].desc[1] = 0;\n+\tpriv->flc_desc[0].desc[2] = 0;\n+\n+\tif (session->ctxt_type == DPAA2_SEC_CIPHER_HASH) {\n+\t\tbufsize = cnstr_shdsc_authenc(priv->flc_desc[0].desc, 1,\n+\t\t\t\t\t 0, &cipherdata, &authdata, ctxt->iv.length,\n+\t\t\t\t\t ctxt->auth_only_len, ctxt->trunc_len,\n+\t\t\t\t\t session->dir);\n+\t} else {\n+\t\tRTE_LOG(ERR, PMD, \"Hash before cipher not supported\");\n+\t\tgoto error_out;\n+\t}\n+\n+\tflc->word1_sdl = (uint8_t)bufsize;\n+\tflc->word2_rflc_31_0 = lower_32_bits(\n+\t\t\t(uint64_t)&(((struct dpaa2_sec_qp *)\n+\t\t\tdev->data->queue_pairs[0])->rx_vq));\n+\tflc->word3_rflc_63_32 = upper_32_bits(\n+\t\t\t(uint64_t)&(((struct dpaa2_sec_qp *)\n+\t\t\tdev->data->queue_pairs[0])->rx_vq));\n+\tsession->ctxt = priv;\n+\n+\treturn 0;\n+\n+error_out:\n+\trte_free(session->cipher_key.data);\n+\trte_free(session->auth_key.data);\n+\treturn -1;\n+}\n+\n+static void *\n+dpaa2_sec_session_configure(struct rte_cryptodev *dev,\n+\t\t\t struct rte_crypto_sym_xform *xform,\tvoid *sess)\n+{\n+\tdpaa2_sec_session *session = sess;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (unlikely(sess == NULL)) {\n+\t\tRTE_LOG(ERR, PMD, \"invalid session struct\");\n+\t\treturn NULL;\n+\t}\n+\t/* Cipher Only */\n+\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL) {\n+\t\tsession->ctxt_type = DPAA2_SEC_CIPHER;\n+\t\tdpaa2_sec_cipher_init(dev, xform, session);\n+\n+\t/* Authentication Only */\n+\t} else if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&\n+\t\t xform->next == NULL) {\n+\t\tsession->ctxt_type = DPAA2_SEC_AUTH;\n+\t\tdpaa2_sec_auth_init(dev, xform, session);\n+\n+\t/* Cipher then Authenticate */\n+\t} else if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&\n+\t\t xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) {\n+\t\tsession->ext_params.aead_ctxt.auth_cipher_text = true;\n+\t\tdpaa2_sec_aead_init(dev, xform, session);\n+\n+\t/* Authenticate then Cipher */\n+\t} else if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&\n+\t\t xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {\n+\t\tsession->ext_params.aead_ctxt.auth_cipher_text = false;\n+\t\tdpaa2_sec_aead_init(dev, xform, session);\n+\t} else {\n+\t\tRTE_LOG(ERR, PMD, \"Invalid crypto type\");\n+\t\treturn NULL;\n+\t}\n+\n+\treturn session;\n+}\n+\n+/** Clear the memory of session so it doesn't leave key material behind */\n+static void\n+dpaa2_sec_session_clear(struct rte_cryptodev *dev __rte_unused, void *sess)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (sess)\n+\t\tmemset(sess, 0, sizeof(dpaa2_sec_session));\n+}\n+\n+static int\n+dpaa2_sec_dev_configure(struct rte_cryptodev *dev __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\treturn -ENOTSUP;\n+}\n+\n+static int\n+dpaa2_sec_dev_start(struct rte_cryptodev *dev)\n+{\n+\tstruct dpaa2_sec_dev_private *priv = dev->data->dev_private;\n+\tstruct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;\n+\tstruct dpseci_attr attr;\n+\tstruct dpaa2_queue *dpaa2_q;\n+\tstruct dpaa2_sec_qp **qp = (struct dpaa2_sec_qp **)\n+\t\t\t\t\tdev->data->queue_pairs;\n+\tstruct dpseci_rx_queue_attr rx_attr;\n+\tstruct dpseci_tx_queue_attr tx_attr;\n+\tint ret, i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tmemset(&attr, 0, sizeof(struct dpseci_attr));\n+\n+\tret = dpseci_enable(dpseci, CMD_PRI_LOW, priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"DPSECI with HW_ID = %d ENABLE FAILED\\n\",\n+\t\t\t priv->hw_id);\n+\t\tgoto get_attr_failure;\n+\t}\n+\tret = dpseci_get_attributes(dpseci, CMD_PRI_LOW, priv->token, &attr);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"DPSEC ATTRIBUTE READ FAILED, disabling DPSEC\\n\");\n+\t\tgoto get_attr_failure;\n+\t}\n+\tfor (i = 0; i < attr.num_rx_queues && qp[i]; i++) {\n+\t\tdpaa2_q = &qp[i]->rx_vq;\n+\t\tdpseci_get_rx_queue(dpseci, CMD_PRI_LOW, priv->token, i,\n+\t\t\t\t &rx_attr);\n+\t\tdpaa2_q->fqid = rx_attr.fqid;\n+\t\tPMD_INIT_LOG(DEBUG, \"rx_fqid: %d\", dpaa2_q->fqid);\n+\t}\n+\tfor (i = 0; i < attr.num_tx_queues && qp[i]; i++) {\n+\t\tdpaa2_q = &qp[i]->tx_vq;\n+\t\tdpseci_get_tx_queue(dpseci, CMD_PRI_LOW, priv->token, i,\n+\t\t\t\t &tx_attr);\n+\t\tdpaa2_q->fqid = tx_attr.fqid;\n+\t\tPMD_INIT_LOG(DEBUG, \"tx_fqid: %d\", dpaa2_q->fqid);\n+\t}\n+\n+\treturn 0;\n+get_attr_failure:\n+\tdpseci_disable(dpseci, CMD_PRI_LOW, priv->token);\n+\treturn -1;\n+}\n+\n+static void\n+dpaa2_sec_dev_stop(struct rte_cryptodev *dev)\n+{\n+\tstruct dpaa2_sec_dev_private *priv = dev->data->dev_private;\n+\tstruct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tret = dpseci_disable(dpseci, CMD_PRI_LOW, priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure in disabling dpseci %d device\",\n+\t\t\t priv->hw_id);\n+\t\treturn;\n+\t}\n+\n+\tret = dpseci_reset(dpseci, CMD_PRI_LOW, priv->token);\n+\tif (ret < 0) {\n+\t\tPMD_INIT_LOG(ERR, \"SEC Device cannot be reset:Error = %0x\\n\",\n+\t\t\t ret);\n+\t\treturn;\n+\t}\n+}\n+\n+static int\n+dpaa2_sec_dev_close(struct rte_cryptodev *dev)\n+{\n+\tstruct dpaa2_sec_dev_private *priv = dev->data->dev_private;\n+\tstruct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/*Function is reverse of dpaa2_sec_dev_init.\n+\t * It does the following:\n+\t * 1. Detach a DPSECI from attached resources i.e. buffer pools, dpbp_id.\n+\t * 2. Close the DPSECI device\n+\t * 3. Free the allocated resources.\n+\t */\n+\n+\t/*Close the device at underlying layer*/\n+\tret = dpseci_close(dpseci, CMD_PRI_LOW, priv->token);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failure closing dpseci device with\"\n+\t\t\t \" error code %d\\n\", ret);\n+\t\treturn -1;\n+\t}\n+\n+\t/*Free the allocated memory for ethernet private data and dpseci*/\n+\tpriv->hw = NULL;\n+\tfree(dpseci);\n+\n+\treturn 0;\n+}\n+\n+static void\n+dpaa2_sec_dev_infos_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info)\n+{\n+\tstruct dpaa2_sec_dev_private *internals = dev->data->dev_private;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (info != NULL) {\n+\t\tinfo->max_nb_queue_pairs = internals->max_nb_queue_pairs;\n+\t\tinfo->feature_flags = dev->feature_flags;\n+\t\tinfo->capabilities = dpaa2_sec_capabilities;\n+\t\tinfo->sym.max_nb_sessions = internals->max_nb_sessions;\n+\t\tinfo->dev_type = RTE_CRYPTODEV_DPAA2_SEC_PMD;\n+\t}\n+}\n+\n+static struct rte_cryptodev_ops crypto_ops = {\n+\t.dev_configure\t = dpaa2_sec_dev_configure,\n+\t.dev_start\t = dpaa2_sec_dev_start,\n+\t.dev_stop\t = dpaa2_sec_dev_stop,\n+\t.dev_close\t = dpaa2_sec_dev_close,\n+\t.dev_infos_get = dpaa2_sec_dev_infos_get,\n+\t.queue_pair_setup = dpaa2_sec_queue_pair_setup,\n+\t.queue_pair_release = dpaa2_sec_queue_pair_release,\n+\t.queue_pair_start = dpaa2_sec_queue_pair_start,\n+\t.queue_pair_stop = dpaa2_sec_queue_pair_stop,\n+\t.queue_pair_count = dpaa2_sec_queue_pair_count,\n+\t.session_get_size = dpaa2_sec_session_get_size,\n+\t.session_initialize = dpaa2_sec_session_initialize,\n+\t.session_configure = dpaa2_sec_session_configure,\n+\t.session_clear = dpaa2_sec_session_clear,\n+};\n+\n static int\n dpaa2_sec_uninit(__attribute__((unused)) const struct rte_cryptodev_driver *crypto_drv,\n \t\t struct rte_cryptodev *dev)\n@@ -71,13 +1381,29 @@ static int\n dpaa2_sec_dev_init(__attribute__((unused)) struct rte_cryptodev_driver *crypto_drv,\n \t\t struct rte_cryptodev *dev)\n {\n+\tstruct dpaa2_sec_dev_private *internals;\n \tstruct fsl_mc_io *dpseci;\n \tuint16_t token;\n+\tstruct dpseci_attr attr;\n \tint retcode, hw_id = dev->pci_dev->addr.devid;\n \n+\tPMD_INIT_FUNC_TRACE();\n+\tPMD_INIT_LOG(DEBUG, \"Found crypto device at %02x:%02x.%x\",\n+\t\t dev->pci_dev->addr.bus,\n+\t\t dev->pci_dev->addr.devid,\n+\t\t dev->pci_dev->addr.function);\n \n \tdev->dev_type = RTE_CRYPTODEV_DPAA2_SEC_PMD;\n+\tdev->dev_ops = &crypto_ops;\n+\n+\tdev->enqueue_burst = dpaa2_sec_enqueue_burst;\n+\tdev->dequeue_burst = dpaa2_sec_dequeue_burst;\n+\tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING;\n \n+\tinternals = dev->data->dev_private;\n+\tinternals->max_nb_sessions = RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS;\n \n \t/*\n \t * For secondary processes, we don't initialise any further as primary\n@@ -104,8 +1430,18 @@ dpaa2_sec_dev_init(__attribute__((unused)) struct rte_cryptodev_driver *crypto_d\n \t\t\t retcode);\n \t\tgoto init_error;\n \t}\n+\tretcode = dpseci_get_attributes(dpseci, CMD_PRI_LOW, token, &attr);\n+\tif (retcode != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Cannot get dpsec device attributed: Error = %x\",\n+\t\t\t retcode);\n+\t\tgoto init_error;\n+\t}\n \tsprintf(dev->data->name, \"dpsec-%u\", hw_id);\n \n+\tinternals->max_nb_queue_pairs = attr.num_tx_queues;\n+\tdev->data->nb_queue_pairs = internals->max_nb_queue_pairs;\n+\tinternals->hw = dpseci;\n+\tinternals->token = token;\n \n \tPMD_INIT_LOG(DEBUG, \"driver %s: created\\n\", dev->data->name);\n \treturn 0;\n@@ -133,6 +1469,7 @@ static struct rte_cryptodev_driver rte_dpaa2_sec_pmd = {\n \t},\n \t.cryptodev_init = dpaa2_sec_dev_init,\n \t.cryptodev_uninit = dpaa2_sec_uninit,\n+\t.dev_private_size = sizeof(struct dpaa2_sec_dev_private),\n };\n \n RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_DPAA2_SEC_PMD, rte_dpaa2_sec_pmd.pci_drv);\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\nnew file mode 100644\nindex 0000000..01fae77\n--- /dev/null\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n@@ -0,0 +1,516 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n+ * Copyright (c) 2016 NXP. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_DPAA2_SEC_PMD_PRIVATE_H_\n+#define _RTE_DPAA2_SEC_PMD_PRIVATE_H_\n+\n+#define MAX_QUEUES\t\t64\n+#define MAX_DESC_SIZE\t\t64\n+/** private data structure for each DPAA2_SEC device */\n+struct dpaa2_sec_dev_private {\n+\tvoid *mc_portal; /**< MC Portal for configuring this device */\n+\tvoid *hw; /**< Hardware handle for this device.Used by NADK framework */\n+\tint32_t hw_id; /**< An unique ID of this device instance */\n+\tint32_t vfio_fd; /**< File descriptor received via VFIO */\n+\tuint16_t token; /**< Token required by DPxxx objects */\n+\tunsigned max_nb_queue_pairs;\n+\n+\tunsigned max_nb_sessions;\n+\t/**< Max number of sessions supported by device */\n+};\n+\n+struct dpaa2_sec_qp {\n+\tstruct dpaa2_queue rx_vq;\n+\tstruct dpaa2_queue tx_vq;\n+};\n+\n+enum shr_desc_type {\n+\tDESC_UPDATE,\n+\tDESC_FINAL,\n+\tDESC_INITFINAL,\n+};\n+\n+#define DIR_ENC 1\n+#define DIR_DEC 0\n+\n+/* SEC Flow Context Descriptor */\n+struct sec_flow_context {\n+\t/* word 0 */\n+\tuint16_t word0_sdid;\t\t/* 11-0 SDID */\n+\tuint16_t word0_res;\t\t/* 31-12 reserved */\n+\n+\t/* word 1 */\n+\tuint8_t word1_sdl;\t\t/* 5-0 SDL */\n+\t\t\t\t\t/* 7-6 reserved */\n+\n+\tuint8_t word1_bits_15_8; /* 11-8 CRID */\n+\t\t\t\t\t/* 14-12 reserved */\n+\t\t\t\t\t/* 15 CRJD */\n+\n+\tuint8_t word1_bits23_16;\t/* 16 EWS */\n+\t\t\t\t\t/* 17 DAC */\n+\t\t\t\t\t/* 18,19,20 ? */\n+\t\t\t\t\t/* 23-21 reserved */\n+\n+\tuint8_t word1_bits31_24;\t/* 24 RSC */\n+\t\t\t\t\t/* 25 RBMT */\n+\t\t\t\t\t/* 31-26 reserved */\n+\n+\t/* word 2 RFLC[31-0] */\n+\tuint32_t word2_rflc_31_0;\n+\n+\t/* word 3 RFLC[63-32] */\n+\tuint32_t word3_rflc_63_32;\n+\n+\t/* word 4 */\n+\tuint16_t word4_iicid;\t\t/* 15-0 IICID */\n+\tuint16_t word4_oicid;\t\t/* 31-16 OICID */\n+\n+\t/* word 5 */\n+\tuint32_t word5_ofqid:24;\t\t/* 23-0 OFQID */\n+\tuint32_t word5_31_24:8;\n+\t\t\t\t\t/* 24 OSC */\n+\t\t\t\t\t/* 25 OBMT */\n+\t\t\t\t\t/* 29-26 reserved */\n+\t\t\t\t\t/* 31-30 ICR */\n+\n+\t/* word 6 */\n+\tuint32_t word6_oflc_31_0;\n+\n+\t/* word 7 */\n+\tuint32_t word7_oflc_63_32;\n+\n+\t/* Word 8-15 storage profiles */\n+\tuint16_t dl;\t\t\t/**< DataLength(correction) */\n+\tuint16_t reserved;\t\t/**< reserved */\n+\tuint16_t dhr;\t\t\t/**< DataHeadRoom(correction) */\n+\tuint16_t mode_bits;\t\t/**< mode bits */\n+\tuint16_t bpv0;\t\t\t/**< buffer pool0 valid */\n+\tuint16_t bpid0;\t\t\t/**< Bypass Memory Translation */\n+\tuint16_t bpv1;\t\t\t/**< buffer pool1 valid */\n+\tuint16_t bpid1;\t\t\t/**< Bypass Memory Translation */\n+\tuint64_t word_12_15[2];\t\t/**< word 12-15 are reserved */\n+};\n+\n+struct sec_flc_desc {\n+\tstruct sec_flow_context flc;\n+\tuint32_t desc[MAX_DESC_SIZE];\n+};\n+\n+struct ctxt_priv {\n+\tstruct sec_flc_desc flc_desc[0];\n+};\n+\n+enum dpaa2_sec_op_type {\n+\tDPAA2_SEC_NONE, /*!< No Cipher operations*/\n+\tDPAA2_SEC_CIPHER,/*!< CIPHER operations */\n+\tDPAA2_SEC_AUTH, /*!< Authentication Operations */\n+\tDPAA2_SEC_CIPHER_HASH, /*!< Authenticated Encryption with associated data */\n+\tDPAA2_SEC_HASH_CIPHER, /*!< Encryption with Authenticated associated data */\n+\tDPAA2_SEC_IPSEC, /*!< IPSEC protocol operations*/\n+\tDPAA2_SEC_PDCP, /*!< PDCP protocol operations*/\n+\tDPAA2_SEC_PKC, /*!< Public Key Cryptographic Operations */\n+\tDPAA2_SEC_MAX\n+};\n+\n+struct dpaa2_sec_cipher_ctxt {\n+\tstruct {\n+\t\tuint8_t *data;\n+\t\tuint16_t length;\n+\t} iv;\t/**< Initialisation vector parameters */\n+\tuint8_t *init_counter; /*!< Set initial counter for CTR mode */\n+};\n+\n+struct dpaa2_sec_auth_ctxt {\n+\tuint8_t trunc_len; /*!< Length for output ICV, should\n+\t\t\t\t\t * be 0 if no truncation required */\n+};\n+\n+struct dpaa2_sec_aead_ctxt {\n+\tstruct {\n+\t\tuint8_t *data;\n+\t\tuint16_t length;\n+\t} iv;\t/**< Initialisation vector parameters */\n+\tuint16_t auth_only_len; /*!< Length of data for Auth only */\n+\tuint8_t auth_cipher_text; /**< Authenticate/cipher ordering */\n+\tuint8_t trunc_len; /*!< Length for output ICV, should\n+\t\t\t\t\t * be 0 if no truncation required */\n+};\n+\n+typedef struct dpaa2_sec_session_entry {\n+\tvoid *ctxt;\n+\tuint8_t ctxt_type;\n+\tuint8_t dir; /*!< Operation Direction */\n+\tenum rte_crypto_cipher_algorithm cipher_alg; /*!< Cipher Algorithm*/\n+\tenum rte_crypto_auth_algorithm auth_alg; /*!< Authentication Algorithm*/\n+\tstruct {\n+\t\tuint8_t *data;\t/**< pointer to key data */\n+\t\tsize_t length;\t/**< key length in bytes */\n+\t} cipher_key;\n+\tstruct {\n+\t\tuint8_t *data;\t/**< pointer to key data */\n+\t\tsize_t length;\t/**< key length in bytes */\n+\t} auth_key;\n+\tuint8_t status;\n+\tunion {\n+\t\tstruct dpaa2_sec_cipher_ctxt cipher_ctxt;\n+\t\tstruct dpaa2_sec_auth_ctxt auth_ctxt;\n+\t\tstruct dpaa2_sec_aead_ctxt aead_ctxt;\n+/*\t\tstruct nadk_ipsec_ctxt ipsec_ctxt;\n+\t\tstruct nadk_pdcp_ctxt pdcp_ctxt;\n+\t\tstruct nadk_null_sec_ctxt null_sec_ctxt;*/\n+\t} ext_params;\n+} dpaa2_sec_session;\n+\n+static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = {\n+\t{\t/* MD5 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_MD5_HMAC,\n+\t\t\t\t.block_size = 64,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 64,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.aad_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA1 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,\n+\t\t\t\t.block_size = 64,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 64,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 20,\n+\t\t\t\t\t.max = 20,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.aad_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA224 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,\n+\t\t\t\t.block_size = 64,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 64,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 28,\n+\t\t\t\t\t.max = 28,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.aad_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA256 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,\n+\t\t\t\t.block_size = 64,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 64,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t\t.min = 32,\n+\t\t\t\t\t\t.max = 32,\n+\t\t\t\t\t\t.increment = 0\n+\t\t\t\t\t},\n+\t\t\t\t\t.aad_size = { 0 }\n+\t\t\t\t}, }\n+\t\t\t}, }\n+\t\t},\n+\t{\t/* SHA384 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,\n+\t\t\t\t.block_size = 128,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 128,\n+\t\t\t\t\t.max = 128,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 48,\n+\t\t\t\t\t.max = 48,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.aad_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* SHA512 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,\n+\t\t\t\t.block_size = 128,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 128,\n+\t\t\t\t\t.max = 128,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 64,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.aad_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* AES XCBC MAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.aad_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* AES GCM (AUTH) */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_AES_GCM,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 4\n+\t\t\t\t},\n+\t\t\t\t.aad_size = {\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 12,\n+\t\t\t\t\t.increment = 4\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* AES CBC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CBC,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* AES CTR */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CTR,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* AES GCM (CIPHER) */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_GCM,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t},\n+\n+\t{\t/* 3DES CBC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_3DES_CBC,\n+\t\t\t\t.block_size = 8,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 24,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 8,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* 3DES CTR */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_3DES_CTR,\n+\t\t\t\t.block_size = 8,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 24,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 8,\n+\t\t\t\t\t.max = 8,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* SNOW3G (UIA2) */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 4,\n+\t\t\t\t\t.max = 4,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.aad_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t},\n+\t{\t/* SNOW3G (UEA2) */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t},\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+#endif /* _RTE_DPAA2_SEC_PMD_PRIVATE_H_ */\ndiff --git a/drivers/net/dpaa2/base/dpaa2_hw_pvt.h b/drivers/net/dpaa2/base/dpaa2_hw_pvt.h\nindex a1afa23..ee3fdc9 100644\n--- a/drivers/net/dpaa2/base/dpaa2_hw_pvt.h\n+++ b/drivers/net/dpaa2/base/dpaa2_hw_pvt.h\n@@ -140,8 +140,10 @@ struct qbman_fle {\n } while (0)\n #define DPAA2_SET_FD_LEN(fd, length)\tfd->simple.len = length\n #define DPAA2_SET_FD_BPID(fd, bpid)\t(fd->simple.bpid_offset |= bpid)\n+#define DPAA2_SET_FD_IVP(fd) ((fd->simple.bpid_offset |= 0x00004000))\n #define DPAA2_SET_FD_OFFSET(fd, offset)\t\\\n \t((fd->simple.bpid_offset |= (uint32_t)(offset) << 16))\n+#define DPAA2_SET_FD_INTERNAL_JD(fd, len) fd->simple.frc = (0x80000000 | (len))\n #define DPAA2_RESET_FD_CTRL(fd)\tfd->simple.ctrl = 0\n \n #define\tDPAA2_SET_FD_ASAL(fd, asal)\t(fd->simple.ctrl |= (asal << 16))\n@@ -149,12 +151,32 @@ struct qbman_fle {\n \tfd->simple.flc_lo = lower_32_bits((uint64_t)addr);\t\\\n \tfd->simple.flc_hi = upper_32_bits((uint64_t)addr);\t\\\n } while (0)\n+#define DPAA2_SET_FLE_INTERNAL_JD(fle, len) (fle->frc = (0x80000000 | (len)))\n+#define DPAA2_GET_FLE_ADDR(fle)\t\t\t\t\t\\\n+\t(uint64_t)((((uint64_t)(fle->addr_hi)) << 32) + fle->addr_lo)\n+#define DPAA2_SET_FLE_ADDR(fle, addr) do { \\\n+\tfle->addr_lo = lower_32_bits((uint64_t)addr); \\\n+\tfle->addr_hi = upper_32_bits((uint64_t)addr);\t \\\n+} while (0)\n+#define DPAA2_SET_FLE_OFFSET(fle, offset) \\\n+\t((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)\n+#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid)\n+#define DPAA2_GET_FLE_BPID(fle, bpid) (fle->fin_bpid_offset & 0x000000ff)\n+#define DPAA2_SET_FLE_FIN(fle)\t(fle->fin_bpid_offset |= (uint64_t)1 << 31)\n+#define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))\n+#define DPAA2_SET_FD_COMPOUND_FMT(fd)\t\\\n+\t(fd->simple.bpid_offset |= (uint32_t)1 << 28)\n #define DPAA2_GET_FD_ADDR(fd)\t\\\n ((uint64_t)((((uint64_t)(fd->simple.addr_hi)) << 32) + fd->simple.addr_lo))\n \n #define DPAA2_GET_FD_LEN(fd)\t(fd->simple.len)\n #define DPAA2_GET_FD_BPID(fd)\t((fd->simple.bpid_offset & 0x00003FFF))\n+#define DPAA2_GET_FD_IVP(fd) ((fd->simple.bpid_offset & 0x00004000) >> 14)\n #define DPAA2_GET_FD_OFFSET(fd)\t((fd->simple.bpid_offset & 0x0FFF0000) >> 16)\n+#define DPAA2_SET_FLE_SG_EXT(fle) (fle->fin_bpid_offset |= (uint64_t)1 << 29)\n+#define DPAA2_IS_SET_FLE_SG_EXT(fle)\t\\\n+\t((fle->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)\n+\n #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \\\n \t((struct rte_mbuf *)((uint64_t)buf - meta_data_size))\n \n@@ -207,6 +229,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)\n */\n \n #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) (mbuf->buf_physaddr)\n+#define DPAA2_OP_VADDR_TO_IOVA(op) (op->phys_addr)\n \n /**\n * macro to convert Virtual address to IOVA\n@@ -227,6 +250,8 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)\n #else\t/* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */\n \n #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) (mbuf->buf_addr)\n+#define DPAA2_OP_VADDR_TO_IOVA(op) (op)\n+\n #define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)\n #define DPAA2_IOVA_TO_VADDR(_iova) (_iova)\n #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)\n", "prefixes": [ "dpdk-dev", "6/8" ] }