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GET /api/patches/17119/?format=api
{ "id": 17119, "url": "http://patches.dpdk.org/api/patches/17119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1479740470-6723-17-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1479740470-6723-17-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1479740470-6723-17-git-send-email-arybchenko@solarflare.com", "date": "2016-11-21T15:00:30", "name": "[dpdk-dev,16/56] net/sfc: import libefx PHY statistics support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "8e7d11b25ce81f3da06a6fc9ae7a39b79e1960ff", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1479740470-6723-17-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/17119/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/17119/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 7FA7DD4B8;\n\tMon, 21 Nov 2016 16:02:52 +0100 (CET)", "from nbfkord-smmo02.seg.att.com (nbfkord-smmo02.seg.att.com\n\t[209.65.160.78]) by dpdk.org (Postfix) with ESMTP id DEAF9376D\n\tfor <dev@dpdk.org>; Mon, 21 Nov 2016 16:01:31 +0100 (CET)", "from unknown [12.187.104.26]\n\tby nbfkord-smmo02.seg.att.com(mxl_mta-7.2.4-7) with SMTP id\n\tb4c03385.0.1541294.00-2325.3424199.nbfkord-smmo02.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tMon, 21 Nov 2016 15:01:32 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 21 Nov 2016 07:01:21 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 21 Nov 2016 07:01:21 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1Ksw007146 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:20 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1J37006765 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:20 GMT" ], "X-MXL-Hash": "58330c4c3508a01a-b6b3204b95cd25f78bbbed9b58ae44a343b38b34", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "Date": "Mon, 21 Nov 2016 15:00:30 +0000", "Message-ID": "<1479740470-6723-17-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>", "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-AnalysisOut": [ "[v=2.1 cv=UI/baXry c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==]", "[:17 a=L24OOQBejmoA:10 a=zRKbQ67AAAAA:8 a=ENGxld5z3m_8FbI2b]", "[i4A:9 a=nULaPGwmIRdVIH-r:21 a=Y78o92se0G-RtxKf:21 a=V2Ta2N]", "[7SAFb-8KKX:21 a=PA03WX8tBzeizutn5_OT:22]" ], "X-Spam": "[F=0.5007354083; CM=0.500; S=0.500(2015072901)]", "X-MAIL-FROM": "<arybchenko@solarflare.com>", "X-SOURCE-IP": "[12.187.104.26]", "Subject": "[dpdk-dev] [PATCH 16/56] net/sfc: import libefx PHY statistics\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "EFSYS_OPT_PHY_STATS should be enabled to use it.\n\nFrom Solarflare Communications Inc.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/efx/base/ef10_impl.h | 10 +++\n drivers/net/sfc/efx/base/ef10_phy.c | 17 ++++\n drivers/net/sfc/efx/base/efx.h | 80 ++++++++++++++++++\n drivers/net/sfc/efx/base/efx_check.h | 7 ++\n drivers/net/sfc/efx/base/efx_impl.h | 4 +\n drivers/net/sfc/efx/base/efx_mcdi.c | 5 ++\n drivers/net/sfc/efx/base/efx_phy.c | 93 +++++++++++++++++++++\n drivers/net/sfc/efx/base/siena_impl.h | 18 ++++\n drivers/net/sfc/efx/base/siena_nic.c | 6 ++\n drivers/net/sfc/efx/base/siena_phy.c | 152 ++++++++++++++++++++++++++++++++++\n 10 files changed, 392 insertions(+)", "diff": "diff --git a/drivers/net/sfc/efx/base/ef10_impl.h b/drivers/net/sfc/efx/base/ef10_impl.h\nindex e1d2903..e847c22 100644\n--- a/drivers/net/sfc/efx/base/ef10_impl.h\n+++ b/drivers/net/sfc/efx/base/ef10_impl.h\n@@ -352,6 +352,16 @@ ef10_phy_oui_get(\n \t__in\t\tefx_nic_t *enp,\n \t__out\t\tuint32_t *ouip);\n \n+#if EFSYS_OPT_PHY_STATS\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+ef10_phy_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_PHY_NSTATS)\tuint32_t *stat);\n+\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n+\n #if EFSYS_OPT_BIST\n \n extern\t__checkReturn\t\tefx_rc_t\ndiff --git a/drivers/net/sfc/efx/base/ef10_phy.c b/drivers/net/sfc/efx/base/ef10_phy.c\nindex c7e584b..b15b693 100644\n--- a/drivers/net/sfc/efx/base/ef10_phy.c\n+++ b/drivers/net/sfc/efx/base/ef10_phy.c\n@@ -394,6 +394,23 @@ ef10_phy_oui_get(\n \treturn (ENOTSUP);\n }\n \n+#if EFSYS_OPT_PHY_STATS\n+\n+\t__checkReturn\t\t\t\tefx_rc_t\n+ef10_phy_stats_update(\n+\t__in\t\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_PHY_NSTATS)\t\tuint32_t *stat)\n+{\n+\t/* TBD: no stats support in firmware yet */\n+\t_NOTE(ARGUNUSED(enp, esmp))\n+\tmemset(stat, 0, EFX_PHY_NSTATS * sizeof (*stat));\n+\n+\treturn (0);\n+}\n+\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n+\n #if EFSYS_OPT_BIST\n \n \t__checkReturn\t\tefx_rc_t\ndiff --git a/drivers/net/sfc/efx/base/efx.h b/drivers/net/sfc/efx/base/efx.h\nindex 6dd5a8e..02526cd 100644\n--- a/drivers/net/sfc/efx/base/efx.h\n+++ b/drivers/net/sfc/efx/base/efx.h\n@@ -548,6 +548,80 @@ efx_phy_module_get_info(\n \t__in\t\t\t\tuint8_t len,\n \t__out_bcount(len)\t\tuint8_t *data);\n \n+#if EFSYS_OPT_PHY_STATS\n+\n+/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */\n+typedef enum efx_phy_stat_e {\n+\tEFX_PHY_STAT_OUI,\n+\tEFX_PHY_STAT_PMA_PMD_LINK_UP,\n+\tEFX_PHY_STAT_PMA_PMD_RX_FAULT,\n+\tEFX_PHY_STAT_PMA_PMD_TX_FAULT,\n+\tEFX_PHY_STAT_PMA_PMD_REV_A,\n+\tEFX_PHY_STAT_PMA_PMD_REV_B,\n+\tEFX_PHY_STAT_PMA_PMD_REV_C,\n+\tEFX_PHY_STAT_PMA_PMD_REV_D,\n+\tEFX_PHY_STAT_PCS_LINK_UP,\n+\tEFX_PHY_STAT_PCS_RX_FAULT,\n+\tEFX_PHY_STAT_PCS_TX_FAULT,\n+\tEFX_PHY_STAT_PCS_BER,\n+\tEFX_PHY_STAT_PCS_BLOCK_ERRORS,\n+\tEFX_PHY_STAT_PHY_XS_LINK_UP,\n+\tEFX_PHY_STAT_PHY_XS_RX_FAULT,\n+\tEFX_PHY_STAT_PHY_XS_TX_FAULT,\n+\tEFX_PHY_STAT_PHY_XS_ALIGN,\n+\tEFX_PHY_STAT_PHY_XS_SYNC_A,\n+\tEFX_PHY_STAT_PHY_XS_SYNC_B,\n+\tEFX_PHY_STAT_PHY_XS_SYNC_C,\n+\tEFX_PHY_STAT_PHY_XS_SYNC_D,\n+\tEFX_PHY_STAT_AN_LINK_UP,\n+\tEFX_PHY_STAT_AN_MASTER,\n+\tEFX_PHY_STAT_AN_LOCAL_RX_OK,\n+\tEFX_PHY_STAT_AN_REMOTE_RX_OK,\n+\tEFX_PHY_STAT_CL22EXT_LINK_UP,\n+\tEFX_PHY_STAT_SNR_A,\n+\tEFX_PHY_STAT_SNR_B,\n+\tEFX_PHY_STAT_SNR_C,\n+\tEFX_PHY_STAT_SNR_D,\n+\tEFX_PHY_STAT_PMA_PMD_SIGNAL_A,\n+\tEFX_PHY_STAT_PMA_PMD_SIGNAL_B,\n+\tEFX_PHY_STAT_PMA_PMD_SIGNAL_C,\n+\tEFX_PHY_STAT_PMA_PMD_SIGNAL_D,\n+\tEFX_PHY_STAT_AN_COMPLETE,\n+\tEFX_PHY_STAT_PMA_PMD_REV_MAJOR,\n+\tEFX_PHY_STAT_PMA_PMD_REV_MINOR,\n+\tEFX_PHY_STAT_PMA_PMD_REV_MICRO,\n+\tEFX_PHY_STAT_PCS_FW_VERSION_0,\n+\tEFX_PHY_STAT_PCS_FW_VERSION_1,\n+\tEFX_PHY_STAT_PCS_FW_VERSION_2,\n+\tEFX_PHY_STAT_PCS_FW_VERSION_3,\n+\tEFX_PHY_STAT_PCS_FW_BUILD_YY,\n+\tEFX_PHY_STAT_PCS_FW_BUILD_MM,\n+\tEFX_PHY_STAT_PCS_FW_BUILD_DD,\n+\tEFX_PHY_STAT_PCS_OP_MODE,\n+\tEFX_PHY_NSTATS\n+} efx_phy_stat_t;\n+\n+/* END MKCONFIG GENERATED PhyHeaderStatsBlock */\n+\n+#if EFSYS_OPT_NAMES\n+\n+extern\t\t\t\t\tconst char *\n+efx_phy_stat_name(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefx_phy_stat_t stat);\n+\n+#endif\t/* EFSYS_OPT_NAMES */\n+\n+#define\tEFX_PHY_STATS_SIZE 0x100\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+efx_phy_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_PHY_NSTATS)\tuint32_t *stat);\n+\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n+\n \n #if EFSYS_OPT_BIST\n \n@@ -671,8 +745,14 @@ typedef struct efx_nic_cfg_s {\n #if EFSYS_OPT_PHY_FLAGS\n \tuint32_t\t\tenc_phy_flags_mask;\n #endif\t/* EFSYS_OPT_PHY_FLAGS */\n+#if EFSYS_OPT_PHY_STATS\n+\tuint64_t\t\tenc_phy_stat_mask;\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n #if EFSYS_OPT_MCDI\n \tuint8_t\t\t\tenc_mcdi_mdio_channel;\n+#if EFSYS_OPT_PHY_STATS\n+\tuint32_t\t\tenc_mcdi_phy_stat_mask;\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n #endif\t/* EFSYS_OPT_MCDI */\n #if EFSYS_OPT_BIST\n \tuint32_t\t\tenc_bist_mask;\ndiff --git a/drivers/net/sfc/efx/base/efx_check.h b/drivers/net/sfc/efx/base/efx_check.h\nindex 68c01f3..adda531 100644\n--- a/drivers/net/sfc/efx/base/efx_check.h\n+++ b/drivers/net/sfc/efx/base/efx_check.h\n@@ -201,6 +201,13 @@\n # error \"PHY_SFX7101 is obsolete and is not supported.\"\n #endif\n \n+#if EFSYS_OPT_PHY_STATS\n+/* Support PHY statistics */\n+# if !EFSYS_OPT_SIENA\n+# error \"PHY_STATS requires SIENA\"\n+# endif\n+#endif /* EFSYS_OPT_PHY_STATS */\n+\n #ifdef EFSYS_OPT_PHY_TXC43128\n # error \"PHY_TXC43128 is obsolete and is not supported.\"\n #endif\ndiff --git a/drivers/net/sfc/efx/base/efx_impl.h b/drivers/net/sfc/efx/base/efx_impl.h\nindex 489fcbc..2b81768 100644\n--- a/drivers/net/sfc/efx/base/efx_impl.h\n+++ b/drivers/net/sfc/efx/base/efx_impl.h\n@@ -182,6 +182,10 @@ typedef struct efx_phy_ops_s {\n \tefx_rc_t\t(*epo_reconfigure)(efx_nic_t *);\n \tefx_rc_t\t(*epo_verify)(efx_nic_t *);\n \tefx_rc_t\t(*epo_oui_get)(efx_nic_t *, uint32_t *);\n+#if EFSYS_OPT_PHY_STATS\n+\tefx_rc_t\t(*epo_stats_update)(efx_nic_t *, efsys_mem_t *,\n+\t\t\t\t\t uint32_t *);\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n #if EFSYS_OPT_BIST\n \tefx_rc_t\t(*epo_bist_enable_offline)(efx_nic_t *);\n \tefx_rc_t\t(*epo_bist_start)(efx_nic_t *, efx_bist_type_t);\ndiff --git a/drivers/net/sfc/efx/base/efx_mcdi.c b/drivers/net/sfc/efx/base/efx_mcdi.c\nindex b070887..8b8b137 100644\n--- a/drivers/net/sfc/efx/base/efx_mcdi.c\n+++ b/drivers/net/sfc/efx/base/efx_mcdi.c\n@@ -1435,6 +1435,11 @@ efx_mcdi_get_phy_cfg(\n \tencp->enc_mcdi_mdio_channel =\n \t\t(uint8_t)MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_CHANNEL);\n \n+#if EFSYS_OPT_PHY_STATS\n+\tencp->enc_mcdi_phy_stat_mask =\n+\t\tMCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_STATS_MASK);\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n+\n #if EFSYS_OPT_BIST\n \tencp->enc_bist_mask = 0;\n \tif (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS,\ndiff --git a/drivers/net/sfc/efx/base/efx_phy.c b/drivers/net/sfc/efx/base/efx_phy.c\nindex f07f127..20debd3 100644\n--- a/drivers/net/sfc/efx/base/efx_phy.c\n+++ b/drivers/net/sfc/efx/base/efx_phy.c\n@@ -39,6 +39,9 @@ static const efx_phy_ops_t\t__efx_phy_siena_ops = {\n \tsiena_phy_reconfigure,\t\t/* epo_reconfigure */\n \tsiena_phy_verify,\t\t/* epo_verify */\n \tsiena_phy_oui_get,\t\t/* epo_oui_get */\n+#if EFSYS_OPT_PHY_STATS\n+\tsiena_phy_stats_update,\t\t/* epo_stats_update */\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n #if EFSYS_OPT_BIST\n \tNULL,\t\t\t\t/* epo_bist_enable_offline */\n \tsiena_phy_bist_start,\t\t/* epo_bist_start */\n@@ -55,6 +58,9 @@ static const efx_phy_ops_t\t__efx_phy_ef10_ops = {\n \tef10_phy_reconfigure,\t\t/* epo_reconfigure */\n \tef10_phy_verify,\t\t/* epo_verify */\n \tef10_phy_oui_get,\t\t/* epo_oui_get */\n+#if EFSYS_OPT_PHY_STATS\n+\tef10_phy_stats_update,\t\t/* epo_stats_update */\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n #if EFSYS_OPT_BIST\n \tef10_bist_enable_offline,\t/* epo_bist_enable_offline */\n \tef10_bist_start,\t\t/* epo_bist_start */\n@@ -277,6 +283,93 @@ efx_phy_module_get_info(\n \treturn (rc);\n }\n \n+#if EFSYS_OPT_PHY_STATS\n+\n+#if EFSYS_OPT_NAMES\n+\n+/* START MKCONFIG GENERATED PhyStatNamesBlock af9ffa24da3bc100 */\n+static const char * const __efx_phy_stat_name[] = {\n+\t\"oui\",\n+\t\"pma_pmd_link_up\",\n+\t\"pma_pmd_rx_fault\",\n+\t\"pma_pmd_tx_fault\",\n+\t\"pma_pmd_rev_a\",\n+\t\"pma_pmd_rev_b\",\n+\t\"pma_pmd_rev_c\",\n+\t\"pma_pmd_rev_d\",\n+\t\"pcs_link_up\",\n+\t\"pcs_rx_fault\",\n+\t\"pcs_tx_fault\",\n+\t\"pcs_ber\",\n+\t\"pcs_block_errors\",\n+\t\"phy_xs_link_up\",\n+\t\"phy_xs_rx_fault\",\n+\t\"phy_xs_tx_fault\",\n+\t\"phy_xs_align\",\n+\t\"phy_xs_sync_a\",\n+\t\"phy_xs_sync_b\",\n+\t\"phy_xs_sync_c\",\n+\t\"phy_xs_sync_d\",\n+\t\"an_link_up\",\n+\t\"an_master\",\n+\t\"an_local_rx_ok\",\n+\t\"an_remote_rx_ok\",\n+\t\"cl22ext_link_up\",\n+\t\"snr_a\",\n+\t\"snr_b\",\n+\t\"snr_c\",\n+\t\"snr_d\",\n+\t\"pma_pmd_signal_a\",\n+\t\"pma_pmd_signal_b\",\n+\t\"pma_pmd_signal_c\",\n+\t\"pma_pmd_signal_d\",\n+\t\"an_complete\",\n+\t\"pma_pmd_rev_major\",\n+\t\"pma_pmd_rev_minor\",\n+\t\"pma_pmd_rev_micro\",\n+\t\"pcs_fw_version_0\",\n+\t\"pcs_fw_version_1\",\n+\t\"pcs_fw_version_2\",\n+\t\"pcs_fw_version_3\",\n+\t\"pcs_fw_build_yy\",\n+\t\"pcs_fw_build_mm\",\n+\t\"pcs_fw_build_dd\",\n+\t\"pcs_op_mode\",\n+};\n+\n+/* END MKCONFIG GENERATED PhyStatNamesBlock */\n+\n+\t\t\t\t\tconst char *\n+efx_phy_stat_name(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefx_phy_stat_t type)\n+{\n+\t_NOTE(ARGUNUSED(enp))\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);\n+\n+\treturn (__efx_phy_stat_name[type]);\n+}\n+\n+#endif\t/* EFSYS_OPT_NAMES */\n+\n+\t__checkReturn\t\t\tefx_rc_t\n+efx_phy_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_PHY_NSTATS)\tuint32_t *stat)\n+{\n+\tefx_port_t *epp = &(enp->en_port);\n+\tconst efx_phy_ops_t *epop = epp->ep_epop;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);\n+\n+\treturn (epop->epo_stats_update(enp, esmp, stat));\n+}\n+\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n+\n \n #if EFSYS_OPT_BIST\n \ndiff --git a/drivers/net/sfc/efx/base/siena_impl.h b/drivers/net/sfc/efx/base/siena_impl.h\nindex bdaa4a3..fc01205 100644\n--- a/drivers/net/sfc/efx/base/siena_impl.h\n+++ b/drivers/net/sfc/efx/base/siena_impl.h\n@@ -170,6 +170,24 @@ siena_phy_oui_get(\n \t__in\t\tefx_nic_t *enp,\n \t__out\t\tuint32_t *ouip);\n \n+#if EFSYS_OPT_PHY_STATS\n+\n+extern\t\t\t\t\t\tvoid\n+siena_phy_decode_stats(\n+\t__in\t\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\t\tuint32_t vmask,\n+\t__in_opt\t\t\t\tefsys_mem_t *esmp,\n+\t__out_opt\t\t\t\tuint64_t *smaskp,\n+\t__inout_ecount_opt(EFX_PHY_NSTATS)\tuint32_t *stat);\n+\n+extern\t__checkReturn\t\t\tefx_rc_t\n+siena_phy_stats_update(\n+\t__in\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_PHY_NSTATS)\tuint32_t *stat);\n+\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n+\n #if EFSYS_OPT_BIST\n \n extern\t__checkReturn\t\tefx_rc_t\ndiff --git a/drivers/net/sfc/efx/base/siena_nic.c b/drivers/net/sfc/efx/base/siena_nic.c\nindex 2d079c2..135f705 100644\n--- a/drivers/net/sfc/efx/base/siena_nic.c\n+++ b/drivers/net/sfc/efx/base/siena_nic.c\n@@ -145,6 +145,12 @@ siena_phy_cfg(\n \tif ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)\n \t\tgoto fail1;\n \n+#if EFSYS_OPT_PHY_STATS\n+\t/* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */\n+\tsiena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,\n+\t\t\t NULL, &encp->enc_phy_stat_mask, NULL);\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n+\n \treturn (0);\n \n fail1:\ndiff --git a/drivers/net/sfc/efx/base/siena_phy.c b/drivers/net/sfc/efx/base/siena_phy.c\nindex 6451298..73690f1 100644\n--- a/drivers/net/sfc/efx/base/siena_phy.c\n+++ b/drivers/net/sfc/efx/base/siena_phy.c\n@@ -376,6 +376,158 @@ siena_phy_oui_get(\n \treturn (ENOTSUP);\n }\n \n+#if EFSYS_OPT_PHY_STATS\n+\n+#define\tSIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat,\t\t\\\n+\t\t\t _mc_record, _efx_record)\t\t\t\\\n+\tif ((_vmask) & (1ULL << (_mc_record))) {\t\t\t\\\n+\t\t(_smask) |= (1ULL << (_efx_record));\t\t\t\\\n+\t\tif ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) {\t\\\n+\t\t\tefx_dword_t dword;\t\t\t\t\\\n+\t\t\tEFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\\\n+\t\t\t(_stat)[_efx_record] =\t\t\t\t\\\n+\t\t\t\tEFX_DWORD_FIELD(dword, EFX_DWORD_0);\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t}\n+\n+#define\tSIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record)\t\\\n+\tSIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat,\t\t\\\n+\t\t\t MC_CMD_ ## _record,\t\t\t\t\\\n+\t\t\t EFX_PHY_STAT_ ## _record)\n+\n+\t\t\t\t\t\tvoid\n+siena_phy_decode_stats(\n+\t__in\t\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\t\tuint32_t vmask,\n+\t__in_opt\t\t\t\tefsys_mem_t *esmp,\n+\t__out_opt\t\t\t\tuint64_t *smaskp,\n+\t__inout_ecount_opt(EFX_PHY_NSTATS)\tuint32_t *stat)\n+{\n+\tuint64_t smask = 0;\n+\n+\t_NOTE(ARGUNUSED(enp))\n+\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI);\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP);\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT);\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT);\n+\n+\tif (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) {\n+\t\tsmask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) |\n+\t\t\t (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) |\n+\t\t\t (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) |\n+\t\t\t (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D));\n+\t\tif (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) {\n+\t\t\tefx_dword_t dword;\n+\t\t\tuint32_t sig;\n+\t\t\tEFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL,\n+\t\t\t\t\t&dword);\n+\t\t\tsig = EFX_DWORD_FIELD(dword, EFX_DWORD_0);\n+\t\t\tstat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1;\n+\t\t\tstat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1;\n+\t\t\tstat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1;\n+\t\t\tstat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1;\n+\t\t}\n+\t}\n+\n+\tSIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A,\n+\t\t\t EFX_PHY_STAT_SNR_A);\n+\tSIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B,\n+\t\t\t EFX_PHY_STAT_SNR_B);\n+\tSIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C,\n+\t\t\t EFX_PHY_STAT_SNR_C);\n+\tSIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D,\n+\t\t\t EFX_PHY_STAT_SNR_D);\n+\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP);\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT);\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT);\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER);\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS);\n+\n+\tSIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP,\n+\t\t\t EFX_PHY_STAT_PHY_XS_LINK_UP);\n+\tSIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT,\n+\t\t\t EFX_PHY_STAT_PHY_XS_RX_FAULT);\n+\tSIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT,\n+\t\t\t EFX_PHY_STAT_PHY_XS_TX_FAULT);\n+\tSIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN,\n+\t\t\t EFX_PHY_STAT_PHY_XS_ALIGN);\n+\n+\tif (vmask & (1 << MC_CMD_PHYXS_SYNC)) {\n+\t\tsmask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) |\n+\t\t\t (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) |\n+\t\t\t (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) |\n+\t\t\t (1 << EFX_PHY_STAT_PHY_XS_SYNC_D));\n+\t\tif (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) {\n+\t\t\tefx_dword_t dword;\n+\t\t\tuint32_t sync;\n+\t\t\tEFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword);\n+\t\t\tsync = EFX_DWORD_FIELD(dword, EFX_DWORD_0);\n+\t\t\tstat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;\n+\t\t\tstat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;\n+\t\t\tstat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;\n+\t\t\tstat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;\n+\t\t}\n+\t}\n+\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP);\n+\tSIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE);\n+\n+\tSIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP,\n+\t\t\t EFX_PHY_STAT_CL22EXT_LINK_UP);\n+\n+\tif (smaskp != NULL)\n+\t\t*smaskp = smask;\n+}\n+\n+\t__checkReturn\t\t\t\tefx_rc_t\n+siena_phy_stats_update(\n+\t__in\t\t\t\t\tefx_nic_t *enp,\n+\t__in\t\t\t\t\tefsys_mem_t *esmp,\n+\t__inout_ecount(EFX_PHY_NSTATS)\t\tuint32_t *stat)\n+{\n+\tefx_nic_cfg_t *encp = &(enp->en_nic_cfg);\n+\tuint32_t vmask = encp->enc_mcdi_phy_stat_mask;\n+\tuint64_t smask;\n+\tefx_mcdi_req_t req;\n+\tuint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN,\n+\t\t\t MC_CMD_PHY_STATS_OUT_DMA_LEN)];\n+\tefx_rc_t rc;\n+\n+\t(void) memset(payload, 0, sizeof (payload));\n+\treq.emr_cmd = MC_CMD_PHY_STATS;\n+\treq.emr_in_buf = payload;\n+\treq.emr_in_length = MC_CMD_PHY_STATS_IN_LEN;\n+\treq.emr_out_buf = payload;\n+\treq.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN;\n+\n+\tMCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO,\n+\t\t\t EFSYS_MEM_ADDR(esmp) & 0xffffffff);\n+\tMCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI,\n+\t\t\t EFSYS_MEM_ADDR(esmp) >> 32);\n+\n+\tefx_mcdi_execute(enp, &req);\n+\n+\tif (req.emr_rc != 0) {\n+\t\trc = req.emr_rc;\n+\t\tgoto fail1;\n+\t}\n+\tEFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN);\n+\n+\tsiena_phy_decode_stats(enp, vmask, esmp, &smask, stat);\n+\tEFSYS_ASSERT(smask == encp->enc_phy_stat_mask);\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (0);\n+}\n+\n+#endif\t/* EFSYS_OPT_PHY_STATS */\n+\n #if EFSYS_OPT_BIST\n \n \t__checkReturn\t\tefx_rc_t\n", "prefixes": [ "dpdk-dev", "16/56" ] }