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GET /api/patches/16567/?format=api
{ "id": 16567, "url": "http://patches.dpdk.org/api/patches/16567/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1476417604-22400-2-git-send-email-jianbo.liu@linaro.org/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1476417604-22400-2-git-send-email-jianbo.liu@linaro.org>", "list_archive_url": "https://inbox.dpdk.org/dev/1476417604-22400-2-git-send-email-jianbo.liu@linaro.org", "date": "2016-10-14T04:00:00", "name": "[dpdk-dev,v2,1/5] i40e: extract non-x86 specific code from vector driver", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "91fb29d72be6c51c152a491df98e4c223b763848", "submitter": { "id": 380, "url": "http://patches.dpdk.org/api/people/380/?format=api", "name": "Jianbo Liu", "email": "jianbo.liu@linaro.org" }, "delegate": { "id": 10, "url": "http://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1476417604-22400-2-git-send-email-jianbo.liu@linaro.org/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/16567/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/16567/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 0A6876CD6;\n\tFri, 14 Oct 2016 06:00:40 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.101.70])\n\tby dpdk.org (Postfix) with ESMTP id 53BAC6CD4\n\tfor <dev@dpdk.org>; Fri, 14 Oct 2016 06:00:38 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B3F222B;\n\tThu, 13 Oct 2016 21:00:37 -0700 (PDT)", "from Overdrive.asiapac.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\tBCAF93F21A; Thu, 13 Oct 2016 21:00:36 -0700 (PDT)" ], "From": "Jianbo Liu <jianbo.liu@linaro.org>", "To": "helin.zhang@intel.com, jingjing.wu@intel.com,\n\tjerin.jacob@caviumnetworks.com, dev@dpdk.org, qi.z.zhang@intel.com", "Cc": "Jianbo Liu <jianbo.liu@linaro.org>", "Date": "Fri, 14 Oct 2016 09:30:00 +0530", "Message-Id": "<1476417604-22400-2-git-send-email-jianbo.liu@linaro.org>", "X-Mailer": "git-send-email 2.4.11", "In-Reply-To": "<1476417604-22400-1-git-send-email-jianbo.liu@linaro.org>", "References": "<1472032425-16136-1-git-send-email-jianbo.liu@linaro.org>\n\t<1476417604-22400-1-git-send-email-jianbo.liu@linaro.org>", "Subject": "[dpdk-dev] [PATCH v2 1/5] i40e: extract non-x86 specific code from\n\tvector driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "move scalar code which does not use x86 intrinsic functions to new file\n\"i40e_rxtx_vec_common.h\", while keeping x86 code in i40e_rxtx_vec.c.\nThis allows the scalar code to to be shared among vector drivers for\ndifferent platforms.\n\nSigned-off-by: Jianbo Liu <jianbo.liu@linaro.org>\n---\n drivers/net/i40e/i40e_rxtx_vec.c | 196 +------------------------\n drivers/net/i40e/i40e_rxtx_vec_common.h | 251 ++++++++++++++++++++++++++++++++\n 2 files changed, 255 insertions(+), 192 deletions(-)\n create mode 100644 drivers/net/i40e/i40e_rxtx_vec_common.h", "diff": "diff --git a/drivers/net/i40e/i40e_rxtx_vec.c b/drivers/net/i40e/i40e_rxtx_vec.c\nindex 0ee0241..3607312 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec.c\n@@ -39,6 +39,7 @@\n #include \"base/i40e_type.h\"\n #include \"i40e_ethdev.h\"\n #include \"i40e_rxtx.h\"\n+#include \"i40e_rxtx_vec_common.h\"\n \n #include <tmmintrin.h>\n \n@@ -445,68 +446,6 @@ i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n \treturn _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);\n }\n \n-static inline uint16_t\n-reassemble_packets(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_bufs,\n-\t\t uint16_t nb_bufs, uint8_t *split_flags)\n-{\n-\tstruct rte_mbuf *pkts[RTE_I40E_VPMD_RX_BURST]; /*finished pkts*/\n-\tstruct rte_mbuf *start = rxq->pkt_first_seg;\n-\tstruct rte_mbuf *end = rxq->pkt_last_seg;\n-\tunsigned pkt_idx, buf_idx;\n-\n-\tfor (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {\n-\t\tif (end != NULL) {\n-\t\t\t/* processing a split packet */\n-\t\t\tend->next = rx_bufs[buf_idx];\n-\t\t\trx_bufs[buf_idx]->data_len += rxq->crc_len;\n-\n-\t\t\tstart->nb_segs++;\n-\t\t\tstart->pkt_len += rx_bufs[buf_idx]->data_len;\n-\t\t\tend = end->next;\n-\n-\t\t\tif (!split_flags[buf_idx]) {\n-\t\t\t\t/* it's the last packet of the set */\n-\t\t\t\tstart->hash = end->hash;\n-\t\t\t\tstart->ol_flags = end->ol_flags;\n-\t\t\t\t/* we need to strip crc for the whole packet */\n-\t\t\t\tstart->pkt_len -= rxq->crc_len;\n-\t\t\t\tif (end->data_len > rxq->crc_len) {\n-\t\t\t\t\tend->data_len -= rxq->crc_len;\n-\t\t\t\t} else {\n-\t\t\t\t\t/* free up last mbuf */\n-\t\t\t\t\tstruct rte_mbuf *secondlast = start;\n-\n-\t\t\t\t\twhile (secondlast->next != end)\n-\t\t\t\t\t\tsecondlast = secondlast->next;\n-\t\t\t\t\tsecondlast->data_len -= (rxq->crc_len -\n-\t\t\t\t\t\t\tend->data_len);\n-\t\t\t\t\tsecondlast->next = NULL;\n-\t\t\t\t\trte_pktmbuf_free_seg(end);\n-\t\t\t\t\tend = secondlast;\n-\t\t\t\t}\n-\t\t\t\tpkts[pkt_idx++] = start;\n-\t\t\t\tstart = end = NULL;\n-\t\t\t}\n-\t\t} else {\n-\t\t\t/* not processing a split packet */\n-\t\t\tif (!split_flags[buf_idx]) {\n-\t\t\t\t/* not a split packet, save and skip */\n-\t\t\t\tpkts[pkt_idx++] = rx_bufs[buf_idx];\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t\tend = start = rx_bufs[buf_idx];\n-\t\t\trx_bufs[buf_idx]->data_len += rxq->crc_len;\n-\t\t\trx_bufs[buf_idx]->pkt_len += rxq->crc_len;\n-\t\t}\n-\t}\n-\n-\t/* save the partial packet for next time */\n-\trxq->pkt_first_seg = start;\n-\trxq->pkt_last_seg = end;\n-\tmemcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));\n-\treturn pkt_idx;\n-}\n-\n /* vPMD receive routine that reassembles scattered packets\n * Notice:\n * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet\n@@ -572,73 +511,6 @@ vtx(volatile struct i40e_tx_desc *txdp,\n \t\tvtx1(txdp, *pkt, flags);\n }\n \n-static inline int __attribute__((always_inline))\n-i40e_tx_free_bufs(struct i40e_tx_queue *txq)\n-{\n-\tstruct i40e_tx_entry *txep;\n-\tuint32_t n;\n-\tuint32_t i;\n-\tint nb_free = 0;\n-\tstruct rte_mbuf *m, *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];\n-\n-\t/* check DD bits on threshold descriptor */\n-\tif ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &\n-\t\t\trte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=\n-\t\t\trte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))\n-\t\treturn 0;\n-\n-\tn = txq->tx_rs_thresh;\n-\n-\t /* first buffer to free from S/W ring is at index\n-\t * tx_next_dd - (tx_rs_thresh-1)\n-\t */\n-\ttxep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];\n-\tm = __rte_pktmbuf_prefree_seg(txep[0].mbuf);\n-\tif (likely(m != NULL)) {\n-\t\tfree[0] = m;\n-\t\tnb_free = 1;\n-\t\tfor (i = 1; i < n; i++) {\n-\t\t\tm = __rte_pktmbuf_prefree_seg(txep[i].mbuf);\n-\t\t\tif (likely(m != NULL)) {\n-\t\t\t\tif (likely(m->pool == free[0]->pool)) {\n-\t\t\t\t\tfree[nb_free++] = m;\n-\t\t\t\t} else {\n-\t\t\t\t\trte_mempool_put_bulk(free[0]->pool,\n-\t\t\t\t\t\t\t (void *)free,\n-\t\t\t\t\t\t\t nb_free);\n-\t\t\t\t\tfree[0] = m;\n-\t\t\t\t\tnb_free = 1;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t}\n-\t\trte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);\n-\t} else {\n-\t\tfor (i = 1; i < n; i++) {\n-\t\t\tm = __rte_pktmbuf_prefree_seg(txep[i].mbuf);\n-\t\t\tif (m != NULL)\n-\t\t\t\trte_mempool_put(m->pool, m);\n-\t\t}\n-\t}\n-\n-\t/* buffers were freed, update counters */\n-\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);\n-\ttxq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);\n-\tif (txq->tx_next_dd >= txq->nb_tx_desc)\n-\t\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n-\n-\treturn txq->tx_rs_thresh;\n-}\n-\n-static inline void __attribute__((always_inline))\n-tx_backlog_entry(struct i40e_tx_entry *txep,\n-\t\t struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < (int)nb_pkts; ++i)\n-\t\ttxep[i].mbuf = tx_pkts[i];\n-}\n-\n uint16_t\n i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t uint16_t nb_pkts)\n@@ -709,49 +581,13 @@ i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n void __attribute__((cold))\n i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)\n {\n-\tconst unsigned mask = rxq->nb_rx_desc - 1;\n-\tunsigned i;\n-\n-\tif (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)\n-\t\treturn;\n-\n-\t/* free all mbufs that are valid in the ring */\n-\tif (rxq->rxrearm_nb == 0) {\n-\t\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n-\t\t\tif (rxq->sw_ring[i].mbuf != NULL)\n-\t\t\t\trte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);\n-\t\t}\n-\t} else {\n-\t\tfor (i = rxq->rx_tail;\n-\t\t i != rxq->rxrearm_start;\n-\t\t i = (i + 1) & mask) {\n-\t\t\tif (rxq->sw_ring[i].mbuf != NULL)\n-\t\t\t\trte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);\n-\t\t}\n-\t}\n-\n-\trxq->rxrearm_nb = rxq->nb_rx_desc;\n-\n-\t/* set all entries to NULL */\n-\tmemset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);\n+\t_i40e_rx_queue_release_mbufs_vec(rxq);\n }\n \n int __attribute__((cold))\n i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)\n {\n-\tuintptr_t p;\n-\tstruct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */\n-\n-\tmb_def.nb_segs = 1;\n-\tmb_def.data_off = RTE_PKTMBUF_HEADROOM;\n-\tmb_def.port = rxq->port_id;\n-\trte_mbuf_refcnt_set(&mb_def, 1);\n-\n-\t/* prevent compiler reordering: rearm_data covers previous fields */\n-\trte_compiler_barrier();\n-\tp = (uintptr_t)&mb_def.rearm_data;\n-\trxq->mbuf_initializer = *(uint64_t *)p;\n-\treturn 0;\n+\treturn i40e_rxq_vec_setup_default(rxq);\n }\n \n int __attribute__((cold))\n@@ -764,34 +600,10 @@ int __attribute__((cold))\n i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)\n {\n #ifndef RTE_LIBRTE_IEEE1588\n-\tstruct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;\n-\tstruct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;\n-\n \t/* need SSE4.1 support */\n \tif (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))\n \t\treturn -1;\n-\n-#ifndef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE\n-\t/* whithout rx ol_flags, no VP flag report */\n-\tif (rxmode->hw_vlan_strip != 0 ||\n-\t rxmode->hw_vlan_extend != 0 ||\n-\t rxmode->hw_ip_checksum != 0)\n-\t\treturn -1;\n #endif\n \n-\t/* no fdir support */\n-\tif (fconf->mode != RTE_FDIR_MODE_NONE)\n-\t\treturn -1;\n-\n-\t /* - no csum error report support\n-\t * - no header split support\n-\t */\n-\tif (rxmode->header_split == 1)\n-\t\treturn -1;\n-\n-\treturn 0;\n-#else\n-\tRTE_SET_USED(dev);\n-\treturn -1;\n-#endif\n+\treturn i40e_rx_vec_dev_conf_condition_check_default(dev);\n }\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_common.h b/drivers/net/i40e/i40e_rxtx_vec_common.h\nnew file mode 100644\nindex 0000000..6cb5dce\n--- /dev/null\n+++ b/drivers/net/i40e/i40e_rxtx_vec_common.h\n@@ -0,0 +1,251 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _I40E_RXTX_VEC_COMMON_H_\n+#define _I40E_RXTX_VEC_COMMON_H_\n+#include <stdint.h>\n+#include <rte_ethdev.h>\n+#include <rte_malloc.h>\n+\n+#include \"i40e_ethdev.h\"\n+#include \"i40e_rxtx.h\"\n+\n+static inline uint16_t\n+reassemble_packets(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_bufs,\n+\t\t uint16_t nb_bufs, uint8_t *split_flags)\n+{\n+\tstruct rte_mbuf *pkts[RTE_I40E_VPMD_RX_BURST]; /*finished pkts*/\n+\tstruct rte_mbuf *start = rxq->pkt_first_seg;\n+\tstruct rte_mbuf *end = rxq->pkt_last_seg;\n+\tunsigned pkt_idx, buf_idx;\n+\n+\tfor (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {\n+\t\tif (end != NULL) {\n+\t\t\t/* processing a split packet */\n+\t\t\tend->next = rx_bufs[buf_idx];\n+\t\t\trx_bufs[buf_idx]->data_len += rxq->crc_len;\n+\n+\t\t\tstart->nb_segs++;\n+\t\t\tstart->pkt_len += rx_bufs[buf_idx]->data_len;\n+\t\t\tend = end->next;\n+\n+\t\t\tif (!split_flags[buf_idx]) {\n+\t\t\t\t/* it's the last packet of the set */\n+\t\t\t\tstart->hash = end->hash;\n+\t\t\t\tstart->ol_flags = end->ol_flags;\n+\t\t\t\t/* we need to strip crc for the whole packet */\n+\t\t\t\tstart->pkt_len -= rxq->crc_len;\n+\t\t\t\tif (end->data_len > rxq->crc_len) {\n+\t\t\t\t\tend->data_len -= rxq->crc_len;\n+\t\t\t\t} else {\n+\t\t\t\t\t/* free up last mbuf */\n+\t\t\t\t\tstruct rte_mbuf *secondlast = start;\n+\n+\t\t\t\t\twhile (secondlast->next != end)\n+\t\t\t\t\t\tsecondlast = secondlast->next;\n+\t\t\t\t\tsecondlast->data_len -= (rxq->crc_len -\n+\t\t\t\t\t\t\tend->data_len);\n+\t\t\t\t\tsecondlast->next = NULL;\n+\t\t\t\t\trte_pktmbuf_free_seg(end);\n+\t\t\t\t\tend = secondlast;\n+\t\t\t\t}\n+\t\t\t\tpkts[pkt_idx++] = start;\n+\t\t\t\tstart = end = NULL;\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* not processing a split packet */\n+\t\t\tif (!split_flags[buf_idx]) {\n+\t\t\t\t/* not a split packet, save and skip */\n+\t\t\t\tpkts[pkt_idx++] = rx_bufs[buf_idx];\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\tend = start = rx_bufs[buf_idx];\n+\t\t\trx_bufs[buf_idx]->data_len += rxq->crc_len;\n+\t\t\trx_bufs[buf_idx]->pkt_len += rxq->crc_len;\n+\t\t}\n+\t}\n+\n+\t/* save the partial packet for next time */\n+\trxq->pkt_first_seg = start;\n+\trxq->pkt_last_seg = end;\n+\tmemcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));\n+\treturn pkt_idx;\n+}\n+\n+static inline int __attribute__((always_inline))\n+i40e_tx_free_bufs(struct i40e_tx_queue *txq)\n+{\n+\tstruct i40e_tx_entry *txep;\n+\tuint32_t n;\n+\tuint32_t i;\n+\tint nb_free = 0;\n+\tstruct rte_mbuf *m, *free[RTE_I40E_TX_MAX_FREE_BUF_SZ];\n+\n+\t/* check DD bits on threshold descriptor */\n+\tif ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &\n+\t\t\trte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=\n+\t\t\trte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))\n+\t\treturn 0;\n+\n+\tn = txq->tx_rs_thresh;\n+\n+\t /* first buffer to free from S/W ring is at index\n+\t * tx_next_dd - (tx_rs_thresh-1)\n+\t */\n+\ttxep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];\n+\tm = __rte_pktmbuf_prefree_seg(txep[0].mbuf);\n+\tif (likely(m != NULL)) {\n+\t\tfree[0] = m;\n+\t\tnb_free = 1;\n+\t\tfor (i = 1; i < n; i++) {\n+\t\t\tm = __rte_pktmbuf_prefree_seg(txep[i].mbuf);\n+\t\t\tif (likely(m != NULL)) {\n+\t\t\t\tif (likely(m->pool == free[0]->pool)) {\n+\t\t\t\t\tfree[nb_free++] = m;\n+\t\t\t\t} else {\n+\t\t\t\t\trte_mempool_put_bulk(free[0]->pool,\n+\t\t\t\t\t\t\t (void *)free,\n+\t\t\t\t\t\t\t nb_free);\n+\t\t\t\t\tfree[0] = m;\n+\t\t\t\t\tnb_free = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\trte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);\n+\t} else {\n+\t\tfor (i = 1; i < n; i++) {\n+\t\t\tm = __rte_pktmbuf_prefree_seg(txep[i].mbuf);\n+\t\t\tif (m != NULL)\n+\t\t\t\trte_mempool_put(m->pool, m);\n+\t\t}\n+\t}\n+\n+\t/* buffers were freed, update counters */\n+\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);\n+\ttxq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);\n+\tif (txq->tx_next_dd >= txq->nb_tx_desc)\n+\t\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n+\n+\treturn txq->tx_rs_thresh;\n+}\n+\n+static inline void __attribute__((always_inline))\n+tx_backlog_entry(struct i40e_tx_entry *txep,\n+\t\t struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < (int)nb_pkts; ++i)\n+\t\ttxep[i].mbuf = tx_pkts[i];\n+}\n+\n+static inline void\n+_i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)\n+{\n+\tconst unsigned mask = rxq->nb_rx_desc - 1;\n+\tunsigned i;\n+\n+\tif (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)\n+\t\treturn;\n+\n+\t/* free all mbufs that are valid in the ring */\n+\tif (rxq->rxrearm_nb == 0) {\n+\t\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n+\t\t\tif (rxq->sw_ring[i].mbuf != NULL)\n+\t\t\t\trte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);\n+\t\t}\n+\t} else {\n+\t\tfor (i = rxq->rx_tail;\n+\t\t i != rxq->rxrearm_start;\n+\t\t i = (i + 1) & mask) {\n+\t\t\tif (rxq->sw_ring[i].mbuf != NULL)\n+\t\t\t\trte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);\n+\t\t}\n+\t}\n+\n+\trxq->rxrearm_nb = rxq->nb_rx_desc;\n+\n+\t/* set all entries to NULL */\n+\tmemset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);\n+}\n+\n+static inline int\n+i40e_rxq_vec_setup_default(struct i40e_rx_queue *rxq)\n+{\n+\tuintptr_t p;\n+\tstruct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */\n+\n+\tmb_def.nb_segs = 1;\n+\tmb_def.data_off = RTE_PKTMBUF_HEADROOM;\n+\tmb_def.port = rxq->port_id;\n+\trte_mbuf_refcnt_set(&mb_def, 1);\n+\n+\t/* prevent compiler reordering: rearm_data covers previous fields */\n+\trte_compiler_barrier();\n+\tp = (uintptr_t)&mb_def.rearm_data;\n+\trxq->mbuf_initializer = *(uint64_t *)p;\n+\treturn 0;\n+}\n+\n+static inline int\n+i40e_rx_vec_dev_conf_condition_check_default(struct rte_eth_dev *dev)\n+{\n+#ifndef RTE_LIBRTE_IEEE1588\n+\tstruct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;\n+\tstruct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;\n+\n+#ifndef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE\n+\t/* whithout rx ol_flags, no VP flag report */\n+\tif (rxmode->hw_vlan_strip != 0 ||\n+\t rxmode->hw_vlan_extend != 0 ||\n+\t rxmode->hw_ip_checksum != 0)\n+\t\treturn -1;\n+#endif\n+\n+\t/* no fdir support */\n+\tif (fconf->mode != RTE_FDIR_MODE_NONE)\n+\t\treturn -1;\n+\n+\t /* - no csum error report support\n+\t * - no header split support\n+\t */\n+\tif (rxmode->header_split == 1)\n+\t\treturn -1;\n+\n+\treturn 0;\n+#else\n+\tRTE_SET_USED(dev);\n+\treturn -1;\n+#endif\n+}\n+#endif\n", "prefixes": [ "dpdk-dev", "v2", "1/5" ] }