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GET /api/patches/1430/?format=api
{ "id": 1430, "url": "http://patches.dpdk.org/api/patches/1430/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1416530816-2159-21-git-send-email-jingjing.wu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1416530816-2159-21-git-send-email-jingjing.wu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1416530816-2159-21-git-send-email-jingjing.wu@intel.com", "date": "2014-11-21T00:46:54", "name": "[dpdk-dev,v6,20/22] i40e: take flow director flexible payload configuration", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "58cad81f2b1fbfdd1b760079b9d03d92b0f398b3", "submitter": { "id": 47, "url": "http://patches.dpdk.org/api/people/47/?format=api", "name": "Jingjing Wu", "email": "jingjing.wu@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1416530816-2159-21-git-send-email-jingjing.wu@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/1430/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/1430/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 5B00B8006;\n\tFri, 21 Nov 2014 01:38:25 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 8D8AE7FFE\n\tfor <dev@dpdk.org>; Fri, 21 Nov 2014 01:38:23 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga102.fm.intel.com with ESMTP; 20 Nov 2014 16:48:55 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga002.fm.intel.com with ESMTP; 20 Nov 2014 16:47:46 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id sAL0liUs004509;\n\tFri, 21 Nov 2014 08:47:44 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid sAL0lgh7002335; Fri, 21 Nov 2014 08:47:44 +0800", "(from wujingji@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id sAL0lgnT002331; \n\tFri, 21 Nov 2014 08:47:42 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.07,426,1413270000\"; d=\"scan'208\";a=\"635592377\"", "From": "Jingjing Wu <jingjing.wu@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 21 Nov 2014 08:46:54 +0800", "Message-Id": "<1416530816-2159-21-git-send-email-jingjing.wu@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1416530816-2159-1-git-send-email-jingjing.wu@intel.com>", "References": "<1414654006-7472-1-git-send-email-jingjing.wu@intel.com>\n\t<1416530816-2159-1-git-send-email-jingjing.wu@intel.com>", "Subject": "[dpdk-dev] [PATCH v6 20/22] i40e: take flow director flexible\n\tpayload configuration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "configure flexible payload and flex mask in i40e driver\nIt includes arguments verification and HW setting.\n\nSigned-off-by: jingjing.wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_i40e/i40e_fdir.c | 283 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 283 insertions(+)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_fdir.c b/lib/librte_pmd_i40e/i40e_fdir.c\nindex c452a80..54f3e24 100644\n--- a/lib/librte_pmd_i40e/i40e_fdir.c\n+++ b/lib/librte_pmd_i40e/i40e_fdir.c\n@@ -109,6 +109,13 @@\n #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))\n \n static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);\n+static int i40e_check_fdir_flex_conf(\n+\tconst struct rte_eth_fdir_flex_conf *conf);\n+static void i40e_set_flx_pld_cfg(struct i40e_pf *pf,\n+\t\t\t const struct rte_eth_flex_payload_cfg *cfg);\n+static void i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,\n+\t\tenum i40e_filter_pctype pctype,\n+\t\tconst struct rte_eth_fdir_flex_mask *mask_cfg);\n static int i40e_fdir_construct_pkt(struct i40e_pf *pf,\n \t\t\t\t const struct rte_eth_fdir_input *fdir_input,\n \t\t\t\t unsigned char *raw_pkt);\n@@ -364,6 +371,261 @@ i40e_init_flx_pld(struct i40e_pf *pf)\n \t}\n }\n \n+#define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))\n+\n+#define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \\\n+\tif ((flex_pit2).src_offset < \\\n+\t\t(flex_pit1).src_offset + (flex_pit1).size) { \\\n+\t\tPMD_DRV_LOG(ERR, \"src_offset should be not\" \\\n+\t\t\t\" less than than previous offset\" \\\n+\t\t\t\" + previous FSIZE.\"); \\\n+\t\treturn -EINVAL; \\\n+\t} \\\n+} while (0)\n+\n+/*\n+ * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,\n+ * and the flex_pit will be sorted by it's src_offset value\n+ */\n+static inline uint16_t\n+i40e_srcoff_to_flx_pit(const uint16_t *src_offset,\n+\t\t\tstruct i40e_fdir_flex_pit *flex_pit)\n+{\n+\tuint16_t src_tmp, size, num = 0;\n+\tuint16_t i, k, j = 0;\n+\n+\twhile (j < I40E_FDIR_MAX_FLEX_LEN) {\n+\t\tsize = 1;\n+\t\tfor (; j < I40E_FDIR_MAX_FLEX_LEN; j++) {\n+\t\t\tif (src_offset[j + 1] == src_offset[j] + 1)\n+\t\t\t\tsize++;\n+\t\t\telse {\n+\t\t\t\tsrc_tmp = src_offset[j] + 1 - size;\n+\t\t\t\t/* the flex_pit need to be sort by scr_offset */\n+\t\t\t\tfor (i = 0; i < num; i++) {\n+\t\t\t\t\tif (src_tmp < flex_pit[i].src_offset)\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\t/* if insert required, move backward */\n+\t\t\t\tfor (k = num; k > i; k--)\n+\t\t\t\t\tflex_pit[k] = flex_pit[k - 1];\n+\t\t\t\t/* insert */\n+\t\t\t\tflex_pit[i].dst_offset = j + 1 - size;\n+\t\t\t\tflex_pit[i].src_offset = src_tmp;\n+\t\t\t\tflex_pit[i].size = size;\n+\t\t\t\tj++;\n+\t\t\t\tnum++;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn num;\n+}\n+\n+/* i40e_check_fdir_flex_payload -check flex payload configuration arguments */\n+static inline int\n+i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)\n+{\n+\tstruct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];\n+\tuint16_t num, i;\n+\n+\tfor (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {\n+\t\tif (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {\n+\t\t\tPMD_DRV_LOG(ERR, \"exceeds maxmial payload limit.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tmemset(flex_pit, 0, sizeof(flex_pit));\n+\tnum = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);\n+\tif (num > I40E_MAX_FLXPLD_FIED) {\n+\t\tPMD_DRV_LOG(ERR, \"exceeds maxmial number of flex fields.\");\n+\t\treturn -EINVAL;\n+\t}\n+\tfor (i = 0; i < num; i++) {\n+\t\tif (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||\n+\t\t\tflex_pit[i].src_offset & 0x01) {\n+\t\t\tPMD_DRV_LOG(ERR, \"flexpayload should be measured\"\n+\t\t\t\t\" in word\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (i != num - 1)\n+\t\t\tI40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration\n+ * arguments are valid\n+ */\n+static int\n+i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)\n+{\n+\tconst struct rte_eth_flex_payload_cfg *flex_cfg;\n+\tconst struct rte_eth_fdir_flex_mask *flex_mask;\n+\tuint16_t mask_tmp;\n+\tuint8_t nb_bitmask;\n+\tuint16_t i, j;\n+\tint ret = 0;\n+\n+\tif (conf == NULL) {\n+\t\tPMD_DRV_LOG(INFO, \"NULL pointer.\");\n+\t\treturn -EINVAL;\n+\t}\n+\t/* check flexible payload setting configuration */\n+\tif (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {\n+\t\tPMD_DRV_LOG(ERR, \"invalid number of payload setting.\");\n+\t\treturn -EINVAL;\n+\t}\n+\tfor (i = 0; i < conf->nb_payloads; i++) {\n+\t\tflex_cfg = &conf->flex_set[i];\n+\t\tif (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {\n+\t\t\tPMD_DRV_LOG(ERR, \"invalid payload type.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tret = i40e_check_fdir_flex_payload(flex_cfg);\n+\t\tif (ret < 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"invalid flex payload arguments.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\t/* check flex mask setting configuration */\n+\tif (conf->nb_flexmasks > RTE_ETH_FLOW_TYPE_FRAG_IPV6) {\n+\t\tPMD_DRV_LOG(ERR, \"invalid number of flex masks.\");\n+\t\treturn -EINVAL;\n+\t}\n+\tfor (i = 0; i < conf->nb_flexmasks; i++) {\n+\t\tflex_mask = &conf->flex_mask[i];\n+\t\tif (!I40E_VALID_FLOW_TYPE(flex_mask->flow_type)) {\n+\t\t\tPMD_DRV_LOG(WARNING, \"invalid flow type.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tnb_bitmask = 0;\n+\t\tfor (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {\n+\t\t\tmask_tmp = I40E_WORD(flex_mask->mask[j],\n+\t\t\t\t\t flex_mask->mask[j + 1]);\n+\t\t\tif (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {\n+\t\t\t\tnb_bitmask++;\n+\t\t\t\tif (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {\n+\t\t\t\t\tPMD_DRV_LOG(ERR, \" exceed maximal\"\n+\t\t\t\t\t\t\" number of bitmasks.\");\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload\n+ * @pf: board private structure\n+ * @cfg: the rule how bytes stream is extracted as flexible payload\n+ */\n+static void\n+i40e_set_flx_pld_cfg(struct i40e_pf *pf,\n+\t\t\t const struct rte_eth_flex_payload_cfg *cfg)\n+{\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tstruct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];\n+\tuint32_t flx_pit;\n+\tuint16_t num, min_next_off; /* in words */\n+\tuint8_t field_idx = 0;\n+\tuint8_t layer_idx = 0;\n+\tuint16_t i;\n+\n+\tif (cfg->type == RTE_ETH_L2_PAYLOAD)\n+\t\tlayer_idx = I40E_FLXPLD_L2_IDX;\n+\telse if (cfg->type == RTE_ETH_L3_PAYLOAD)\n+\t\tlayer_idx = I40E_FLXPLD_L3_IDX;\n+\telse if (cfg->type == RTE_ETH_L4_PAYLOAD)\n+\t\tlayer_idx = I40E_FLXPLD_L4_IDX;\n+\n+\tmemset(flex_pit, 0, sizeof(flex_pit));\n+\tnum = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);\n+\n+\tfor (i = 0; i < num; i++) {\n+\t\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;\n+\t\t/* record the info in fdir structure */\n+\t\tpf->fdir.flex_set[field_idx].src_offset =\n+\t\t\tflex_pit[i].src_offset / sizeof(uint16_t);\n+\t\tpf->fdir.flex_set[field_idx].size =\n+\t\t\tflex_pit[i].size / sizeof(uint16_t);\n+\t\tpf->fdir.flex_set[field_idx].dst_offset =\n+\t\t\tflex_pit[i].dst_offset / sizeof(uint16_t);\n+\t\tflx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,\n+\t\t\t\tpf->fdir.flex_set[field_idx].size,\n+\t\t\t\tpf->fdir.flex_set[field_idx].dst_offset);\n+\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);\n+\t}\n+\tmin_next_off = pf->fdir.flex_set[field_idx].src_offset +\n+\t\t\t\tpf->fdir.flex_set[field_idx].size;\n+\n+\tfor (; i < I40E_MAX_FLXPLD_FIED; i++) {\n+\t\t/* set the non-used register obeying register's constrain */\n+\t\tflx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,\n+\t\t\t NONUSE_FLX_PIT_DEST_OFF);\n+\t\tI40E_WRITE_REG(hw,\n+\t\t\tI40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),\n+\t\t\tflx_pit);\n+\t\tmin_next_off++;\n+\t}\n+}\n+\n+/*\n+ * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload\n+ * @pf: board private structure\n+ * @pctype: packet classify type\n+ * @flex_masks: mask for flexible payload\n+ */\n+static void\n+i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,\n+\t\tenum i40e_filter_pctype pctype,\n+\t\tconst struct rte_eth_fdir_flex_mask *mask_cfg)\n+{\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tstruct i40e_fdir_flex_mask *flex_mask;\n+\tuint32_t flxinset, fd_mask;\n+\tuint16_t mask_tmp;\n+\tuint8_t i, nb_bitmask = 0;\n+\n+\tflex_mask = &pf->fdir.flex_mask[pctype];\n+\tmemset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));\n+\tfor (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {\n+\t\tmask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);\n+\t\tif (mask_tmp != 0x0) {\n+\t\t\tflex_mask->word_mask |=\n+\t\t\t\tI40E_FLEX_WORD_MASK(i / sizeof(uint16_t));\n+\t\t\tif (mask_tmp != UINT16_MAX) {\n+\t\t\t\t/* set bit mask */\n+\t\t\t\tflex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;\n+\t\t\t\tflex_mask->bitmask[nb_bitmask].offset =\n+\t\t\t\t\ti / sizeof(uint16_t);\n+\t\t\t\tnb_bitmask++;\n+\t\t\t}\n+\t\t}\n+\t}\n+\t/* write mask to hw */\n+\tflxinset = (flex_mask->word_mask <<\n+\t\tI40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &\n+\t\tI40E_PRTQF_FD_FLXINSET_INSET_MASK;\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);\n+\n+\tfor (i = 0; i < nb_bitmask; i++) {\n+\t\tfd_mask = (flex_mask->bitmask[i].mask <<\n+\t\t\tI40E_PRTQF_FD_MSK_MASK_SHIFT) &\n+\t\t\tI40E_PRTQF_FD_MSK_MASK_MASK;\n+\t\tfd_mask |= ((flex_mask->bitmask[i].offset +\n+\t\t\tI40E_FLX_OFFSET_IN_FIELD_VECTOR) <<\n+\t\t\tI40E_PRTQF_FD_MSK_OFFSET_SHIFT) &\n+\t\t\tI40E_PRTQF_FD_MSK_OFFSET_MASK;\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);\n+\t}\n+}\n+\n /*\n * Configure flow director related setting\n */\n@@ -372,7 +634,10 @@ i40e_fdir_configure(struct rte_eth_dev *dev)\n {\n \tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct rte_eth_fdir_flex_conf *conf;\n+\tenum i40e_filter_pctype pctype;\n \tuint32_t val;\n+\tuint8_t i;\n \tint ret = 0;\n \n \t/*\n@@ -396,6 +661,24 @@ i40e_fdir_configure(struct rte_eth_dev *dev)\n \t\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);\n \n \t\ti40e_init_flx_pld(pf); /* set flex config to default value */\n+\n+\t\tconf = &dev->data->dev_conf.fdir_conf.flex_conf;\n+\t\tret = i40e_check_fdir_flex_conf(conf);\n+\t\tif (ret < 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \" invalid configuration arguments.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\t/* configure flex payload */\n+\t\tfor (i = 0; i < conf->nb_payloads; i++)\n+\t\t\ti40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);\n+\t\t/* configure flex mask*/\n+\t\tfor (i = 0; i < conf->nb_flexmasks; i++) {\n+\t\t\tpctype = i40e_flowtype_to_pctype(\n+\t\t\t\tconf->flex_mask[i].flow_type);\n+\t\t\ti40e_set_flex_mask_on_pctype(pf,\n+\t\t\t\t\tpctype,\n+\t\t\t\t\t&conf->flex_mask[i]);\n+\t\t}\n \t} else {\n \t\t/* disable FDIR filter */\n \t\tval &= ~I40E_PFQF_CTL_0_FD_ENA_MASK;\n", "prefixes": [ "dpdk-dev", "v6", "20/22" ] }