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GET /api/patches/139748/?format=api
{ "id": 139748, "url": "http://patches.dpdk.org/api/patches/139748/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240430202144.49899-2-andrew.boyer@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240430202144.49899-2-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240430202144.49899-2-andrew.boyer@amd.com", "date": "2024-04-30T20:21:36", "name": "[v2,1/9] crypto/ionic: introduce AMD Pensando ionic crypto driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f9a9a9ac4c88b1844eedd9fb645eccadb6db5e7d", "submitter": { "id": 2861, "url": "http://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240430202144.49899-2-andrew.boyer@amd.com/mbox/", "series": [ { "id": 31850, "url": "http://patches.dpdk.org/api/series/31850/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31850", "date": "2024-04-30T20:21:35", "name": "crypto/ionic: introduce AMD Pensando ionic crypto driver", "version": 2, "mbox": "http://patches.dpdk.org/series/31850/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139748/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/139748/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 07C2743F56;\n\tTue, 30 Apr 2024 22:22:05 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B2BB4402BE;\n\tTue, 30 Apr 2024 22:22:01 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2087.outbound.protection.outlook.com [40.107.93.87])\n by mails.dpdk.org (Postfix) with ESMTP id 9AF1D402BD\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH v2 1/9] crypto/ionic: introduce AMD Pensando ionic crypto\n driver", "Date": "Tue, 30 Apr 2024 13:21:36 -0700", "Message-ID": "<20240430202144.49899-2-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240430202144.49899-1-andrew.boyer@amd.com>", "References": "<20240419195310.21432-1-andrew.boyer@amd.com>\n <20240430202144.49899-1-andrew.boyer@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF00026369:EE_|IA0PR12MB8228:EE_", "X-MS-Office365-Filtering-Correlation-Id": "8c651fb2-7f8a-4dfb-7091-08dc69532ea8", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|36860700004|1800799015|82310400014|376005;", "X-Microsoft-Antispam-Message-Info": "\n 5W6jCElIKJju8FfKRV/j0Rn8K3kDmxEDZVkluO17ALpRXVVJR5m1vmKiiYi51vuOdKdsmdd/1dJ5TCB/jhKDD6kx79z6FPJi7g/daAX13C6Z3eqMt8elSM5AfycnTTLqS4CqUSNOi/FH1OXvExdnvDrHDVI5TP4Z6ID3sg2rpZ8uMonSfm6gBAzsNe93fm/4PDefgMCk/0tLnWAobchFildHYAxVw3QGEYOP5hSUQE4iScfIahkeW26du5IPJnQ5unmgeqrH4eASO6P3qvcpGM9Zm5wNl9wWhQX5Dw4SUqPOuCKY7yQG1UCah9oah98Kl2yya+rBKzJfW0yXacZ1eh3XFaGLawijQ046ZPygYHwOY2A139Rf1hU2I6OjOFozamGz+9/PFDzNcwPahU44ZAPZk4QRwBwAex0lEsMcmtv+u6P28/yNAvdhZQMa3H7fthK0sxruNObbR7fM1B5a1pidtt0umnRObDMTd/S9xQPnhezsfRsX/5WbXIFZ2AT+dWIHspncSutUTomEWv4a1a7UE7YnUG5GSVHv+5FkbdKbwSgcQhWdUxL/30Oz4vT4l+B1LITt2p7i8MhcW2AuUX9P7HATMAh1mFK0/U6MNL1vxlp0oPRBGbjivI0fLu/MqYx/XeczK0DfAbzACXxSdy457U5IZnVT8uvgXICv2RX4iQ7nVgg2pmhRXsEqQ127q2xXmYHWqN762lJmnNL+NOg6RZe7VJ4mVoBtm6B6gM2CZac4HOfxT68fT2iPDVoPokLANuMjaBWl9dxwAMpP9RtiFWPSERCW9KtGZ00HTOSgSqTC7Y9oRbI50ZD8KjhbsTdOCyhkEF057f0aZN+1YvL+4GtwFE4K3GgOsX3PLTE6F1kFRwvb+JD9p4u7XExY/gy4g2fukNOaH9FuvN4SWwNh3aFqmKLIXcc+KjIOpdeCEkEefInt5OvQFnWdA9HCy81cZ3Ge7d5U+nAyRfue4aNRq/+L9HiisYltOZ4PuZ7r4cnyskHFPA3jySQUg3rHZZTT2F9oFmanpx3BiLcTvOMtaj8mXupOIR7NdL1q0bNbv6SmGVepVMI/Bnr8P9Z+egme1zlmCfE0YCiB640Y4MjYyFJ3OLhe2vKxjbG9VbkJtmvR48rpPC6ojhvbSh8s2TyTkppHUlrDsoN+Kvkc9rZt+GzzsTKDcqVEzxzztWtyZJgEZv8XnfadhaOUhici3k/NvWGSa7xHaf0KHIQc3KRyuX1yVFJVfpYqnloGiN7IBfKDs5I4yiXdZTdwjvfmjeQVtSqvOOLbtNXvVZUUKUTyLYW2OI1rF81CtqjGi2oP0XZMWbihCiW42ZXjErKY4Q7HBUyy+1wle4pytNo+1TrHsSjlWQ/6Fvyt5eMIoJwbUkKHJ9igEBz8WQnjRaLY", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(36860700004)(1800799015)(82310400014)(376005); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Apr 2024 20:21:56.4979 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8c651fb2-7f8a-4dfb-7091-08dc69532ea8", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF00026369.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA0PR12MB8228", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Introduce a new crypto PMD for AMD Pensando hardware accelerators. It\nallows applications running directly on the AMD Pensando DSC to offload\ncryptographic operations to hardware cryptographic blocks.\n\nAdd support for the cryptodevs to the common ionic library.\nAdd the driver skeleton.\nAdd a skeleton features list and guide.\nHook the new PMD up to the build.\nUpdate MAINTAINERS.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n MAINTAINERS | 7 ++\n doc/guides/cryptodevs/features/ionic.ini | 32 +++++\n doc/guides/cryptodevs/index.rst | 1 +\n doc/guides/cryptodevs/ionic.rst | 28 +++++\n drivers/common/ionic/ionic_common.h | 2 +\n drivers/common/ionic/ionic_common_uio.c | 48 +++++++-\n drivers/common/ionic/version.map | 1 +\n drivers/crypto/ionic/ionic_crypto.h | 92 ++++++++++++++\n drivers/crypto/ionic/ionic_crypto_main.c | 148 +++++++++++++++++++++++\n drivers/crypto/ionic/ionic_crypto_vdev.c | 91 ++++++++++++++\n drivers/crypto/ionic/meson.build | 13 ++\n drivers/crypto/meson.build | 1 +\n 12 files changed, 463 insertions(+), 1 deletion(-)\n create mode 100644 doc/guides/cryptodevs/features/ionic.ini\n create mode 100644 doc/guides/cryptodevs/ionic.rst\n create mode 100644 drivers/crypto/ionic/ionic_crypto.h\n create mode 100644 drivers/crypto/ionic/ionic_crypto_main.c\n create mode 100644 drivers/crypto/ionic/ionic_crypto_vdev.c\n create mode 100644 drivers/crypto/ionic/meson.build", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 7abb3aee49..7cf999371c 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1075,6 +1075,13 @@ F: drivers/crypto/ccp/\n F: doc/guides/cryptodevs/ccp.rst\n F: doc/guides/cryptodevs/features/ccp.ini\n \n+AMD Pensando ionic crypto\n+M: Andrew Boyer <andrew.boyer@amd.com>\n+F: drivers/crypto/ionic/\n+F: drivers/common/ionic/\n+F: doc/guides/cryptodevs/ionic.rst\n+F: doc/guides/cryptodevs/features/ionic.ini\n+\n ARMv8 Crypto\n M: Ruifeng Wang <ruifeng.wang@arm.com>\n F: drivers/crypto/armv8/\ndiff --git a/doc/guides/cryptodevs/features/ionic.ini b/doc/guides/cryptodevs/features/ionic.ini\nnew file mode 100644\nindex 0000000000..62b7e9e8f2\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/ionic.ini\n@@ -0,0 +1,32 @@\n+;\n+; Supported features of the 'ionic' crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+\n+;\n+; Supported crypto algorithms of 'ionic' crypto driver.\n+;\n+[Cipher]\n+\n+;\n+; Supported authentication algorithms of 'ionic' crypto driver.\n+;\n+[Auth]\n+\n+;\n+; Supported AEAD algorithms of 'ionic' crypto driver.\n+;\n+[AEAD]\n+\n+;\n+; Supported Asymmetric algorithms of the 'ionic' crypto driver.\n+;\n+[Asymmetric]\n+\n+;\n+; Supported Operating systems of the 'ionic' crypto driver.\n+;\n+[OS]\n+Linux = Y\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\nindex cb4ce227e9..1e57a9fe86 100644\n--- a/doc/guides/cryptodevs/index.rst\n+++ b/doc/guides/cryptodevs/index.rst\n@@ -20,6 +20,7 @@ Crypto Device Drivers\n cnxk\n dpaa2_sec\n dpaa_sec\n+ ionic\n kasumi\n octeontx\n openssl\ndiff --git a/doc/guides/cryptodevs/ionic.rst b/doc/guides/cryptodevs/ionic.rst\nnew file mode 100644\nindex 0000000000..c9173deb2f\n--- /dev/null\n+++ b/doc/guides/cryptodevs/ionic.rst\n@@ -0,0 +1,28 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright 2021-2024 Advanced Micro Devices, Inc.\n+\n+IONIC Crypto Driver\n+===================\n+\n+The ionic crypto driver provides support for offloading cryptographic operations\n+to hardware cryptographic blocks on AMD Pensando server adapters.\n+It currently supports the below models:\n+\n+- DSC-25 dual-port 25G Distributed Services Card `(pdf) <https://pensandoio.secure.force.com/DownloadFile?id=a0L4T000004IKurUAG>`__\n+- DSC-100 dual-port 100G Distributed Services Card `(pdf) <https://pensandoio.secure.force.com/DownloadFile?id=a0L4T000004IKuwUAG>`__\n+- DSC-200 dual-port 200G Distributed Services Card `(pdf) <https://www.amd.com/system/files/documents/pensando-dsc-200-product-brief.pdf>`__\n+\n+Please visit the AMD Pensando web site at https://www.amd.com/en/accelerators/pensando for more information.\n+\n+Device Support\n+--------------\n+\n+The ionic crypto PMD currently supports running directly on the device's embedded\n+processors. It does not yet support host-side access via PCI.\n+For help running the PMD, please contact AMD Pensando support.\n+\n+Runtime Configuration\n+---------------------\n+\n+None\n+\ndiff --git a/drivers/common/ionic/ionic_common.h b/drivers/common/ionic/ionic_common.h\nindex eb4850e24c..c4a15fdf2b 100644\n--- a/drivers/common/ionic/ionic_common.h\n+++ b/drivers/common/ionic/ionic_common.h\n@@ -32,6 +32,8 @@ struct ionic_dev_bar {\n \n __rte_internal\n void ionic_uio_scan_mnet_devices(void);\n+__rte_internal\n+void ionic_uio_scan_mcrypt_devices(void);\n \n __rte_internal\n void ionic_uio_get_rsrc(const char *name, int idx, struct ionic_dev_bar *bar);\ndiff --git a/drivers/common/ionic/ionic_common_uio.c b/drivers/common/ionic/ionic_common_uio.c\nindex e5c73faf96..c647b22eaf 100644\n--- a/drivers/common/ionic/ionic_common_uio.c\n+++ b/drivers/common/ionic/ionic_common_uio.c\n@@ -23,10 +23,12 @@\n \n #define IONIC_MDEV_UNK \"mdev_unknown\"\n #define IONIC_MNIC \"cpu_mnic\"\n+#define IONIC_MCRYPT \"cpu_mcrypt\"\n \n #define IONIC_MAX_NAME_LEN 20\n #define IONIC_MAX_MNETS 5\n-#define IONIC_MAX_DEVICES (IONIC_MAX_MNETS)\n+#define IONIC_MAX_MCPTS 1\n+#define IONIC_MAX_DEVICES (IONIC_MAX_MNETS + IONIC_MAX_MCPTS)\n #define IONIC_MAX_U16_IDX 0xFFFF\n #define IONIC_UIO_MAX_TRIES 32\n \n@@ -49,6 +51,7 @@ struct ionic_map_tbl ionic_mdev_map[IONIC_MAX_DEVICES] = {\n \t{ \"net_ionic2\", 2, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK },\n \t{ \"net_ionic3\", 3, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK },\n \t{ \"net_ionic4\", 4, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK },\n+\t{ \"crypto_ionic0\", 5, IONIC_MAX_U16_IDX, IONIC_MDEV_UNK },\n };\n \n struct uio_name {\n@@ -143,6 +146,49 @@ ionic_uio_scan_mnet_devices(void)\n \t}\n }\n \n+void\n+ionic_uio_scan_mcrypt_devices(void)\n+{\n+\tstruct ionic_map_tbl *map;\n+\tchar devname[IONIC_MAX_NAME_LEN];\n+\tstruct uio_name name_cache[IONIC_MAX_DEVICES];\n+\tbool done;\n+\tint mdev_idx = 0;\n+\tint uio_idx;\n+\tint i;\n+\tstatic bool scan_done;\n+\n+\tif (scan_done)\n+\t\treturn;\n+\n+\tscan_done = true;\n+\n+\tuio_fill_name_cache(name_cache, IONIC_MCRYPT);\n+\n+\tfor (i = IONIC_MAX_MNETS; i < IONIC_MAX_DEVICES; i++) {\n+\t\tdone = false;\n+\n+\t\twhile (!done) {\n+\t\t\tif (mdev_idx > IONIC_MAX_MDEV_SCAN)\n+\t\t\t\tbreak;\n+\n+\t\t\t/* Look for a matching mcrypt */\n+\t\t\tsnprintf(devname, IONIC_MAX_NAME_LEN,\n+\t\t\t\tIONIC_MCRYPT \"%d\", mdev_idx);\n+\t\t\tuio_idx = uio_get_idx_for_devname(name_cache, devname);\n+\t\t\tif (uio_idx >= 0) {\n+\t\t\t\tmap = &ionic_mdev_map[i];\n+\t\t\t\tmap->uio_idx = (uint16_t)uio_idx;\n+\t\t\t\tstrlcpy(map->mdev_name, devname,\n+\t\t\t\t\tIONIC_MAX_NAME_LEN);\n+\t\t\t\tdone = true;\n+\t\t\t}\n+\n+\t\t\tmdev_idx++;\n+\t\t}\n+\t}\n+}\n+\n static int\n uio_get_multi_dev_uionum(const char *name)\n {\ndiff --git a/drivers/common/ionic/version.map b/drivers/common/ionic/version.map\nindex 484330c437..db532d4ffc 100644\n--- a/drivers/common/ionic/version.map\n+++ b/drivers/common/ionic/version.map\n@@ -2,6 +2,7 @@ INTERNAL {\n \tglobal:\n \n \tionic_uio_scan_mnet_devices;\n+\tionic_uio_scan_mcrypt_devices;\n \tionic_uio_get_rsrc;\n \tionic_uio_rel_rsrc;\n \ndiff --git a/drivers/crypto/ionic/ionic_crypto.h b/drivers/crypto/ionic/ionic_crypto.h\nnew file mode 100644\nindex 0000000000..86750f0cbd\n--- /dev/null\n+++ b/drivers/crypto/ionic/ionic_crypto.h\n@@ -0,0 +1,92 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#ifndef _IONIC_CRYPTO_H_\n+#define _IONIC_CRYPTO_H_\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <inttypes.h>\n+\n+#include <rte_common.h>\n+#include <rte_dev.h>\n+#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n+#include <rte_log.h>\n+\n+#include \"ionic_common.h\"\n+#include \"ionic_regs.h\"\n+\n+/* Devargs */\n+/* NONE */\n+\n+extern int iocpt_logtype;\n+#define RTE_LOGTYPE_IOCPT iocpt_logtype\n+\n+#define IOCPT_PRINT(level, ...)\t\t\t\t\t\t\\\n+\tRTE_LOG_LINE_PREFIX(level, IOCPT, \"%s(): \", __func__, __VA_ARGS__)\n+\n+#define IOCPT_PRINT_CALL() IOCPT_PRINT(DEBUG, \" >>\")\n+\n+struct iocpt_dev_bars {\n+\tstruct ionic_dev_bar bar[IONIC_BARS_MAX];\n+\tuint32_t num_bars;\n+};\n+\n+#define IOCPT_DEV_F_INITED\t\tBIT(0)\n+#define IOCPT_DEV_F_UP\t\t\tBIT(1)\n+#define IOCPT_DEV_F_FW_RESET\t\tBIT(2)\n+\n+/* Combined dev / LIF object */\n+struct iocpt_dev {\n+\tconst char *name;\n+\tstruct iocpt_dev_bars bars;\n+\n+\tconst struct iocpt_dev_intf *intf;\n+\tvoid *bus_dev;\n+\tstruct rte_cryptodev *crypto_dev;\n+\n+\tuint32_t max_qps;\n+\tuint32_t max_sessions;\n+\tuint16_t state;\n+\tuint8_t driver_id;\n+\tuint8_t socket_id;\n+\n+\tuint64_t features;\n+\tuint32_t hw_features;\n+};\n+\n+struct iocpt_dev_intf {\n+\tint (*setup_bars)(struct iocpt_dev *dev);\n+\tvoid (*unmap_bars)(struct iocpt_dev *dev);\n+};\n+\n+static inline int\n+iocpt_setup_bars(struct iocpt_dev *dev)\n+{\n+\tif (dev->intf->setup_bars == NULL)\n+\t\treturn -EINVAL;\n+\n+\treturn (*dev->intf->setup_bars)(dev);\n+}\n+\n+int iocpt_probe(void *bus_dev, struct rte_device *rte_dev,\n+\tstruct iocpt_dev_bars *bars, const struct iocpt_dev_intf *intf,\n+\tuint8_t driver_id, uint8_t socket_id);\n+int iocpt_remove(struct rte_device *rte_dev);\n+\n+void iocpt_configure(struct iocpt_dev *dev);\n+void iocpt_deinit(struct iocpt_dev *dev);\n+\n+static inline bool\n+iocpt_is_embedded(void)\n+{\n+#if defined(RTE_LIBRTE_IONIC_PMD_EMBEDDED)\n+\treturn true;\n+#else\n+\treturn false;\n+#endif\n+}\n+\n+#endif /* _IONIC_CRYPTO_H_ */\ndiff --git a/drivers/crypto/ionic/ionic_crypto_main.c b/drivers/crypto/ionic/ionic_crypto_main.c\nnew file mode 100644\nindex 0000000000..ecbb1cb161\n--- /dev/null\n+++ b/drivers/crypto/ionic/ionic_crypto_main.c\n@@ -0,0 +1,148 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#include <inttypes.h>\n+\n+#include <rte_common.h>\n+#include <rte_malloc.h>\n+#include <rte_bitops.h>\n+\n+#include \"ionic_crypto.h\"\n+\n+static int\n+iocpt_init(struct iocpt_dev *dev)\n+{\n+\tdev->state |= IOCPT_DEV_F_INITED;\n+\n+\treturn 0;\n+}\n+\n+void\n+iocpt_configure(struct iocpt_dev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+}\n+\n+void\n+iocpt_deinit(struct iocpt_dev *dev)\n+{\n+\tIOCPT_PRINT_CALL();\n+\n+\tif (!(dev->state & IOCPT_DEV_F_INITED))\n+\t\treturn;\n+\n+\tdev->state &= ~IOCPT_DEV_F_INITED;\n+}\n+\n+static int\n+iocpt_devargs(struct rte_devargs *devargs, struct iocpt_dev *dev)\n+{\n+\tRTE_SET_USED(devargs);\n+\tRTE_SET_USED(dev);\n+\n+\treturn 0;\n+}\n+\n+int\n+iocpt_probe(void *bus_dev, struct rte_device *rte_dev,\n+\tstruct iocpt_dev_bars *bars, const struct iocpt_dev_intf *intf,\n+\tuint8_t driver_id, uint8_t socket_id)\n+{\n+\tstruct rte_cryptodev_pmd_init_params init_params = {\n+\t\t\"iocpt\",\n+\t\tsizeof(struct iocpt_dev),\n+\t\tsocket_id,\n+\t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS\n+\t};\n+\tstruct rte_cryptodev *cdev;\n+\tstruct iocpt_dev *dev;\n+\tuint32_t i;\n+\tint err;\n+\n+\t/* Multi-process not supported */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\terr = -EPERM;\n+\t\tgoto err;\n+\t}\n+\n+\tcdev = rte_cryptodev_pmd_create(rte_dev->name, rte_dev, &init_params);\n+\tif (cdev == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"OOM\");\n+\t\terr = -ENOMEM;\n+\t\tgoto err;\n+\t}\n+\n+\tdev = cdev->data->dev_private;\n+\tdev->crypto_dev = cdev;\n+\tdev->bus_dev = bus_dev;\n+\tdev->intf = intf;\n+\tdev->driver_id = driver_id;\n+\tdev->socket_id = socket_id;\n+\n+\tfor (i = 0; i < bars->num_bars; i++) {\n+\t\tstruct ionic_dev_bar *bar = &bars->bar[i];\n+\n+\t\tIOCPT_PRINT(DEBUG,\n+\t\t\t\"bar[%u] = { .va = %p, .pa = %#jx, .len = %lu }\",\n+\t\t\ti, bar->vaddr, bar->bus_addr, bar->len);\n+\t\tif (bar->vaddr == NULL) {\n+\t\t\tIOCPT_PRINT(ERR, \"Null bar found, aborting\");\n+\t\t\terr = -EFAULT;\n+\t\t\tgoto err_destroy_crypto_dev;\n+\t\t}\n+\n+\t\tdev->bars.bar[i].vaddr = bar->vaddr;\n+\t\tdev->bars.bar[i].bus_addr = bar->bus_addr;\n+\t\tdev->bars.bar[i].len = bar->len;\n+\t}\n+\tdev->bars.num_bars = bars->num_bars;\n+\n+\terr = iocpt_devargs(rte_dev->devargs, dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot parse device arguments\");\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n+\terr = iocpt_setup_bars(dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot setup BARs: %d, aborting\", err);\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n+\terr = iocpt_init(dev);\n+\tif (err != 0) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot init device: %d, aborting\", err);\n+\t\tgoto err_destroy_crypto_dev;\n+\t}\n+\n+\treturn 0;\n+\n+err_destroy_crypto_dev:\n+\trte_cryptodev_pmd_destroy(cdev);\n+err:\n+\treturn err;\n+}\n+\n+int\n+iocpt_remove(struct rte_device *rte_dev)\n+{\n+\tstruct rte_cryptodev *cdev;\n+\tstruct iocpt_dev *dev;\n+\n+\tcdev = rte_cryptodev_pmd_get_named_dev(rte_dev->name);\n+\tif (cdev == NULL) {\n+\t\tIOCPT_PRINT(DEBUG, \"Cannot find device %s\", rte_dev->name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdev = cdev->data->dev_private;\n+\n+\tiocpt_deinit(dev);\n+\n+\trte_cryptodev_pmd_destroy(cdev);\n+\n+\treturn 0;\n+}\n+\n+RTE_LOG_REGISTER_DEFAULT(iocpt_logtype, NOTICE);\ndiff --git a/drivers/crypto/ionic/ionic_crypto_vdev.c b/drivers/crypto/ionic/ionic_crypto_vdev.c\nnew file mode 100644\nindex 0000000000..a915aa06aa\n--- /dev/null\n+++ b/drivers/crypto/ionic/ionic_crypto_vdev.c\n@@ -0,0 +1,91 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2021-2024 Advanced Micro Devices, Inc.\n+ */\n+\n+#include <stdint.h>\n+#include <errno.h>\n+\n+#include <rte_errno.h>\n+#include <rte_common.h>\n+#include <rte_log.h>\n+#include <rte_eal.h>\n+#include <bus_vdev_driver.h>\n+#include <rte_dev.h>\n+#include <rte_string_fns.h>\n+\n+#include \"ionic_crypto.h\"\n+\n+#define IOCPT_VDEV_DEV_BAR 0\n+#define IOCPT_VDEV_INTR_CTL_BAR 1\n+#define IOCPT_VDEV_INTR_CFG_BAR 2\n+#define IOCPT_VDEV_DB_BAR 3\n+#define IOCPT_VDEV_BARS_MAX 4\n+\n+#define IOCPT_VDEV_DEV_INFO_REGS_OFFSET 0x0000\n+#define IOCPT_VDEV_DEV_CMD_REGS_OFFSET 0x0800\n+\n+static int\n+iocpt_vdev_setup_bars(struct iocpt_dev *dev)\n+{\n+\tIOCPT_PRINT_CALL();\n+\n+\tdev->name = rte_vdev_device_name(dev->bus_dev);\n+\n+\treturn 0;\n+}\n+\n+static void\n+iocpt_vdev_unmap_bars(struct iocpt_dev *dev)\n+{\n+\tstruct iocpt_dev_bars *bars = &dev->bars;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < IOCPT_VDEV_BARS_MAX; i++)\n+\t\tionic_uio_rel_rsrc(dev->name, i, &bars->bar[i]);\n+}\n+\n+static uint8_t iocpt_vdev_driver_id;\n+static const struct iocpt_dev_intf iocpt_vdev_intf = {\n+\t.setup_bars = iocpt_vdev_setup_bars,\n+\t.unmap_bars = iocpt_vdev_unmap_bars,\n+};\n+\n+static int\n+iocpt_vdev_probe(struct rte_vdev_device *vdev)\n+{\n+\tstruct iocpt_dev_bars bars = {};\n+\tconst char *name = rte_vdev_device_name(vdev);\n+\tunsigned int i;\n+\n+\tIOCPT_PRINT(NOTICE, \"Initializing device %s%s\", name,\n+\t\trte_eal_process_type() == RTE_PROC_SECONDARY ?\n+\t\t\t\" [SECONDARY]\" : \"\");\n+\n+\tionic_uio_scan_mcrypt_devices();\n+\n+\tfor (i = 0; i < IOCPT_VDEV_BARS_MAX; i++)\n+\t\tionic_uio_get_rsrc(name, i, &bars.bar[i]);\n+\n+\tbars.num_bars = IOCPT_VDEV_BARS_MAX;\n+\n+\treturn iocpt_probe((void *)vdev, &vdev->device,\n+\t\t\t&bars, &iocpt_vdev_intf,\n+\t\t\tiocpt_vdev_driver_id, rte_socket_id());\n+}\n+\n+static int\n+iocpt_vdev_remove(struct rte_vdev_device *vdev)\n+{\n+\treturn iocpt_remove(&vdev->device);\n+}\n+\n+static struct rte_vdev_driver rte_vdev_iocpt_pmd = {\n+\t.probe = iocpt_vdev_probe,\n+\t.remove = iocpt_vdev_remove,\n+};\n+\n+static struct cryptodev_driver rte_vdev_iocpt_drv;\n+\n+RTE_PMD_REGISTER_VDEV(crypto_ionic, rte_vdev_iocpt_pmd);\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(rte_vdev_iocpt_drv, rte_vdev_iocpt_pmd.driver,\n+\t\tiocpt_vdev_driver_id);\ndiff --git a/drivers/crypto/ionic/meson.build b/drivers/crypto/ionic/meson.build\nnew file mode 100644\nindex 0000000000..4114e13e53\n--- /dev/null\n+++ b/drivers/crypto/ionic/meson.build\n@@ -0,0 +1,13 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright 2021-2024 Advanced Micro Devices, Inc.\n+\n+deps += ['bus_vdev']\n+deps += ['common_ionic']\n+\n+sources = files(\n+ 'ionic_crypto_main.c',\n+ 'ionic_crypto_vdev.c',\n+)\n+name = 'ionic_crypto'\n+\n+includes += include_directories('../../common/ionic')\ndiff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build\nindex ee5377deff..e799861bb6 100644\n--- a/drivers/crypto/meson.build\n+++ b/drivers/crypto/meson.build\n@@ -10,6 +10,7 @@ drivers = [\n 'cnxk',\n 'dpaa_sec',\n 'dpaa2_sec',\n+ 'ionic',\n 'ipsec_mb',\n 'mlx5',\n 'mvsam',\n", "prefixes": [ "v2", "1/9" ] }