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GET /api/patches/139738/?format=api
{ "id": 139738, "url": "http://patches.dpdk.org/api/patches/139738/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240430120810.108928-7-mattias.ronnblom@ericsson.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240430120810.108928-7-mattias.ronnblom@ericsson.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240430120810.108928-7-mattias.ronnblom@ericsson.com", "date": "2024-04-30T12:08:10", "name": "[RFC,v5,6/6] eal: add unit tests for atomic bit access functions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bbaf67d51868c7186fb1a0fc33bf7f4196744b6a", "submitter": { "id": 1077, "url": "http://patches.dpdk.org/api/people/1077/?format=api", "name": "Mattias Rönnblom", "email": "mattias.ronnblom@ericsson.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240430120810.108928-7-mattias.ronnblom@ericsson.com/mbox/", "series": [ { "id": 31843, "url": "http://patches.dpdk.org/api/series/31843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31843", "date": "2024-04-30T12:08:04", "name": "Improve EAL bit operations API", "version": 5, "mbox": "http://patches.dpdk.org/series/31843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139738/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/139738/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7278843F54;\n\tTue, 30 Apr 2024 14:19:22 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A1A6C40647;\n\tTue, 30 Apr 2024 14:18:42 +0200 (CEST)", "from EUR05-AM6-obe.outbound.protection.outlook.com\n (mail-am6eur05on2059.outbound.protection.outlook.com [40.107.22.59])\n by mails.dpdk.org (Postfix) with ESMTP id B8D3F402D0\n for <dev@dpdk.org>; Tue, 30 Apr 2024 14:18:37 +0200 (CEST)", "from AM9P193CA0015.EURP193.PROD.OUTLOOK.COM (2603:10a6:20b:21e::20)\n by AS8PR07MB7589.eurprd07.prod.outlook.com (2603:10a6:20b:2af::10)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.35; Tue, 30 Apr\n 2024 12:18:34 +0000", "from AM3PEPF0000A799.eurprd04.prod.outlook.com\n (2603:10a6:20b:21e:cafe::49) by AM9P193CA0015.outlook.office365.com\n (2603:10a6:20b:21e::20) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.34 via Frontend\n Transport; Tue, 30 Apr 2024 12:18:34 +0000", "from oa.msg.ericsson.com (192.176.1.74) by\n AM3PEPF0000A799.mail.protection.outlook.com (10.167.16.104) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7544.18 via Frontend Transport; Tue, 30 Apr 2024 12:18:33 +0000", "from seliicinfr00049.seli.gic.ericsson.se (153.88.142.248) by\n smtp-central.internal.ericsson.com (100.87.178.62) with Microsoft SMTP Server\n id 15.2.1544.9; Tue, 30 Apr 2024 14:18:33 +0200", "from breslau.. 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helo=oa.msg.ericsson.com; pr=C", "From": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "To": "<dev@dpdk.org>", "CC": "<hofors@lysator.liu.se>, Heng Wang <heng.wang@ericsson.com>,\n \"Stephen Hemminger\" <stephen@networkplumber.org>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>,\n =?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>, =?utf-8?q?Mattia?=\n\t=?utf-8?q?s_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "Subject": "[RFC v5 6/6] eal: add unit tests for atomic bit access functions", "Date": "Tue, 30 Apr 2024 14:08:10 +0200", "Message-ID": "<20240430120810.108928-7-mattias.ronnblom@ericsson.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240430120810.108928-1-mattias.ronnblom@ericsson.com>", "References": "<20240430095523.108688-2-mattias.ronnblom@ericsson.com>\n <20240430120810.108928-1-mattias.ronnblom@ericsson.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "AM3PEPF0000A799:EE_|AS8PR07MB7589:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7a4bfe8a-3984-4c6b-9637-08dc690fa7cd", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|82310400014|1800799015|376005|36860700004;", "X-Microsoft-Antispam-Message-Info": "=?utf-8?q?0XckUMNv/sBNlKX08iJmdcgsNVOmLZK?=\n\t=?utf-8?q?iEljCkyTdnIS0AB6UVIFKkMAhy4Vovn9RPJuw1Jp5KpmRkqkfnmbmByBtHTpcbSm9?=\n\t=?utf-8?q?2so+x2NTCRByYpI3fPDOKKcm5zdNA7xFMNVWUVIvxWtvT2ytc8AhWc1+jyBj80Rsc?=\n\t=?utf-8?q?cPmDwPn74wgHGoYfRLXm0FBP+FEECK9WeDnEtCux8j9UBe6Vr017CCIOZb9X2R3tG?=\n\t=?utf-8?q?4rfhxffXvCStt4+7T1ODffng9ogL53Ya2zA1Ib1ZahtIc4X2wIw5Oud6k8Ee7O/uM?=\n\t=?utf-8?q?G17H76+ICOCrC7Mseb76ZZhHKrm2W4vWlScNCYE2I8a8ThiAhY1Ud2WUmc8ds6QCg?=\n\t=?utf-8?q?fg+jy7UgIRvcmC9SyAJM0Yls6+a2dccTfdL4mnTDGvWvjoQQS62RrscPW+6m9+NH+?=\n\t=?utf-8?q?CHArA+BQKst6vLiLaavzuCxzpptBw1GyCek4JghXuWcQWXaOzESycV2JUQS8Ujt66?=\n\t=?utf-8?q?U2NPj778qdm0wyMlj+wMnIT1iFOU/FPZB0udrQD9gQJP6sqbved+fUGtYVKlOj22x?=\n\t=?utf-8?q?VR/SkITf+JYbsDFIOTaJBko6fvPyRUDOCAcj/dqE3dgCYMH4etgyBAaJuTNkYDMpc?=\n\t=?utf-8?q?JwDlEGZbFw52c5Y4/jQHibGcrIYhKYJ3dFzN//0Ye4YhjWQYOF9bQ0/m6Ub04g0eM?=\n\t=?utf-8?q?f058uWIn2JH53i6WIyOfpbXlRce9aZLlAnUhTzCCjuUvmNKJnFOOxQ782tHe2lCb0?=\n\t=?utf-8?q?PKvsJxWOZoFZZJqp5Q6yWZWpEjDKMWGnXUCLFyPSjCcJMIlRYoVVmY6722WpEZ/Z3?=\n\t=?utf-8?q?JX4SIjeugvycSu0vJHpko/TomAI0MzZP0qM/i9SvG0aCx/zteHIVyE8pEucSGS5ng?=\n\t=?utf-8?q?rQSu8g+d3MRU7jK3m/uJpGoJBzIhNBl8zAYUYmg16YKFVwxwwqyrNDU7hZPhc+QHW?=\n\t=?utf-8?q?p5I3RS1imwdVxPSPyYcuAcsqrswxiAqRBLWTxR8vtAJOSgpe4mlwosy+Rx3+O+AAx?=\n\t=?utf-8?q?Vh7gTHgnMqdz0utfpWcEJx29FneDIZYxo8X4l+SvCMMcD+3YlUKyXkdIDJXvlNN5J?=\n\t=?utf-8?q?6bz5BdjTK+ppuln0Ti8pV8osN9JsULTL8UB8O69Lw0pCAn62rn4yzbo6Zbo+U104g?=\n\t=?utf-8?q?sKke8/4/GQtG+v++txv2qRj8T5lebHj71umXaisbFzphydMMm4+7VqRDfVeB/WiXK?=\n\t=?utf-8?q?+aV1aNEpUPf3OJBkwnz0z9oOoz13LPFjJnGjgVdlP+xA8MeVkjOTVUrSW5jExeeTt?=\n\t=?utf-8?q?Pc0D9KNePM2HhIViQuuVSg6ZNKzlgac1mwXDw3t5U+DXgK72Ef4uFTm3VGLzrIeNR?=\n\t=?utf-8?q?wGZq8Lw/BzJ0kDcv3+aD03hzbEKP93rI5qeLLRZLIYE+xjCfoRpaGOY+35F/vm5nU?=\n\t=?utf-8?q?bDkEoLQ2ZP3I?=", "X-Forefront-Antispam-Report": "CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net;\n CAT:NONE; SFS:(13230031)(82310400014)(1800799015)(376005)(36860700004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "ericsson.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Apr 2024 12:18:33.9993 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7a4bfe8a-3984-4c6b-9637-08dc690fa7cd", "X-MS-Exchange-CrossTenant-Id": "92e84ceb-fbfd-47ab-be52-080c6b87953f", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74];\n Helo=[oa.msg.ericsson.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM3PEPF0000A799.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AS8PR07MB7589", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Extend bitops tests to cover the\nrte_bit_atomic_[set|clear|assign|test|test_and_[set|clear|assign]]()\nfamily of functions.\n\nRFC v4:\n * Add atomicity test for atomic bit flip.\n\nRFC v3:\n * Rename variable 'main' to make ICC happy.\n\nSigned-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\nAcked-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\n---\n app/test/test_bitops.c | 315 ++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 314 insertions(+), 1 deletion(-)", "diff": "diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c\nindex 615ec6e563..abc07e8caf 100644\n--- a/app/test/test_bitops.c\n+++ b/app/test/test_bitops.c\n@@ -3,10 +3,13 @@\n * Copyright(c) 2024 Ericsson AB\n */\n \n+#include <inttypes.h>\n #include <stdbool.h>\n \n-#include <rte_launch.h>\n #include <rte_bitops.h>\n+#include <rte_cycles.h>\n+#include <rte_launch.h>\n+#include <rte_lcore.h>\n #include <rte_random.h>\n #include \"test.h\"\n \n@@ -64,6 +67,304 @@ GEN_TEST_BIT_ACCESS(test_bit_once_access64, rte_bit_once_set,\n \t\t rte_bit_once_clear, rte_bit_once_assign,\n \t\t rte_bit_once_flip, rte_bit_once_test, 64)\n \n+#define bit_atomic_set(addr, nr)\t\t\t\t\\\n+\trte_bit_atomic_set(addr, nr, rte_memory_order_relaxed)\n+\n+#define bit_atomic_clear(addr, nr)\t\t\t\t\t\\\n+\trte_bit_atomic_clear(addr, nr, rte_memory_order_relaxed)\n+\n+#define bit_atomic_assign(addr, nr, value)\t\t\t\t\\\n+\trte_bit_atomic_assign(addr, nr, value, rte_memory_order_relaxed)\n+\n+#define bit_atomic_flip(addr, nr)\t\t\t\t\t\\\n+ rte_bit_atomic_flip(addr, nr, rte_memory_order_relaxed)\n+\n+#define bit_atomic_test(addr, nr)\t\t\t\t\\\n+\trte_bit_atomic_test(addr, nr, rte_memory_order_relaxed)\n+\n+GEN_TEST_BIT_ACCESS(test_bit_atomic_access32, bit_atomic_set,\n+\t\t bit_atomic_clear, bit_atomic_assign,\n+\t\t bit_atomic_flip, bit_atomic_test, 32)\n+\n+GEN_TEST_BIT_ACCESS(test_bit_atomic_access64, bit_atomic_set,\n+\t\t bit_atomic_clear, bit_atomic_assign,\n+\t\t bit_atomic_flip, bit_atomic_test, 64)\n+\n+#define PARALLEL_TEST_RUNTIME 0.25\n+\n+#define GEN_TEST_BIT_PARALLEL_ASSIGN(size)\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstruct parallel_access_lcore ## size\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int bit;\t\t\t\t\t\\\n+\t\tuint ## size ##_t *word;\t\t\t\t\\\n+\t\tbool failed;\t\t\t\t\t\t\\\n+\t};\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\trun_parallel_assign ## size(void *arg)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_access_lcore ## size *lcore = arg;\t\\\n+\t\tuint64_t deadline = rte_get_timer_cycles() +\t\t\\\n+\t\t\tPARALLEL_TEST_RUNTIME * rte_get_timer_hz();\t\\\n+\t\tbool value = false;\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tbool new_value = rte_rand() & 1;\t\t\\\n+\t\t\tbool use_test_and_modify = rte_rand() & 1;\t\\\n+\t\t\tbool use_assign = rte_rand() & 1;\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tif (rte_bit_atomic_test(lcore->word, lcore->bit, \\\n+\t\t\t\t\t\trte_memory_order_relaxed) != value) { \\\n+\t\t\t\tlcore->failed = true;\t\t\t\\\n+\t\t\t\tbreak;\t\t\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tif (use_test_and_modify) {\t\t\t\\\n+\t\t\t\tbool old_value;\t\t\t\t\\\n+\t\t\t\tif (use_assign) \t\t\t\\\n+\t\t\t\t\told_value = rte_bit_atomic_test_and_assign( \\\n+\t\t\t\t\t\tlcore->word, lcore->bit, new_value, \\\n+\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\telse {\t\t\t\t\t\\\n+\t\t\t\t\told_value = new_value ?\t\t\\\n+\t\t\t\t\t\trte_bit_atomic_test_and_set( \\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed) : \\\n+\t\t\t\t\t\trte_bit_atomic_test_and_clear( \\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t\tif (old_value != value) {\t\t\\\n+\t\t\t\t\tlcore->failed = true;\t\t\\\n+\t\t\t\t\tbreak;\t\t\t\t\\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t} else {\t\t\t\t\t\\\n+\t\t\t\tif (use_assign)\t\t\t\t\\\n+\t\t\t\t\trte_bit_atomic_assign(lcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\t new_value, \\\n+\t\t\t\t\t\t\t rte_memory_order_relaxed); \\\n+\t\t\t\telse {\t\t\t\t\t\\\n+\t\t\t\t\tif (new_value)\t\t\t\\\n+\t\t\t\t\t\trte_bit_atomic_set(\t\\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\t\telse\t\t\t\t\\\n+\t\t\t\t\t\trte_bit_atomic_clear(\t\\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tvalue = new_value;\t\t\t\t\\\n+\t\t} while (rte_get_timer_cycles() < deadline);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn 0;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\ttest_bit_atomic_parallel_assign ## size(void)\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int worker_lcore_id;\t\t\t\t\\\n+\t\tuint ## size ## _t word = 0;\t\t\t\t\\\n+\t\tstruct parallel_access_lcore ## size lmain = {\t\t\\\n+\t\t\t.word = &word\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_access_lcore ## size lworker = {\t\\\n+\t\t\t.word = &word\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tif (rte_lcore_count() < 2) {\t\t\t\t\\\n+\t\t\tprintf(\"Need multiple cores to run parallel test.\\n\"); \\\n+\t\t\treturn TEST_SKIPPED;\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tworker_lcore_id = rte_get_next_lcore(-1, 1, 0);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tlmain.bit = rte_rand_max(size);\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tlworker.bit = rte_rand_max(size);\t\t\\\n+\t\t} while (lworker.bit == lmain.bit);\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tint rc = rte_eal_remote_launch(run_parallel_assign ## size, \\\n+\t\t\t\t\t &lworker, worker_lcore_id); \\\n+\t\tTEST_ASSERT(rc == 0, \"Worker thread launch failed\");\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trun_parallel_assign ## size(&lmain);\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trte_eal_mp_wait_lcore();\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(!lmain.failed, \"Main lcore atomic access failed\"); \\\n+\t\tTEST_ASSERT(!lworker.failed, \"Worker lcore atomic access \" \\\n+\t\t\t \"failed\");\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn TEST_SUCCESS;\t\t\t\t\t\\\n+\t}\n+\n+GEN_TEST_BIT_PARALLEL_ASSIGN(32)\n+GEN_TEST_BIT_PARALLEL_ASSIGN(64)\n+\n+#define GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(size)\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstruct parallel_test_and_set_lcore ## size\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tuint ## size ##_t *word;\t\t\t\t\\\n+\t\tunsigned int bit;\t\t\t\t\t\\\n+\t\tuint64_t flips;\t\t\t\t\t\t\\\n+\t};\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\trun_parallel_test_and_modify ## size(void *arg)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_test_and_set_lcore ## size *lcore = arg; \\\n+\t\tuint64_t deadline = rte_get_timer_cycles() +\t\t\\\n+\t\t\tPARALLEL_TEST_RUNTIME * rte_get_timer_hz();\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tbool old_value;\t\t\t\t\t\\\n+\t\t\tbool new_value = rte_rand() & 1;\t\t\\\n+\t\t\tbool use_assign = rte_rand() & 1;\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tif (use_assign)\t\t\t\t\t\\\n+\t\t\t\told_value = rte_bit_atomic_test_and_assign( \\\n+\t\t\t\t\tlcore->word, lcore->bit, new_value, \\\n+\t\t\t\t\trte_memory_order_relaxed);\t\\\n+\t\t\telse\t\t\t\t\t\t\\\n+\t\t\t\told_value = new_value ?\t\t\t\\\n+\t\t\t\t\trte_bit_atomic_test_and_set(\t\\\n+\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\trte_memory_order_relaxed) : \\\n+\t\t\t\t\trte_bit_atomic_test_and_clear(\t\\\n+\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\tif (old_value != new_value)\t\t\t\\\n+\t\t\t\tlcore->flips++;\t\t\t\t\\\n+\t\t} while (rte_get_timer_cycles() < deadline);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn 0;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\ttest_bit_atomic_parallel_test_and_modify ## size(void)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int worker_lcore_id;\t\t\t\t\\\n+\t\tuint ## size ## _t word = 0;\t\t\t\t\\\n+\t\tunsigned int bit = rte_rand_max(size);\t\t\t\\\n+\t\tstruct parallel_test_and_set_lcore ## size lmain = {\t\\\n+\t\t\t.word = &word,\t\t\t\t\t\\\n+\t\t\t.bit = bit\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_test_and_set_lcore ## size lworker = {\t\\\n+\t\t\t.word = &word,\t\t\t\t\t\\\n+\t\t\t.bit = bit\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tif (rte_lcore_count() < 2) {\t\t\t\t\\\n+\t\t\tprintf(\"Need multiple cores to run parallel test.\\n\"); \\\n+\t\t\treturn TEST_SKIPPED;\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tworker_lcore_id = rte_get_next_lcore(-1, 1, 0);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tint rc = rte_eal_remote_launch(run_parallel_test_and_modify ## size, \\\n+\t\t\t\t\t &lworker, worker_lcore_id); \\\n+\t\tTEST_ASSERT(rc == 0, \"Worker thread launch failed\");\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trun_parallel_test_and_modify ## size(&lmain);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trte_eal_mp_wait_lcore();\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t total_flips = lmain.flips + lworker.flips;\t\\\n+\t\tbool expected_value = total_flips % 2;\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_value == rte_bit_test(&word, bit), \\\n+\t\t\t \"After %\"PRId64\" flips, the bit value \"\t\\\n+\t\t\t \"should be %d\", total_flips, expected_value); \\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t expected_word = 0;\t\t\t\t\\\n+\t\trte_bit_assign(&expected_word, bit, expected_value);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_word == word, \"Untouched bits have \" \\\n+\t\t\t \"changed value\");\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn TEST_SUCCESS;\t\t\t\t\t\\\n+\t}\n+\n+GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(32)\n+GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(64)\n+\n+#define GEN_TEST_BIT_PARALLEL_FLIP(size)\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstruct parallel_flip_lcore ## size\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tuint ## size ##_t *word;\t\t\t\t\\\n+\t\tunsigned int bit;\t\t\t\t\t\\\n+\t\tuint64_t flips;\t\t\t\t\t\t\\\n+\t};\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\trun_parallel_flip ## size(void *arg)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_flip_lcore ## size *lcore = arg; \\\n+\t\tuint64_t deadline = rte_get_timer_cycles() +\t\t\\\n+\t\t\tPARALLEL_TEST_RUNTIME * rte_get_timer_hz();\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\trte_bit_atomic_flip(lcore->word, lcore->bit,\t\\\n+\t\t\t\t\t rte_memory_order_relaxed);\t\\\n+\t\t\tlcore->flips++;\t\t\t\t\t\\\n+\t\t} while (rte_get_timer_cycles() < deadline);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn 0;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\ttest_bit_atomic_parallel_flip ## size(void)\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int worker_lcore_id;\t\t\t\t\\\n+\t\tuint ## size ## _t word = 0;\t\t\t\t\\\n+\t\tunsigned int bit = rte_rand_max(size);\t\t\t\\\n+\t\tstruct parallel_flip_lcore ## size lmain = {\t\t\\\n+\t\t\t.word = &word,\t\t\t\t\t\\\n+\t\t\t.bit = bit\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_flip_lcore ## size lworker = {\t\t\\\n+\t\t\t.word = &word,\t\t\t\t\t\\\n+\t\t\t.bit = bit\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tif (rte_lcore_count() < 2) {\t\t\t\t\\\n+\t\t\tprintf(\"Need multiple cores to run parallel test.\\n\"); \\\n+\t\t\treturn TEST_SKIPPED;\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tworker_lcore_id = rte_get_next_lcore(-1, 1, 0);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tint rc = rte_eal_remote_launch(run_parallel_flip ## size, \\\n+\t\t\t\t\t &lworker, worker_lcore_id); \\\n+\t\tTEST_ASSERT(rc == 0, \"Worker thread launch failed\");\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trun_parallel_flip ## size(&lmain);\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trte_eal_mp_wait_lcore();\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t total_flips = lmain.flips + lworker.flips;\t\\\n+\t\tbool expected_value = total_flips % 2;\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_value == rte_bit_test(&word, bit), \\\n+\t\t\t \"After %\"PRId64\" flips, the bit value \"\t\\\n+\t\t\t \"should be %d\", total_flips, expected_value); \\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t expected_word = 0;\t\t\t\t\\\n+\t\trte_bit_assign(&expected_word, bit, expected_value);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_word == word, \"Untouched bits have \" \\\n+\t\t\t \"changed value\");\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn TEST_SUCCESS;\t\t\t\t\t\\\n+\t}\n+\n+GEN_TEST_BIT_PARALLEL_FLIP(32)\n+GEN_TEST_BIT_PARALLEL_FLIP(64)\n+\n static uint32_t val32;\n static uint64_t val64;\n \n@@ -182,6 +483,18 @@ static struct unit_test_suite test_suite = {\n \t\tTEST_CASE(test_bit_access64),\n \t\tTEST_CASE(test_bit_once_access32),\n \t\tTEST_CASE(test_bit_once_access64),\n+\t\tTEST_CASE(test_bit_access32),\n+\t\tTEST_CASE(test_bit_access64),\n+\t\tTEST_CASE(test_bit_once_access32),\n+\t\tTEST_CASE(test_bit_once_access64),\n+\t\tTEST_CASE(test_bit_atomic_access32),\n+\t\tTEST_CASE(test_bit_atomic_access64),\n+\t\tTEST_CASE(test_bit_atomic_parallel_assign32),\n+\t\tTEST_CASE(test_bit_atomic_parallel_assign64),\n+\t\tTEST_CASE(test_bit_atomic_parallel_test_and_modify32),\n+\t\tTEST_CASE(test_bit_atomic_parallel_test_and_modify64),\n+\t\tTEST_CASE(test_bit_atomic_parallel_flip32),\n+\t\tTEST_CASE(test_bit_atomic_parallel_flip64),\n \t\tTEST_CASE(test_bit_relaxed_set),\n \t\tTEST_CASE(test_bit_relaxed_clear),\n \t\tTEST_CASE(test_bit_relaxed_test_set_clear),\n", "prefixes": [ "RFC", "v5", "6/6" ] }