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GET /api/patches/139677/?format=api
{ "id": 139677, "url": "http://patches.dpdk.org/api/patches/139677/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240425085853.97888-7-mattias.ronnblom@ericsson.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240425085853.97888-7-mattias.ronnblom@ericsson.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240425085853.97888-7-mattias.ronnblom@ericsson.com", "date": "2024-04-25T08:58:53", "name": "[RFC,v2,6/6] eal: add unit tests for atomic bit access functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "2e1c24a1f7a7d49443d778ef4988d49c07e14446", "submitter": { "id": 1077, "url": "http://patches.dpdk.org/api/people/1077/?format=api", "name": "Mattias Rönnblom", "email": "mattias.ronnblom@ericsson.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240425085853.97888-7-mattias.ronnblom@ericsson.com/mbox/", "series": [ { "id": 31818, "url": "http://patches.dpdk.org/api/series/31818/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31818", "date": "2024-04-25T08:58:47", "name": "Improve EAL bit operations API", "version": 2, "mbox": "http://patches.dpdk.org/series/31818/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139677/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/139677/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4A62A43F04;\n\tThu, 25 Apr 2024 11:10:36 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 581C7436E1;\n\tThu, 25 Apr 2024 11:10:08 +0200 (CEST)", "from EUR04-VI1-obe.outbound.protection.outlook.com\n (mail-vi1eur04on2082.outbound.protection.outlook.com [40.107.8.82])\n by mails.dpdk.org (Postfix) with ESMTP id F3038436D2\n for <dev@dpdk.org>; Thu, 25 Apr 2024 11:10:03 +0200 (CEST)", "from DUZPR01CA0172.eurprd01.prod.exchangelabs.com\n (2603:10a6:10:4b3::29) by AS8PR07MB7959.eurprd07.prod.outlook.com\n (2603:10a6:20b:352::14) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Thu, 25 Apr\n 2024 09:10:02 +0000", "from DB1PEPF000509E7.eurprd03.prod.outlook.com\n (2603:10a6:10:4b3:cafe::bb) by DUZPR01CA0172.outlook.office365.com\n (2603:10a6:10:4b3::29) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.23 via Frontend\n Transport; Thu, 25 Apr 2024 09:10:02 +0000", "from oa.msg.ericsson.com (192.176.1.74) by\n DB1PEPF000509E7.mail.protection.outlook.com (10.167.242.57) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7519.19 via Frontend Transport; Thu, 25 Apr 2024 09:10:01 +0000", "from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by\n smtp-central.internal.ericsson.com (100.87.178.63) with Microsoft SMTP Server\n id 15.2.1258.12; Thu, 25 Apr 2024 11:09:59 +0200", "from breslau.. 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helo=oa.msg.ericsson.com; pr=C", "From": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "To": "<dev@dpdk.org>", "CC": "<hofors@lysator.liu.se>, Heng Wang <heng.wang@ericsson.com>,\n \"Stephen Hemminger\" <stephen@networkplumber.org>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>, =?utf-8?q?Mattias_R=C3=B6nnb?=\n\t=?utf-8?q?lom?= <mattias.ronnblom@ericsson.com>", "Subject": "[RFC v2 6/6] eal: add unit tests for atomic bit access functions", "Date": "Thu, 25 Apr 2024 10:58:53 +0200", "Message-ID": "<20240425085853.97888-7-mattias.ronnblom@ericsson.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240425085853.97888-1-mattias.ronnblom@ericsson.com>", "References": "<20240302135328.531940-2-mattias.ronnblom@ericsson.com>\n <20240425085853.97888-1-mattias.ronnblom@ericsson.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DB1PEPF000509E7:EE_|AS8PR07MB7959:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4b0a77bc-1641-4586-0750-08dc65077d04", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "=?utf-8?q?g3/2zHT16FVO92OoOlyRUGHIdNZkJfb?=\n\t=?utf-8?q?TC87puTswdHjr8Af5mjgeuoBWtERKMF4o4ZtKWrl/ZZsKPtgKYHXvD9JUfrD3yHqF?=\n\t=?utf-8?q?b7+HBR6onzpv7QY9BsJC675SBe9nACAJgpFNd3Wna9+YZztfO7PzWpCFFB5MDQ2NZ?=\n\t=?utf-8?q?IWBrzuorKBT2GYiQIKJxPKMxrI3Vv9VWwdvf2195libhIMTFQ3GF2iVXRWuGfU37X?=\n\t=?utf-8?q?QWO/84Hr1C74C2vkXFE3R0LEmFevssRczzuW+qiZSEtTsfnkLie75rRARebplfVzy?=\n\t=?utf-8?q?I8E7D0mYFAGGcxbWAkngffKKF4ODoslVi2ue6m8Vjz27wyjluFutAbBptW+yrhovg?=\n\t=?utf-8?q?ySMBrP87Dtv6HUkW91D4hPugi14JiCFKBSc5DGO9N47urbDkVB9Ld+ieFt6nAM3eM?=\n\t=?utf-8?q?uAfcPVMZb8HRY8i6ZW8/sZ6koNzhpJY9xj1fgQJgtZTnEMewWQ7LMtVoBnS/Hdspl?=\n\t=?utf-8?q?mdulzFS4ZBbSmu73V4lT1IHzLPT1daZ/Qtd9y5YDawRTJ4vanKtccxmxJAUvT1HxE?=\n\t=?utf-8?q?rRcVpbrH/KvkANZItXSwCyIQORjASJ32qztJAHzdIuMUD6ig9V9bRT/Bnoe6b9XMW?=\n\t=?utf-8?q?MGufMgHRlm8D92lW81aAA/l5ppwiPjqnSKxqbT3y5+kST07Scc9ISDhS7JnqFF9nG?=\n\t=?utf-8?q?oFi/EGiwY73KrItWqzbXxoZkV0NpT0GTZ2dkXRVIFY4n4GxbNunuQIT003RQwxP+c?=\n\t=?utf-8?q?85QEhCejxgkI+1R9IIV1ISttv2qLG0tDZysO7xQZQ7FmS+sglOu0BS7T0+Ctu/qD4?=\n\t=?utf-8?q?hN+5MNo7ZCOhlYAlwJP4HI6h2Fc7Ca4lut8Kg0X4pBrEf+nu9fmkcZc8IYZOaaHk9?=\n\t=?utf-8?q?CZwUEFVKGtVPzxiRRy6yM3EcJa/DY187ialdlXfLD6bK/9jdOLODv2jI0JKe6Ayil?=\n\t=?utf-8?q?q11ZaevvzPS3jl9yAxegZqGuGqvvwlV9pBSEq+sXzR+pXT2cI7+IeETbAtbZb3KJs?=\n\t=?utf-8?q?VaqPR0gjitKTlC/0urI+7SPm97hEz+YRk7Ub1Rz/VlLJ+eAShmT3HMz3D5lKtMiS8?=\n\t=?utf-8?q?/zcappbf5jsfRsxlRM5ZjYsn8JirAXuqo60j7tFzd9Aq0JNpVca9AHpJXkwrZoQ7d?=\n\t=?utf-8?q?+7Us3V8wliTOXbl/rXKEbu2w0jnMVbwM8khROoHAC5usUGm6Zb8g0Wqae+9S8MduE?=\n\t=?utf-8?q?YglkUux1u/i0/p5x8WMp5NZOYoXbPSDfVFrbyDFuuZ4DX250zd9/M5mW99gsCC5DB?=\n\t=?utf-8?q?haHPo4Z1hdzoJd79+wz4cmn4vRLkVEo2m0Ft7DWN6aclVLCvqxxBLQ5TZTfhTqFvo?=\n\t=?utf-8?q?HQhA9t5YO5ovAqj4eUDAVVBNM7cBUh1zP9EqAakc9DWaDiO7Awx8VH8WTxeF5o33O?=\n\t=?utf-8?q?AGWQlZ/FkSVq?=", "X-Forefront-Antispam-Report": "CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net;\n CAT:NONE; SFS:(13230031)(82310400014)(1800799015)(376005)(36860700004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "ericsson.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Apr 2024 09:10:01.5422 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4b0a77bc-1641-4586-0750-08dc65077d04", "X-MS-Exchange-CrossTenant-Id": "92e84ceb-fbfd-47ab-be52-080c6b87953f", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74];\n Helo=[oa.msg.ericsson.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DB1PEPF000509E7.eurprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AS8PR07MB7959", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Extend bitops tests to cover the\nrte_bit_atomic_[set|clear|assign|test|test_and_[set|clear|assign]]()\nfamily of functions.\n\nSigned-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>\n---\n app/test/test_bitops.c | 233 ++++++++++++++++++++++++++++++++++-\n lib/eal/include/rte_bitops.h | 1 -\n 2 files changed, 232 insertions(+), 2 deletions(-)", "diff": "diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c\nindex 12c1027e36..a0967260aa 100644\n--- a/app/test/test_bitops.c\n+++ b/app/test/test_bitops.c\n@@ -3,10 +3,13 @@\n * Copyright(c) 2024 Ericsson AB\n */\n \n+#include <inttypes.h>\n #include <stdbool.h>\n \n-#include <rte_launch.h>\n #include <rte_bitops.h>\n+#include <rte_cycles.h>\n+#include <rte_launch.h>\n+#include <rte_lcore.h>\n #include <rte_random.h>\n #include \"test.h\"\n \n@@ -60,6 +63,228 @@ GEN_TEST_BIT_ACCESS(test_bit_once_access_64, rte_bit_once_set,\t\t\\\n \t\t rte_bit_once_clear, rte_bit_once_assign,\t\t\\\n \t\t rte_bit_once_test, 64)\n \n+#define bit_atomic_set(addr, nr)\t\t\t\t\\\n+\trte_bit_atomic_set(addr, nr, rte_memory_order_relaxed)\n+\n+#define bit_atomic_clear(addr, nr)\t\t\t\t\t\\\n+\trte_bit_atomic_clear(addr, nr, rte_memory_order_relaxed)\n+\n+#define bit_atomic_assign(addr, nr, value)\t\t\t\t\\\n+\trte_bit_atomic_assign(addr, nr, value, rte_memory_order_relaxed)\n+\n+#define bit_atomic_test(addr, nr)\t\t\t\t\\\n+\trte_bit_atomic_test(addr, nr, rte_memory_order_relaxed)\n+\n+GEN_TEST_BIT_ACCESS(test_bit_atomic_access_32, bit_atomic_set,\t\\\n+\t\t bit_atomic_clear, bit_atomic_assign,\t\\\n+\t\t bit_atomic_test, 32)\n+\n+GEN_TEST_BIT_ACCESS(test_bit_atomic_access_64, bit_atomic_set,\t\\\n+\t\t bit_atomic_clear, bit_atomic_assign,\t\\\n+\t\t bit_atomic_test, 64)\n+\n+#define PARALLEL_TEST_RUNTIME 0.25\n+\n+#define GEN_TEST_BIT_PARALLEL_ASSIGN(size)\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstruct parallel_access_lcore_ ## size\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int bit;\t\t\t\t\t\\\n+\t\tuint ## size ##_t *word;\t\t\t\t\\\n+\t\tbool failed;\t\t\t\t\t\t\\\n+\t};\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\trun_parallel_assign_ ## size(void *arg)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_access_lcore_ ## size *lcore = arg;\t\\\n+\t\tuint64_t deadline = rte_get_timer_cycles() +\t\t\\\n+\t\t\tPARALLEL_TEST_RUNTIME * rte_get_timer_hz();\t\\\n+\t\tbool value = false;\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tbool new_value = rte_rand() & 1;\t\t\\\n+\t\t\tbool use_test_and_modify = rte_rand() & 1;\t\\\n+\t\t\tbool use_assign = rte_rand() & 1;\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tif (rte_bit_atomic_test(lcore->word, lcore->bit, \\\n+\t\t\t\t\t\trte_memory_order_relaxed) != value) { \\\n+\t\t\t\tlcore->failed = true;\t\t\t\\\n+\t\t\t\tbreak;\t\t\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tif (use_test_and_modify) {\t\t\t\\\n+\t\t\t\tbool old_value;\t\t\t\t\\\n+\t\t\t\tif (use_assign) \t\t\t\\\n+\t\t\t\t\told_value = rte_bit_atomic_test_and_assign( \\\n+\t\t\t\t\t\tlcore->word, lcore->bit, new_value, \\\n+\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\telse {\t\t\t\t\t\\\n+\t\t\t\t\told_value = new_value ?\t\t\\\n+\t\t\t\t\t\trte_bit_atomic_test_and_set( \\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed) : \\\n+\t\t\t\t\t\trte_bit_atomic_test_and_clear( \\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t\tif (old_value != value) {\t\t\\\n+\t\t\t\t\tlcore->failed = true;\t\t\\\n+\t\t\t\t\tbreak;\t\t\t\t\\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t} else {\t\t\t\t\t\\\n+\t\t\t\tif (use_assign)\t\t\t\t\\\n+\t\t\t\t\trte_bit_atomic_assign(lcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\t new_value, \\\n+\t\t\t\t\t\t\t rte_memory_order_relaxed); \\\n+\t\t\t\telse {\t\t\t\t\t\\\n+\t\t\t\t\tif (new_value)\t\t\t\\\n+\t\t\t\t\t\trte_bit_atomic_set(\t\\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\t\telse\t\t\t\t\\\n+\t\t\t\t\t\trte_bit_atomic_clear(\t\\\n+\t\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\t\t}\t\t\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tvalue = new_value;\t\t\t\t\\\n+\t\t} while (rte_get_timer_cycles() < deadline);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn 0;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\ttest_bit_atomic_parallel_assign_ ## size(void)\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int worker_lcore_id;\t\t\t\t\\\n+\t\tuint ## size ## _t word = 0;\t\t\t\t\\\n+\t\tstruct parallel_access_lcore_ ## size main = {\t\t\\\n+\t\t\t.word = &word\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_access_lcore_ ## size worker = {\t\\\n+\t\t\t.word = &word\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tif (rte_lcore_count() < 2) {\t\t\t\t\\\n+\t\t\tprintf(\"Need multiple cores to run parallel test.\\n\"); \\\n+\t\t\treturn TEST_SKIPPED;\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tworker_lcore_id = rte_get_next_lcore(-1, 1, 0);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tmain.bit = rte_rand_max(size);\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tworker.bit = rte_rand_max(size);\t\t\\\n+\t\t} while (worker.bit == main.bit);\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tint rc = rte_eal_remote_launch(run_parallel_assign_ ## size, \\\n+\t\t\t\t\t &worker,\tworker_lcore_id); \\\n+\t\tTEST_ASSERT(rc == 0, \"Worker thread launch failed\");\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trun_parallel_assign_ ## size(&main);\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trte_eal_mp_wait_lcore();\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(!main.failed, \"Main lcore atomic access failed\"); \\\n+\t\tTEST_ASSERT(!worker.failed, \"Worker lcore atomic access \" \\\n+\t\t\t \"failed\");\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn TEST_SUCCESS;\t\t\t\t\t\\\n+\t}\n+\n+GEN_TEST_BIT_PARALLEL_ASSIGN(32)\n+GEN_TEST_BIT_PARALLEL_ASSIGN(64)\n+\n+#define GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(size)\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstruct parallel_test_and_set_lcore_ ## size\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tuint ## size ##_t *word;\t\t\t\t\\\n+\t\tunsigned int bit;\t\t\t\t\t\\\n+\t\tuint64_t flips;\t\t\t\t\t\t\\\n+\t};\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\trun_parallel_test_and_modify_ ## size(void *arg)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_test_and_set_lcore_ ## size *lcore = arg; \\\n+\t\tuint64_t deadline = rte_get_timer_cycles() +\t\t\\\n+\t\t\tPARALLEL_TEST_RUNTIME * rte_get_timer_hz();\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tbool old_value;\t\t\t\t\t\\\n+\t\t\tbool new_value = rte_rand() & 1;\t\t\\\n+\t\t\tbool use_assign = rte_rand() & 1;\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\t\tif (use_assign)\t\t\t\t\t\\\n+\t\t\t\told_value = rte_bit_atomic_test_and_assign( \\\n+\t\t\t\t\tlcore->word, lcore->bit, new_value, \\\n+\t\t\t\t\trte_memory_order_relaxed);\t\\\n+\t\t\telse\t\t\t\t\t\t\\\n+\t\t\t\told_value = new_value ?\t\t\t\\\n+\t\t\t\t\trte_bit_atomic_test_and_set(\t\\\n+\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\trte_memory_order_relaxed) : \\\n+\t\t\t\t\trte_bit_atomic_test_and_clear(\t\\\n+\t\t\t\t\t\tlcore->word, lcore->bit, \\\n+\t\t\t\t\t\trte_memory_order_relaxed); \\\n+\t\t\tif (old_value != new_value)\t\t\t\\\n+\t\t\t\tlcore->flips++;\t\t\t\t\\\n+\t\t} while (rte_get_timer_cycles() < deadline);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn 0;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tstatic int\t\t\t\t\t\t\t\\\n+\ttest_bit_atomic_parallel_test_and_modify_ ## size(void)\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tunsigned int worker_lcore_id;\t\t\t\t\\\n+\t\tuint ## size ## _t word = 0;\t\t\t\t\\\n+\t\tunsigned int bit = rte_rand_max(size);\t\t\t\\\n+\t\tstruct parallel_test_and_set_lcore_ ## size main = {\t\\\n+\t\t\t.word = &word,\t\t\t\t \\\n+\t\t\t.bit = bit \\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\tstruct parallel_test_and_set_lcore_ ## size worker = {\t\\\n+\t\t\t.word = &word,\t\t\t\t\t\\\n+\t\t\t.bit = bit\t\t\t\t\t\\\n+\t\t};\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tif (rte_lcore_count() < 2) {\t\t\t\t\\\n+\t\t\tprintf(\"Need multiple cores to run parallel test.\\n\"); \\\n+\t\t\treturn TEST_SKIPPED;\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tworker_lcore_id = rte_get_next_lcore(-1, 1, 0);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tint rc = rte_eal_remote_launch(run_parallel_test_and_modify_ ## size, \\\n+\t\t\t\t\t &worker,\tworker_lcore_id); \\\n+\t\tTEST_ASSERT(rc == 0, \"Worker thread launch failed\");\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trun_parallel_test_and_modify_ ## size(&main);\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\trte_eal_mp_wait_lcore();\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t total_flips = main.flips + worker.flips;\t\\\n+\t\tbool expected_value = total_flips % 2;\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_value == rte_bit_test(&word, bit), \\\n+\t\t\t \"After %\"PRId64\" flips, the bit value \"\t\\\n+\t\t\t \"should be %d\", total_flips, expected_value); \\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint64_t expected_word = 0;\t\t\t\t\\\n+\t\trte_bit_assign(&expected_word, bit, expected_value);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tTEST_ASSERT(expected_word == word, \"Untouched bits have \" \\\n+\t\t\t \"changed value\");\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\treturn TEST_SUCCESS;\t\t\t\t\t\\\n+\t}\n+\n+GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(32)\n+GEN_TEST_BIT_PARALLEL_TEST_AND_MODIFY(64)\n+\n static uint32_t val32;\n static uint64_t val64;\n \n@@ -178,6 +403,12 @@ static struct unit_test_suite test_suite = {\n \t\tTEST_CASE(test_bit_access_64),\n \t\tTEST_CASE(test_bit_once_access_32),\n \t\tTEST_CASE(test_bit_once_access_64),\n+\t\tTEST_CASE(test_bit_atomic_access_32),\n+\t\tTEST_CASE(test_bit_atomic_access_64),\n+\t\tTEST_CASE(test_bit_atomic_parallel_assign_32),\n+\t\tTEST_CASE(test_bit_atomic_parallel_assign_64),\n+\t\tTEST_CASE(test_bit_atomic_parallel_test_and_modify_32),\n+\t\tTEST_CASE(test_bit_atomic_parallel_test_and_modify_64),\n \t\tTEST_CASE(test_bit_relaxed_set),\n \t\tTEST_CASE(test_bit_relaxed_clear),\n \t\tTEST_CASE(test_bit_relaxed_test_set_clear),\ndiff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h\nindex 8c38a1ac03..bc6d79086b 100644\n--- a/lib/eal/include/rte_bitops.h\n+++ b/lib/eal/include/rte_bitops.h\n@@ -485,7 +485,6 @@ extern \"C\" {\n \t\t uint32_t *: __rte_bit_atomic_test_and_clear32,\t\t\\\n \t\t uint64_t *: __rte_bit_atomic_test_and_clear64)(addr, nr, \\\n \t\t\t\t\t\t\t\tmemory_order)\n-\n /**\n * @warning\n * @b EXPERIMENTAL: this API may change without prior notice.\n", "prefixes": [ "RFC", "v2", "6/6" ] }