Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/139540/?format=api
{ "id": 139540, "url": "http://patches.dpdk.org/api/patches/139540/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240419064319.149-8-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240419064319.149-8-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240419064319.149-8-anoobj@marvell.com", "date": "2024-04-19T06:43:19", "name": "[v3,7/7] dma/odm: add remaining ops", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "845fc55bd87aacb60e4425c769b2574e7ff9beb6", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240419064319.149-8-anoobj@marvell.com/mbox/", "series": [ { "id": 31789, "url": "http://patches.dpdk.org/api/series/31789/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31789", "date": "2024-04-19T06:43:12", "name": "Add ODM DMA device", "version": 3, "mbox": "http://patches.dpdk.org/series/31789/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139540/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/139540/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6861643EAC;\n\tFri, 19 Apr 2024 08:44:18 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B69DF40A6D;\n\tFri, 19 Apr 2024 08:43:49 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id AE6D7406B8\n for <dev@dpdk.org>; Fri, 19 Apr 2024 08:43:47 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 43ILYmcW010585; Thu, 18 Apr 2024 23:43:47 -0700", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3xjhecq8ug-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Thu, 18 Apr 2024 23:43:46 -0700 (PDT)", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.4; Thu, 18 Apr 2024 23:43:44 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend\n Transport; Thu, 18 Apr 2024 23:43:44 -0700", "from BG-LT92004.corp.innovium.com (BG-LT92004.marvell.com\n [10.28.163.189])\n by maili.marvell.com (Postfix) with ESMTP id 5A60C5B6933;\n Thu, 18 Apr 2024 23:43:42 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=0iFhdggkUONNdEvQ/0kv0OB54Hd3402AMEVCmYOuKJI=; b=Tve\n fCJhymJF0GBuV2maYrvPiPceQ3UvoryUrx8L/queYlElwe3Cmsk2+m7SCxVXqbyR\n q2//4ylGkeMT/JJ2Z4KepAJB/DG84MiZUTWnkVFBRF0w+e0/xL+oo6mZC8dk8UZf\n QfL/sI3sUbni0DC5KGlpMuH1wHEN3RytaE1nyW+Dmd6DkRJ3obHRS2Fqxq4BH5rx\n MfPHpmbga+TvFtlWL8hNo6hFai/Ga6ezEW2DItneOh66lTqpl6WlH8GddbhuNDh4\n AZD9vTnigd9mCLTye9p3KERBivj4anCnOmQ7YE/HKs090jnzMP7m47bnNiGn1jYk\n jOS6O3MlbsIwkzkk7Qg==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Chengwen Feng <fengchengwen@huawei.com>, Kevin Laatz\n <kevin.laatz@intel.com>, Bruce Richardson <bruce.richardson@intel.com>,\n \"Jerin Jacob\" <jerinj@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Vidya Sagar Velumuri <vvelumuri@marvell.com>, Gowrishankar Muthukrishnan\n <gmuthukrishn@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v3 7/7] dma/odm: add remaining ops", "Date": "Fri, 19 Apr 2024 12:13:19 +0530", "Message-ID": "<20240419064319.149-8-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240419064319.149-1-anoobj@marvell.com>", "References": "<20240417072708.322-1-anoobj@marvell.com>\n <20240419064319.149-1-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "fF4qSHNRL3pJhFED37tAxVaG0rSja8xk", "X-Proofpoint-GUID": "fF4qSHNRL3pJhFED37tAxVaG0rSja8xk", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-04-19_04,2024-04-17_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n\nAdd all remaining ops such as fill, burst_capacity etc. Also update the\ndocumentation.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n---\n MAINTAINERS | 1 +\n doc/guides/dmadevs/index.rst | 1 +\n doc/guides/dmadevs/odm.rst | 92 +++++++++++++\n drivers/dma/odm/odm.h | 4 +\n drivers/dma/odm/odm_dmadev.c | 250 +++++++++++++++++++++++++++++++++++\n 5 files changed, 348 insertions(+)\n create mode 100644 doc/guides/dmadevs/odm.rst", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex b8d2f7b3d8..38293008aa 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1273,6 +1273,7 @@ M: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\n M: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n T: git://dpdk.org/next/dpdk-next-net-mrvl\n F: drivers/dma/odm/\n+F: doc/guides/dmadevs/odm.rst\n \n NXP DPAA DMA\n M: Gagandeep Singh <g.singh@nxp.com>\ndiff --git a/doc/guides/dmadevs/index.rst b/doc/guides/dmadevs/index.rst\nindex 5bd25b32b9..ce9f6eb260 100644\n--- a/doc/guides/dmadevs/index.rst\n+++ b/doc/guides/dmadevs/index.rst\n@@ -17,3 +17,4 @@ an application through DMA API.\n hisilicon\n idxd\n ioat\n+ odm\ndiff --git a/doc/guides/dmadevs/odm.rst b/doc/guides/dmadevs/odm.rst\nnew file mode 100644\nindex 0000000000..a2eaab59a0\n--- /dev/null\n+++ b/doc/guides/dmadevs/odm.rst\n@@ -0,0 +1,92 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2024 Marvell.\n+\n+Odyssey ODM DMA Device Driver\n+=============================\n+\n+The ``odm`` DMA device driver provides a poll-mode driver (PMD) for Marvell Odyssey\n+DMA Hardware Accelerator block found in Odyssey SoC. The block supports only mem\n+to mem DMA transfers.\n+\n+ODM DMA device can support up to 32 queues and 16 VFs.\n+\n+Prerequisites and Compilation procedure\n+---------------------------------------\n+\n+Device Setup\n+-------------\n+\n+ODM DMA device is initialized by kernel PF driver. The PF kernel driver is part\n+of Marvell software packages for Odyssey.\n+\n+Kernel module can be inserted as in below example::\n+\n+ $ sudo insmod odyssey_odm.ko\n+\n+ODM DMA device can support up to 16 VFs::\n+\n+ $ sudo echo 16 > /sys/bus/pci/devices/0000\\:08\\:00.0/sriov_numvfs\n+\n+Above command creates 16 VFs with 2 queues each.\n+\n+The ``dpdk-devbind.py`` script, included with DPDK, can be used to show the\n+presence of supported hardware. Running ``dpdk-devbind.py --status-dev dma``\n+will show all the Odyssey ODM DMA devices.\n+\n+Devices using VFIO drivers\n+~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The HW devices to be used will need to be bound to a user-space IO driver.\n+The ``dpdk-devbind.py`` script can be used to view the state of the devices\n+and to bind them to a suitable DPDK-supported driver, such as ``vfio-pci``.\n+For example::\n+\n+ $ dpdk-devbind.py -b vfio-pci 0000:08:00.1\n+\n+Device Probing and Initialization\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+To use the devices from an application, the dmadev API can be used.\n+\n+Once configured, the device can then be made ready for use\n+by calling the ``rte_dma_start()`` API.\n+\n+Performing Data Copies\n+~~~~~~~~~~~~~~~~~~~~~~\n+\n+Refer to the :ref:`Enqueue / Dequeue APIs <dmadev_enqueue_dequeue>` section\n+of the dmadev library documentation for details on operation enqueue and\n+submission API usage.\n+\n+Performance Tuning Parameters\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+To achieve higher performance, DMA device needs to be tuned using PF kernel\n+driver module parameters.\n+\n+Following options are exposed by kernel PF driver via devlink interface for\n+tuning performance.\n+\n+``eng_sel``\n+\n+ ODM DMA device has 2 engines internally. Engine to queue mapping is decided\n+ by a hardware register which can be configured as below::\n+\n+ $ /sbin/devlink dev param set pci/0000:08:00.0 name eng_sel value 3435973836 cmode runtime\n+\n+ Each bit in the register corresponds to one queue. Each queue would be\n+ associated with one engine. If the value of the bit corresponding to the queue\n+ is 0, then engine 0 would be picked. If it is 1, then engine 1 would be\n+ picked.\n+\n+ In the above command, the register value is set as\n+ ``1100 1100 1100 1100 1100 1100 1100 1100`` which allows for alternate engines\n+ to be used with alternate VFs (assuming the system has 16 VFs with 2 queues\n+ each).\n+\n+``max_load_request``\n+\n+ Specifies maximum outstanding load requests on internal bus. Values can range\n+ from 1 to 512. Set to 512 for maximum requests in flight.::\n+\n+ $ /sbin/devlink dev param set pci/0000:08:00.0 name max_load_request value 512 cmode runtime\ndiff --git a/drivers/dma/odm/odm.h b/drivers/dma/odm/odm.h\nindex e1373e0c7f..1d60d2d11a 100644\n--- a/drivers/dma/odm/odm.h\n+++ b/drivers/dma/odm/odm.h\n@@ -75,6 +75,10 @@ extern int odm_logtype;\n \trte_log(RTE_LOG_INFO, odm_logtype, \\\n \t\tRTE_FMT(\"%s(): %u\" RTE_FMT_HEAD(__VA_ARGS__, ), __func__, __LINE__, \\\n \t\t\tRTE_FMT_TAIL(__VA_ARGS__, )))\n+#define odm_debug(...) \\\n+\trte_log(RTE_LOG_DEBUG, odm_logtype, \\\n+\t\tRTE_FMT(\"%s(): %u\" RTE_FMT_HEAD(__VA_ARGS__, ), __func__, __LINE__, \\\n+\t\t\tRTE_FMT_TAIL(__VA_ARGS__, )))\n \n #define ODM_MEMZONE_FLAGS \\\n \t(RTE_MEMZONE_1GB | RTE_MEMZONE_16MB | RTE_MEMZONE_16GB | RTE_MEMZONE_256MB | \\\ndiff --git a/drivers/dma/odm/odm_dmadev.c b/drivers/dma/odm/odm_dmadev.c\nindex b21be83a89..57bd6923f1 100644\n--- a/drivers/dma/odm/odm_dmadev.c\n+++ b/drivers/dma/odm/odm_dmadev.c\n@@ -320,6 +320,251 @@ odm_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge *\n \treturn vq->desc_idx++;\n }\n \n+static int\n+odm_dmadev_fill(void *dev_private, uint16_t vchan, uint64_t pattern, rte_iova_t dst,\n+\t\tuint32_t length, uint64_t flags)\n+{\n+\tuint16_t pending_submit_len, pending_submit_cnt, iring_sz_available, iring_head;\n+\tconst int num_words = ODM_IRING_ENTRY_SIZE_MIN;\n+\tstruct odm_dev *odm = dev_private;\n+\tuint64_t *iring_head_ptr;\n+\tstruct odm_queue *vq;\n+\tuint64_t h;\n+\n+\tvq = &odm->vq[vchan];\n+\n+\tunion odm_instr_hdr_s hdr = {\n+\t\t.s.ct = ODM_HDR_CT_CW_NC,\n+\t\t.s.nfst = 0,\n+\t\t.s.nlst = 1,\n+\t};\n+\n+\th = (uint64_t)length;\n+\n+\tswitch (pattern) {\n+\tcase 0:\n+\t\thdr.s.xtype = ODM_XTYPE_FILL0;\n+\t\tbreak;\n+\tcase 0xffffffffffffffff:\n+\t\thdr.s.xtype = ODM_XTYPE_FILL1;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tconst uint16_t max_iring_words = vq->iring_max_words;\n+\n+\tiring_sz_available = vq->iring_sz_available;\n+\tpending_submit_len = vq->pending_submit_len;\n+\tpending_submit_cnt = vq->pending_submit_cnt;\n+\tiring_head_ptr = vq->iring_mz->addr;\n+\tiring_head = vq->iring_head;\n+\n+\tif (iring_sz_available < num_words)\n+\t\treturn -ENOSPC;\n+\n+\tif ((iring_head + num_words) >= max_iring_words) {\n+\n+\t\tiring_head_ptr[iring_head] = hdr.u;\n+\t\tiring_head = (iring_head + 1) % max_iring_words;\n+\n+\t\tiring_head_ptr[iring_head] = h;\n+\t\tiring_head = (iring_head + 1) % max_iring_words;\n+\n+\t\tiring_head_ptr[iring_head] = dst;\n+\t\tiring_head = (iring_head + 1) % max_iring_words;\n+\n+\t\tiring_head_ptr[iring_head] = 0;\n+\t\tiring_head = (iring_head + 1) % max_iring_words;\n+\t} else {\n+\t\tiring_head_ptr[iring_head] = hdr.u;\n+\t\tiring_head_ptr[iring_head + 1] = h;\n+\t\tiring_head_ptr[iring_head + 2] = dst;\n+\t\tiring_head_ptr[iring_head + 3] = 0;\n+\t\tiring_head += num_words;\n+\t}\n+\n+\tpending_submit_len += num_words;\n+\n+\tif (flags & RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\trte_wmb();\n+\t\todm_write64(pending_submit_len, odm->rbase + ODM_VDMA_DBELL(vchan));\n+\t\tvq->stats.submitted += pending_submit_cnt + 1;\n+\t\tvq->pending_submit_len = 0;\n+\t\tvq->pending_submit_cnt = 0;\n+\t} else {\n+\t\tvq->pending_submit_len = pending_submit_len;\n+\t\tvq->pending_submit_cnt++;\n+\t}\n+\n+\tvq->iring_head = iring_head;\n+\tvq->iring_sz_available = iring_sz_available - num_words;\n+\n+\t/* No extra space to save. Skip entry in extra space ring. */\n+\tvq->ins_ring_head = (vq->ins_ring_head + 1) % vq->cring_max_entry;\n+\n+\tvq->iring_sz_available = iring_sz_available - num_words;\n+\n+\treturn vq->desc_idx++;\n+}\n+\n+static uint16_t\n+odm_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls, uint16_t *last_idx,\n+\t\t bool *has_error)\n+{\n+\tconst union odm_cmpl_ent_s cmpl_zero = {0};\n+\tuint16_t cring_head, iring_sz_available;\n+\tstruct odm_dev *odm = dev_private;\n+\tunion odm_cmpl_ent_s cmpl;\n+\tstruct odm_queue *vq;\n+\tuint64_t nb_err = 0;\n+\tuint32_t *cmpl_ptr;\n+\tint cnt;\n+\n+\tvq = &odm->vq[vchan];\n+\tconst uint32_t *base_addr = vq->cring_mz->addr;\n+\tconst uint16_t cring_max_entry = vq->cring_max_entry;\n+\n+\tcring_head = vq->cring_head;\n+\tiring_sz_available = vq->iring_sz_available;\n+\n+\tif (unlikely(vq->stats.submitted == vq->stats.completed)) {\n+\t\t*last_idx = (vq->stats.completed_offset + vq->stats.completed - 1) & 0xFFFF;\n+\t\treturn 0;\n+\t}\n+\n+\tfor (cnt = 0; cnt < nb_cpls; cnt++) {\n+\t\tcmpl_ptr = RTE_PTR_ADD(base_addr, cring_head * sizeof(cmpl));\n+\t\tcmpl.u = rte_atomic_load_explicit((RTE_ATOMIC(uint32_t) *)cmpl_ptr,\n+\t\t\t\t\t\t rte_memory_order_relaxed);\n+\t\tif (!cmpl.s.valid)\n+\t\t\tbreak;\n+\n+\t\tif (cmpl.s.cmp_code)\n+\t\t\tnb_err++;\n+\n+\t\t/* Free space for enqueue */\n+\t\tiring_sz_available += 4 + vq->extra_ins_sz[cring_head];\n+\n+\t\t/* Clear instruction extra space */\n+\t\tvq->extra_ins_sz[cring_head] = 0;\n+\n+\t\trte_atomic_store_explicit((RTE_ATOMIC(uint32_t) *)cmpl_ptr, cmpl_zero.u,\n+\t\t\t\t\t rte_memory_order_relaxed);\n+\t\tcring_head = (cring_head + 1) % cring_max_entry;\n+\t}\n+\n+\tvq->stats.errors += nb_err;\n+\n+\tif (unlikely(has_error != NULL && nb_err))\n+\t\t*has_error = true;\n+\n+\tvq->cring_head = cring_head;\n+\tvq->iring_sz_available = iring_sz_available;\n+\n+\tvq->stats.completed += cnt;\n+\n+\t*last_idx = (vq->stats.completed_offset + vq->stats.completed - 1) & 0xFFFF;\n+\n+\treturn cnt;\n+}\n+\n+static uint16_t\n+odm_dmadev_completed_status(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,\n+\t\t\t uint16_t *last_idx, enum rte_dma_status_code *status)\n+{\n+\tconst union odm_cmpl_ent_s cmpl_zero = {0};\n+\tuint16_t cring_head, iring_sz_available;\n+\tstruct odm_dev *odm = dev_private;\n+\tunion odm_cmpl_ent_s cmpl;\n+\tstruct odm_queue *vq;\n+\tuint32_t *cmpl_ptr;\n+\tint cnt;\n+\n+\tvq = &odm->vq[vchan];\n+\tconst uint32_t *base_addr = vq->cring_mz->addr;\n+\tconst uint16_t cring_max_entry = vq->cring_max_entry;\n+\n+\tcring_head = vq->cring_head;\n+\tiring_sz_available = vq->iring_sz_available;\n+\n+\tif (vq->stats.submitted == vq->stats.completed) {\n+\t\t*last_idx = (vq->stats.completed_offset + vq->stats.completed - 1) & 0xFFFF;\n+\t\treturn 0;\n+\t}\n+\n+#ifdef ODM_DEBUG\n+\todm_debug(\"cring_head: 0x%\" PRIx16, cring_head);\n+\todm_debug(\"Submitted: 0x%\" PRIx64, vq->stats.submitted);\n+\todm_debug(\"Completed: 0x%\" PRIx64, vq->stats.completed);\n+\todm_debug(\"Hardware count: 0x%\" PRIx64, odm_read64(odm->rbase + ODM_VDMA_CNT(vchan)));\n+#endif\n+\n+\tfor (cnt = 0; cnt < nb_cpls; cnt++) {\n+\t\tcmpl_ptr = RTE_PTR_ADD(base_addr, cring_head * sizeof(cmpl));\n+\t\tcmpl.u = rte_atomic_load_explicit((RTE_ATOMIC(uint32_t) *)cmpl_ptr,\n+\t\t\t\t\t\t rte_memory_order_relaxed);\n+\t\tif (!cmpl.s.valid)\n+\t\t\tbreak;\n+\n+\t\tstatus[cnt] = cmpl.s.cmp_code;\n+\n+\t\tif (cmpl.s.cmp_code)\n+\t\t\tvq->stats.errors++;\n+\n+\t\t/* Free space for enqueue */\n+\t\tiring_sz_available += 4 + vq->extra_ins_sz[cring_head];\n+\n+\t\t/* Clear instruction extra space */\n+\t\tvq->extra_ins_sz[cring_head] = 0;\n+\n+\t\trte_atomic_store_explicit((RTE_ATOMIC(uint32_t) *)cmpl_ptr, cmpl_zero.u,\n+\t\t\t\t\t rte_memory_order_relaxed);\n+\t\tcring_head = (cring_head + 1) % cring_max_entry;\n+\t}\n+\n+\tvq->cring_head = cring_head;\n+\tvq->iring_sz_available = iring_sz_available;\n+\n+\tvq->stats.completed += cnt;\n+\n+\t*last_idx = (vq->stats.completed_offset + vq->stats.completed - 1) & 0xFFFF;\n+\n+\treturn cnt;\n+}\n+\n+static int\n+odm_dmadev_submit(void *dev_private, uint16_t vchan)\n+{\n+\tstruct odm_dev *odm = dev_private;\n+\tuint16_t pending_submit_len;\n+\tstruct odm_queue *vq;\n+\n+\tvq = &odm->vq[vchan];\n+\tpending_submit_len = vq->pending_submit_len;\n+\n+\tif (pending_submit_len == 0)\n+\t\treturn 0;\n+\n+\trte_wmb();\n+\todm_write64(pending_submit_len, odm->rbase + ODM_VDMA_DBELL(vchan));\n+\tvq->pending_submit_len = 0;\n+\tvq->stats.submitted += vq->pending_submit_cnt;\n+\tvq->pending_submit_cnt = 0;\n+\n+\treturn 0;\n+}\n+\n+static uint16_t\n+odm_dmadev_burst_capacity(const void *dev_private, uint16_t vchan __rte_unused)\n+{\n+\tconst struct odm_dev *odm = dev_private;\n+\tconst struct odm_queue *vq;\n+\n+\tvq = &odm->vq[vchan];\n+\treturn (vq->iring_sz_available / ODM_IRING_ENTRY_SIZE_MIN);\n+}\n+\n static int\n odm_stats_get(const struct rte_dma_dev *dev, uint16_t vchan, struct rte_dma_stats *rte_stats,\n \t uint32_t size)\n@@ -419,6 +664,11 @@ odm_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_dev\n \n \tdmadev->fp_obj->copy = odm_dmadev_copy;\n \tdmadev->fp_obj->copy_sg = odm_dmadev_copy_sg;\n+\tdmadev->fp_obj->fill = odm_dmadev_fill;\n+\tdmadev->fp_obj->submit = odm_dmadev_submit;\n+\tdmadev->fp_obj->completed = odm_dmadev_completed;\n+\tdmadev->fp_obj->completed_status = odm_dmadev_completed_status;\n+\tdmadev->fp_obj->burst_capacity = odm_dmadev_burst_capacity;\n \n \todm->pci_dev = pci_dev;\n \n", "prefixes": [ "v3", "7/7" ] }