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GET /api/patches/139443/?format=api
{ "id": 139443, "url": "http://patches.dpdk.org/api/patches/139443/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240417072708.322-7-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240417072708.322-7-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240417072708.322-7-anoobj@marvell.com", "date": "2024-04-17T07:27:07", "name": "[v2,6/7] dma/odm: add copy and copy sg ops", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "4e10cf8dd85e7feef36864cb964fd59c3bd74cc7", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240417072708.322-7-anoobj@marvell.com/mbox/", "series": [ { "id": 31766, "url": "http://patches.dpdk.org/api/series/31766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31766", "date": "2024-04-17T07:27:01", "name": "Add ODM DMA device", "version": 2, "mbox": "http://patches.dpdk.org/series/31766/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139443/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139443/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B84A843E8E;\n\tWed, 17 Apr 2024 09:28:09 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B014740DCB;\n\tWed, 17 Apr 2024 09:27:42 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 29F6C40A81\n for <dev@dpdk.org>; Wed, 17 Apr 2024 09:27:38 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 43GK1t7v016891; Wed, 17 Apr 2024 00:27:37 -0700", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3xhfdn5bup-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Wed, 17 Apr 2024 00:27:37 -0700 (PDT)", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.4; Wed, 17 Apr 2024 00:27:36 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend\n Transport; Wed, 17 Apr 2024 00:27:35 -0700", "from BG-LT92004.corp.innovium.com (unknown [10.193.69.67])\n by maili.marvell.com (Postfix) with ESMTP id 0B7C53F707E;\n Wed, 17 Apr 2024 00:27:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=/JYbzfDCKEv1ytqV/l4sKG+IeuvClHlA6BIkmawnX2s=; b=T2t\n SoZTJhNityKDzWSXTjbZMNGh0Dy81xA5isk841fWdHEC+mxVE7H/5rABsSzMdDqr\n 8h1rdv2jGlqfwgZ0fTmp4LUy65NL7l2l233oTS0q/5xKFBuruEevEeFjGxfGYK/z\n y+jsCEr/k6so0LLJ4IPMVlCli8UFCs7GtQzXFt3lxfuegaldF3oYRChjbJvb22ec\n yD1Sn1tXg3msSs6B9U0mX2HdpKFnLuk1y3kcelhn2ulkQThdLegQdz36+yEReFpe\n LLnoCQeUd5fTCKdJmvCz8dBTtrk3JUjtU/YEdmbVY5SzYgW1j1DiESigEa0CUxqY\n SBtUX74YZYtWfay3Xgw==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Chengwen Feng <fengchengwen@huawei.com>, Kevin Laatz\n <kevin.laatz@intel.com>, Bruce Richardson <bruce.richardson@intel.com>,\n \"Jerin Jacob\" <jerinj@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Vidya Sagar Velumuri <vvelumuri@marvell.com>, Gowrishankar Muthukrishnan\n <gmuthukrishn@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v2 6/7] dma/odm: add copy and copy sg ops", "Date": "Wed, 17 Apr 2024 12:57:07 +0530", "Message-ID": "<20240417072708.322-7-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240417072708.322-1-anoobj@marvell.com>", "References": "<20240415153159.86-1-anoobj@marvell.com>\n <20240417072708.322-1-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "83etGZfAArLQAkvoUngNVzJkDuQSe1au", "X-Proofpoint-ORIG-GUID": "83etGZfAArLQAkvoUngNVzJkDuQSe1au", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-04-17_06,2024-04-16_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n\nAdd ODM copy and copy SG ops.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n---\n drivers/dma/odm/odm_dmadev.c | 236 +++++++++++++++++++++++++++++++++++\n 1 file changed, 236 insertions(+)", "diff": "diff --git a/drivers/dma/odm/odm_dmadev.c b/drivers/dma/odm/odm_dmadev.c\nindex 13b2588246..b21be83a89 100644\n--- a/drivers/dma/odm/odm_dmadev.c\n+++ b/drivers/dma/odm/odm_dmadev.c\n@@ -9,6 +9,7 @@\n #include <rte_common.h>\n #include <rte_dmadev.h>\n #include <rte_dmadev_pmd.h>\n+#include <rte_memcpy.h>\n #include <rte_pci.h>\n \n #include \"odm.h\"\n@@ -87,6 +88,238 @@ odm_dmadev_close(struct rte_dma_dev *dev)\n \treturn 0;\n }\n \n+static int\n+odm_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t dst, uint32_t length,\n+\t\tuint64_t flags)\n+{\n+\tuint16_t pending_submit_len, pending_submit_cnt, iring_sz_available, iring_head;\n+\tconst int num_words = ODM_IRING_ENTRY_SIZE_MIN;\n+\tstruct odm_dev *odm = dev_private;\n+\tuint64_t *iring_head_ptr;\n+\tstruct odm_queue *vq;\n+\tuint64_t h;\n+\n+\tconst union odm_instr_hdr_s hdr = {\n+\t\t.s.ct = ODM_HDR_CT_CW_NC,\n+\t\t.s.xtype = ODM_XTYPE_INTERNAL,\n+\t\t.s.nfst = 1,\n+\t\t.s.nlst = 1,\n+\t};\n+\n+\tvq = &odm->vq[vchan];\n+\n+\th = length;\n+\th |= ((uint64_t)length << 32);\n+\n+\tconst uint16_t max_iring_words = vq->iring_max_words;\n+\n+\tiring_sz_available = vq->iring_sz_available;\n+\tpending_submit_len = vq->pending_submit_len;\n+\tpending_submit_cnt = vq->pending_submit_cnt;\n+\tiring_head_ptr = vq->iring_mz->addr;\n+\tiring_head = vq->iring_head;\n+\n+\tif (iring_sz_available < num_words)\n+\t\treturn -ENOSPC;\n+\n+\tif ((iring_head + num_words) >= max_iring_words) {\n+\n+\t\tiring_head_ptr[iring_head] = hdr.u;\n+\t\tiring_head = (iring_head + 1) % max_iring_words;\n+\n+\t\tiring_head_ptr[iring_head] = h;\n+\t\tiring_head = (iring_head + 1) % max_iring_words;\n+\n+\t\tiring_head_ptr[iring_head] = src;\n+\t\tiring_head = (iring_head + 1) % max_iring_words;\n+\n+\t\tiring_head_ptr[iring_head] = dst;\n+\t\tiring_head = (iring_head + 1) % max_iring_words;\n+\t} else {\n+\t\tiring_head_ptr[iring_head++] = hdr.u;\n+\t\tiring_head_ptr[iring_head++] = h;\n+\t\tiring_head_ptr[iring_head++] = src;\n+\t\tiring_head_ptr[iring_head++] = dst;\n+\t}\n+\n+\tpending_submit_len += num_words;\n+\n+\tif (flags & RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\trte_wmb();\n+\t\todm_write64(pending_submit_len, odm->rbase + ODM_VDMA_DBELL(vchan));\n+\t\tvq->stats.submitted += pending_submit_cnt + 1;\n+\t\tvq->pending_submit_len = 0;\n+\t\tvq->pending_submit_cnt = 0;\n+\t} else {\n+\t\tvq->pending_submit_len = pending_submit_len;\n+\t\tvq->pending_submit_cnt++;\n+\t}\n+\n+\tvq->iring_head = iring_head;\n+\n+\tvq->iring_sz_available = iring_sz_available - num_words;\n+\n+\t/* No extra space to save. Skip entry in extra space ring. */\n+\tvq->ins_ring_head = (vq->ins_ring_head + 1) % vq->cring_max_entry;\n+\n+\treturn vq->desc_idx++;\n+}\n+\n+static inline void\n+odm_dmadev_fill_sg(uint64_t *cmd, const struct rte_dma_sge *src, const struct rte_dma_sge *dst,\n+\t\t uint16_t nb_src, uint16_t nb_dst, union odm_instr_hdr_s *hdr)\n+{\n+\tint i = 0, j = 0;\n+\tuint64_t h = 0;\n+\n+\tcmd[j++] = hdr->u;\n+\t/* When nb_src is even */\n+\tif (!(nb_src & 0x1)) {\n+\t\t/* Fill the iring with src pointers */\n+\t\tfor (i = 1; i < nb_src; i += 2) {\n+\t\t\th = ((uint64_t)src[i].length << 32) | src[i - 1].length;\n+\t\t\tcmd[j++] = h;\n+\t\t\tcmd[j++] = src[i - 1].addr;\n+\t\t\tcmd[j++] = src[i].addr;\n+\t\t}\n+\n+\t\t/* Fill the iring with dst pointers */\n+\t\tfor (i = 1; i < nb_dst; i += 2) {\n+\t\t\th = ((uint64_t)dst[i].length << 32) | dst[i - 1].length;\n+\t\t\tcmd[j++] = h;\n+\t\t\tcmd[j++] = dst[i - 1].addr;\n+\t\t\tcmd[j++] = dst[i].addr;\n+\t\t}\n+\n+\t\t/* Handle the last dst pointer when nb_dst is odd */\n+\t\tif (nb_dst & 0x1) {\n+\t\t\th = dst[nb_dst - 1].length;\n+\t\t\tcmd[j++] = h;\n+\t\t\tcmd[j++] = dst[nb_dst - 1].addr;\n+\t\t\tcmd[j++] = 0;\n+\t\t}\n+\t} else {\n+\t\t/* When nb_src is odd */\n+\n+\t\t/* Fill the iring with src pointers */\n+\t\tfor (i = 1; i < nb_src; i += 2) {\n+\t\t\th = ((uint64_t)src[i].length << 32) | src[i - 1].length;\n+\t\t\tcmd[j++] = h;\n+\t\t\tcmd[j++] = src[i - 1].addr;\n+\t\t\tcmd[j++] = src[i].addr;\n+\t\t}\n+\n+\t\t/* Handle the last src pointer */\n+\t\th = ((uint64_t)dst[0].length << 32) | src[nb_src - 1].length;\n+\t\tcmd[j++] = h;\n+\t\tcmd[j++] = src[nb_src - 1].addr;\n+\t\tcmd[j++] = dst[0].addr;\n+\n+\t\t/* Fill the iring with dst pointers */\n+\t\tfor (i = 2; i < nb_dst; i += 2) {\n+\t\t\th = ((uint64_t)dst[i].length << 32) | dst[i - 1].length;\n+\t\t\tcmd[j++] = h;\n+\t\t\tcmd[j++] = dst[i - 1].addr;\n+\t\t\tcmd[j++] = dst[i].addr;\n+\t\t}\n+\n+\t\t/* Handle the last dst pointer when nb_dst is even */\n+\t\tif (!(nb_dst & 0x1)) {\n+\t\t\th = dst[nb_dst - 1].length;\n+\t\t\tcmd[j++] = h;\n+\t\t\tcmd[j++] = dst[nb_dst - 1].addr;\n+\t\t\tcmd[j++] = 0;\n+\t\t}\n+\t}\n+}\n+\n+static int\n+odm_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge *src,\n+\t\t const struct rte_dma_sge *dst, uint16_t nb_src, uint16_t nb_dst, uint64_t flags)\n+{\n+\tuint16_t pending_submit_len, pending_submit_cnt, iring_head, ins_ring_head;\n+\tuint16_t iring_sz_available, i, nb, num_words;\n+\tuint64_t cmd[ODM_IRING_ENTRY_SIZE_MAX];\n+\tstruct odm_dev *odm = dev_private;\n+\tuint32_t s_sz = 0, d_sz = 0;\n+\tuint64_t *iring_head_ptr;\n+\tstruct odm_queue *vq;\n+\tunion odm_instr_hdr_s hdr = {\n+\t\t.s.ct = ODM_HDR_CT_CW_NC,\n+\t\t.s.xtype = ODM_XTYPE_INTERNAL,\n+\t};\n+\n+\tvq = &odm->vq[vchan];\n+\tconst uint16_t max_iring_words = vq->iring_max_words;\n+\n+\tiring_head_ptr = vq->iring_mz->addr;\n+\tiring_head = vq->iring_head;\n+\tiring_sz_available = vq->iring_sz_available;\n+\tins_ring_head = vq->ins_ring_head;\n+\tpending_submit_len = vq->pending_submit_len;\n+\tpending_submit_cnt = vq->pending_submit_cnt;\n+\n+\tif (unlikely(nb_src > 4 || nb_dst > 4))\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i < nb_src; i++)\n+\t\ts_sz += src[i].length;\n+\n+\tfor (i = 0; i < nb_dst; i++)\n+\t\td_sz += dst[i].length;\n+\n+\tif (s_sz != d_sz)\n+\t\treturn -EINVAL;\n+\n+\tnb = nb_src + nb_dst;\n+\thdr.s.nfst = nb_src;\n+\thdr.s.nlst = nb_dst;\n+\tnum_words = 1 + 3 * (nb / 2 + (nb & 0x1));\n+\n+\tif (iring_sz_available < num_words)\n+\t\treturn -ENOSPC;\n+\n+\tif ((iring_head + num_words) >= max_iring_words) {\n+\t\tuint16_t words_avail = max_iring_words - iring_head;\n+\t\tuint16_t words_pend = num_words - words_avail;\n+\n+\t\tif (unlikely(words_avail + words_pend > ODM_IRING_ENTRY_SIZE_MAX))\n+\t\t\treturn -ENOSPC;\n+\n+\t\todm_dmadev_fill_sg(cmd, src, dst, nb_src, nb_dst, &hdr);\n+\t\trte_memcpy((void *)&iring_head_ptr[iring_head], (void *)cmd, words_avail * 8);\n+\t\trte_memcpy((void *)iring_head_ptr, (void *)&cmd[words_avail], words_pend * 8);\n+\t\tiring_head = words_pend;\n+\t} else {\n+\t\todm_dmadev_fill_sg(&iring_head_ptr[iring_head], src, dst, nb_src, nb_dst, &hdr);\n+\t\tiring_head += num_words;\n+\t}\n+\n+\tpending_submit_len += num_words;\n+\n+\tif (flags & RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\trte_wmb();\n+\t\todm_write64(pending_submit_len, odm->rbase + ODM_VDMA_DBELL(vchan));\n+\t\tvq->stats.submitted += pending_submit_cnt + 1;\n+\t\tvq->pending_submit_len = 0;\n+\t\tvq->pending_submit_cnt = 0;\n+\t} else {\n+\t\tvq->pending_submit_len = pending_submit_len;\n+\t\tvq->pending_submit_cnt++;\n+\t}\n+\n+\tvq->iring_head = iring_head;\n+\n+\tvq->iring_sz_available = iring_sz_available - num_words;\n+\n+\t/* Save extra space used for the instruction. */\n+\tvq->extra_ins_sz[ins_ring_head] = num_words - 4;\n+\n+\tvq->ins_ring_head = (ins_ring_head + 1) % vq->cring_max_entry;\n+\n+\treturn vq->desc_idx++;\n+}\n+\n static int\n odm_stats_get(const struct rte_dma_dev *dev, uint16_t vchan, struct rte_dma_stats *rte_stats,\n \t uint32_t size)\n@@ -184,6 +417,9 @@ odm_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_dev\n \tdmadev->fp_obj->dev_private = odm;\n \tdmadev->dev_ops = &odm_dmadev_ops;\n \n+\tdmadev->fp_obj->copy = odm_dmadev_copy;\n+\tdmadev->fp_obj->copy_sg = odm_dmadev_copy_sg;\n+\n \todm->pci_dev = pci_dev;\n \n \trc = odm_dev_init(odm);\n", "prefixes": [ "v2", "6/7" ] }