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GET /api/patches/139442/?format=api
{ "id": 139442, "url": "http://patches.dpdk.org/api/patches/139442/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240417072708.322-5-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240417072708.322-5-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240417072708.322-5-anoobj@marvell.com", "date": "2024-04-17T07:27:05", "name": "[v2,4/7] dma/odm: add device ops", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "7f50069849dc97a79b1cd999e9b847ede2477017", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240417072708.322-5-anoobj@marvell.com/mbox/", "series": [ { "id": 31766, "url": "http://patches.dpdk.org/api/series/31766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31766", "date": "2024-04-17T07:27:01", "name": "Add ODM DMA device", "version": 2, "mbox": "http://patches.dpdk.org/series/31766/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139442/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139442/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1F7C743E8E;\n\tWed, 17 Apr 2024 09:28:03 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4952740DDB;\n\tWed, 17 Apr 2024 09:27:41 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id C480A40A79\n for <dev@dpdk.org>; Wed, 17 Apr 2024 09:27:35 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 43GK1xuk017063; Wed, 17 Apr 2024 00:27:35 -0700", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3xhfdn5btq-13\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Wed, 17 Apr 2024 00:27:34 -0700 (PDT)", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.4; Wed, 17 Apr 2024 00:27:28 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend\n Transport; Wed, 17 Apr 2024 00:27:28 -0700", "from BG-LT92004.corp.innovium.com (unknown [10.193.69.67])\n by maili.marvell.com (Postfix) with ESMTP id 3B5AE3F707E;\n Wed, 17 Apr 2024 00:27:23 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=7RnWzbs+Laq/Ex0hOXJgPWVdWT95NEevwe+xgdgPVxM=; b=P1G\n c6rk7PbhN3PUA8GN7ycTqycRdkuhZLwpPjWRyGljYy8CZyAUtUdknViAWV1fSZ2t\n 8F/L6zNmrJBomIlKQZ5KamvXXs3FYGMCMeV80VnSpyT1u5sfmZneQ354B1X5UPC6\n XQLZcZX08VdLNsMIqZXckZGE5UEZxJAlhmxtECS1u+/1QqNsiPEIUeKgLDfo/A6S\n GhhYIAZaGDpjpkOSmcIBeLAUQ5yO2MgRWInFQNHArVo4uolGJsQHLh7x2Nea6EWf\n 3RYXwr1M0dqn2Bql2nC3b4+Nmz23oKHnsPS0zv4UCnXZQ/agwR8ocPNz0lsuDJdy\n ZGspBpw7qQu91aQUxSA==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Chengwen Feng <fengchengwen@huawei.com>, Kevin Laatz\n <kevin.laatz@intel.com>, Bruce Richardson <bruce.richardson@intel.com>,\n \"Jerin Jacob\" <jerinj@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>, \"Vidya Sagar\n Velumuri\" <vvelumuri@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v2 4/7] dma/odm: add device ops", "Date": "Wed, 17 Apr 2024 12:57:05 +0530", "Message-ID": "<20240417072708.322-5-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240417072708.322-1-anoobj@marvell.com>", "References": "<20240415153159.86-1-anoobj@marvell.com>\n <20240417072708.322-1-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Y7cvi3Oefe-0ZexxjSAnQUad12SZ4eKr", "X-Proofpoint-ORIG-GUID": "Y7cvi3Oefe-0ZexxjSAnQUad12SZ4eKr", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-04-17_06,2024-04-16_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\n\nAdd DMA device control ops.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n---\n drivers/dma/odm/odm.c | 144 ++++++++++++++++++++++++++++++++++-\n drivers/dma/odm/odm.h | 58 ++++++++++++++\n drivers/dma/odm/odm_dmadev.c | 85 +++++++++++++++++++++\n 3 files changed, 285 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/dma/odm/odm.c b/drivers/dma/odm/odm.c\nindex c0963da451..6094ace9fd 100644\n--- a/drivers/dma/odm/odm.c\n+++ b/drivers/dma/odm/odm.c\n@@ -7,6 +7,7 @@\n #include <bus_pci_driver.h>\n \n #include <rte_io.h>\n+#include <rte_malloc.h>\n \n #include \"odm.h\"\n #include \"odm_priv.h\"\n@@ -14,8 +15,15 @@\n static void\n odm_vchan_resc_free(struct odm_dev *odm, int qno)\n {\n-\tRTE_SET_USED(odm);\n-\tRTE_SET_USED(qno);\n+\tstruct odm_queue *vq = &odm->vq[qno];\n+\n+\trte_memzone_free(vq->iring_mz);\n+\trte_memzone_free(vq->cring_mz);\n+\trte_free(vq->extra_ins_sz);\n+\n+\tvq->iring_mz = NULL;\n+\tvq->cring_mz = NULL;\n+\tvq->extra_ins_sz = NULL;\n }\n \n static int\n@@ -53,6 +61,138 @@ send_mbox_to_pf(struct odm_dev *odm, union odm_mbox_msg *msg, union odm_mbox_msg\n \treturn 0;\n }\n \n+static int\n+odm_queue_ring_config(struct odm_dev *odm, int vchan, int isize, int csize)\n+{\n+\tunion odm_vdma_ring_cfg_s ring_cfg = {0};\n+\tstruct odm_queue *vq = &odm->vq[vchan];\n+\n+\tif (vq->iring_mz == NULL || vq->cring_mz == NULL)\n+\t\treturn -EINVAL;\n+\n+\tring_cfg.s.isize = (isize / 1024) - 1;\n+\tring_cfg.s.csize = (csize / 1024) - 1;\n+\n+\todm_write64(ring_cfg.u, odm->rbase + ODM_VDMA_RING_CFG(vchan));\n+\todm_write64(vq->iring_mz->iova, odm->rbase + ODM_VDMA_IRING_BADDR(vchan));\n+\todm_write64(vq->cring_mz->iova, odm->rbase + ODM_VDMA_CRING_BADDR(vchan));\n+\n+\treturn 0;\n+}\n+\n+int\n+odm_enable(struct odm_dev *odm)\n+{\n+\tstruct odm_queue *vq;\n+\tint qno, rc = 0;\n+\n+\tfor (qno = 0; qno < odm->num_qs; qno++) {\n+\t\tvq = &odm->vq[qno];\n+\n+\t\tvq->desc_idx = vq->stats.completed_offset;\n+\t\tvq->pending_submit_len = 0;\n+\t\tvq->pending_submit_cnt = 0;\n+\t\tvq->iring_head = 0;\n+\t\tvq->cring_head = 0;\n+\t\tvq->ins_ring_head = 0;\n+\t\tvq->iring_sz_available = vq->iring_max_words;\n+\n+\t\trc = odm_queue_ring_config(odm, qno, vq->iring_max_words * 8,\n+\t\t\t\t\t vq->cring_max_entry * 4);\n+\t\tif (rc < 0)\n+\t\t\tbreak;\n+\n+\t\todm_write64(0x1, odm->rbase + ODM_VDMA_EN(qno));\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+odm_disable(struct odm_dev *odm)\n+{\n+\tint qno, wait_cnt = ODM_IRING_IDLE_WAIT_CNT;\n+\tuint64_t val;\n+\n+\t/* Disable the queue and wait for the queue to became idle */\n+\tfor (qno = 0; qno < odm->num_qs; qno++) {\n+\t\todm_write64(0x0, odm->rbase + ODM_VDMA_EN(qno));\n+\t\tdo {\n+\t\t\tval = odm_read64(odm->rbase + ODM_VDMA_IRING_BADDR(qno));\n+\t\t} while ((!(val & 1ULL << 63)) && (--wait_cnt > 0));\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+odm_vchan_setup(struct odm_dev *odm, int vchan, int nb_desc)\n+{\n+\tstruct odm_queue *vq = &odm->vq[vchan];\n+\tint isize, csize, max_nb_desc, rc = 0;\n+\tunion odm_mbox_msg mbox_msg;\n+\tconst struct rte_memzone *mz;\n+\tchar name[32];\n+\n+\tif (vq->iring_mz != NULL)\n+\t\todm_vchan_resc_free(odm, vchan);\n+\n+\tmbox_msg.u[0] = 0;\n+\tmbox_msg.u[1] = 0;\n+\n+\t/* ODM PF driver expects vfid starts from index 0 */\n+\tmbox_msg.q.vfid = odm->vfid;\n+\tmbox_msg.q.cmd = ODM_QUEUE_OPEN;\n+\tmbox_msg.q.qidx = vchan;\n+\trc = send_mbox_to_pf(odm, &mbox_msg, &mbox_msg);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\t/* Determine instruction & completion ring sizes. */\n+\n+\t/* Create iring that can support nb_desc. Round up to a multiple of 1024. */\n+\tisize = RTE_ALIGN_CEIL(nb_desc * ODM_IRING_ENTRY_SIZE_MAX * 8, 1024);\n+\tisize = RTE_MIN(isize, ODM_IRING_MAX_SIZE);\n+\tsnprintf(name, sizeof(name), \"vq%d_iring%d\", odm->vfid, vchan);\n+\tmz = rte_memzone_reserve_aligned(name, isize, 0, ODM_MEMZONE_FLAGS, 1024);\n+\tif (mz == NULL)\n+\t\treturn -ENOMEM;\n+\tvq->iring_mz = mz;\n+\tvq->iring_max_words = isize / 8;\n+\n+\t/* Create cring that can support max instructions that can be inflight in hw. */\n+\tmax_nb_desc = (isize / (ODM_IRING_ENTRY_SIZE_MIN * 8));\n+\tcsize = RTE_ALIGN_CEIL(max_nb_desc * sizeof(union odm_cmpl_ent_s), 1024);\n+\tsnprintf(name, sizeof(name), \"vq%d_cring%d\", odm->vfid, vchan);\n+\tmz = rte_memzone_reserve_aligned(name, csize, 0, ODM_MEMZONE_FLAGS, 1024);\n+\tif (mz == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto iring_free;\n+\t}\n+\tvq->cring_mz = mz;\n+\tvq->cring_max_entry = csize / 4;\n+\n+\t/* Allocate memory to track the size of each instruction. */\n+\tsnprintf(name, sizeof(name), \"vq%d_extra%d\", odm->vfid, vchan);\n+\tvq->extra_ins_sz = rte_zmalloc(name, vq->cring_max_entry, 0);\n+\tif (vq->extra_ins_sz == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto cring_free;\n+\t}\n+\n+\tvq->stats = (struct vq_stats){0};\n+\treturn rc;\n+\n+cring_free:\n+\trte_memzone_free(odm->vq[vchan].cring_mz);\n+\tvq->cring_mz = NULL;\n+iring_free:\n+\trte_memzone_free(odm->vq[vchan].iring_mz);\n+\tvq->iring_mz = NULL;\n+\n+\treturn rc;\n+}\n+\n int\n odm_dev_init(struct odm_dev *odm)\n {\ndiff --git a/drivers/dma/odm/odm.h b/drivers/dma/odm/odm.h\nindex 9fd3e30ad8..e1373e0c7f 100644\n--- a/drivers/dma/odm/odm.h\n+++ b/drivers/dma/odm/odm.h\n@@ -9,7 +9,9 @@\n \n #include <rte_common.h>\n #include <rte_compat.h>\n+#include <rte_io.h>\n #include <rte_log.h>\n+#include <rte_memzone.h>\n \n extern int odm_logtype;\n \n@@ -54,6 +56,14 @@ extern int odm_logtype;\n \n #define ODM_MAX_QUEUES_PER_DEV 16\n \n+#define ODM_IRING_MAX_SIZE\t (256 * 1024)\n+#define ODM_IRING_ENTRY_SIZE_MIN 4\n+#define ODM_IRING_ENTRY_SIZE_MAX 13\n+#define ODM_IRING_MAX_WORDS\t (ODM_IRING_MAX_SIZE / 8)\n+#define ODM_IRING_MAX_ENTRY\t (ODM_IRING_MAX_WORDS / ODM_IRING_ENTRY_SIZE_MIN)\n+\n+#define ODM_MAX_POINTER 4\n+\n #define odm_read64(addr) rte_read64_relaxed((volatile void *)(addr))\n #define odm_write64(val, addr) rte_write64_relaxed((val), (volatile void *)(addr))\n \n@@ -66,6 +76,10 @@ extern int odm_logtype;\n \t\tRTE_FMT(\"%s(): %u\" RTE_FMT_HEAD(__VA_ARGS__, ), __func__, __LINE__, \\\n \t\t\tRTE_FMT_TAIL(__VA_ARGS__, )))\n \n+#define ODM_MEMZONE_FLAGS \\\n+\t(RTE_MEMZONE_1GB | RTE_MEMZONE_16MB | RTE_MEMZONE_16GB | RTE_MEMZONE_256MB | \\\n+\t RTE_MEMZONE_512MB | RTE_MEMZONE_4GB | RTE_MEMZONE_SIZE_HINT_ONLY)\n+\n /**\n * Structure odm_instr_hdr_s for ODM\n *\n@@ -141,8 +155,48 @@ union odm_vdma_counts_s {\n \t} s;\n };\n \n+struct vq_stats {\n+\tuint64_t submitted;\n+\tuint64_t completed;\n+\tuint64_t errors;\n+\t/*\n+\t * Since stats.completed is used to return completion index, account for any packets\n+\t * received before stats is reset.\n+\t */\n+\tuint64_t completed_offset;\n+};\n+\n+struct odm_queue {\n+\tstruct odm_dev *dev;\n+\t/* Instructions that are prepared on the iring, but is not pushed to hw yet. */\n+\tuint16_t pending_submit_cnt;\n+\t/* Length (in words) of instructions that are not yet pushed to hw. */\n+\tuint16_t pending_submit_len;\n+\tuint16_t desc_idx;\n+\t/* Instruction ring head. Used for enqueue. */\n+\tuint16_t iring_head;\n+\t/* Completion ring head. Used for dequeue. */\n+\tuint16_t cring_head;\n+\t/* Extra instruction size ring head. Used in enqueue-dequeue.*/\n+\tuint16_t ins_ring_head;\n+\t/* Extra instruction size ring tail. Used in enqueue-dequeue.*/\n+\tuint16_t ins_ring_tail;\n+\t/* Instruction size available.*/\n+\tuint16_t iring_sz_available;\n+\t/* Number of 8-byte words in iring.*/\n+\tuint16_t iring_max_words;\n+\t/* Number of words in cring.*/\n+\tuint16_t cring_max_entry;\n+\t/* Extra instruction size used per inflight instruction.*/\n+\tuint8_t *extra_ins_sz;\n+\tstruct vq_stats stats;\n+\tconst struct rte_memzone *iring_mz;\n+\tconst struct rte_memzone *cring_mz;\n+};\n+\n struct __rte_cache_aligned odm_dev {\n \tstruct rte_pci_device *pci_dev;\n+\tstruct odm_queue vq[ODM_MAX_QUEUES_PER_DEV];\n \tuint8_t *rbase;\n \tuint16_t vfid;\n \tuint8_t max_qs;\n@@ -151,5 +205,9 @@ struct __rte_cache_aligned odm_dev {\n \n int odm_dev_init(struct odm_dev *odm);\n int odm_dev_fini(struct odm_dev *odm);\n+int odm_configure(struct odm_dev *odm);\n+int odm_enable(struct odm_dev *odm);\n+int odm_disable(struct odm_dev *odm);\n+int odm_vchan_setup(struct odm_dev *odm, int vchan, int nb_desc);\n \n #endif /* _ODM_H_ */\ndiff --git a/drivers/dma/odm/odm_dmadev.c b/drivers/dma/odm/odm_dmadev.c\nindex bef335c10c..8c705978fe 100644\n--- a/drivers/dma/odm/odm_dmadev.c\n+++ b/drivers/dma/odm/odm_dmadev.c\n@@ -17,6 +17,87 @@\n #define PCI_DEVID_ODYSSEY_ODM_VF 0xA08C\n #define PCI_DRIVER_NAME\t\t dma_odm\n \n+static int\n+odm_dmadev_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_info, uint32_t size)\n+{\n+\tstruct odm_dev *odm = NULL;\n+\n+\tRTE_SET_USED(size);\n+\n+\todm = dev->fp_obj->dev_private;\n+\n+\tdev_info->max_vchans = odm->max_qs;\n+\tdev_info->nb_vchans = odm->num_qs;\n+\tdev_info->dev_capa =\n+\t\t(RTE_DMA_CAPA_MEM_TO_MEM | RTE_DMA_CAPA_OPS_COPY | RTE_DMA_CAPA_OPS_COPY_SG);\n+\tdev_info->max_desc = ODM_IRING_MAX_ENTRY;\n+\tdev_info->min_desc = 1;\n+\tdev_info->max_sges = ODM_MAX_POINTER;\n+\n+\treturn 0;\n+}\n+\n+static int\n+odm_dmadev_configure(struct rte_dma_dev *dev, const struct rte_dma_conf *conf, uint32_t conf_sz)\n+{\n+\tstruct odm_dev *odm = NULL;\n+\n+\tRTE_SET_USED(conf_sz);\n+\n+\todm = dev->fp_obj->dev_private;\n+\todm->num_qs = conf->nb_vchans;\n+\n+\treturn 0;\n+}\n+\n+static int\n+odm_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,\n+\t\t const struct rte_dma_vchan_conf *conf, uint32_t conf_sz)\n+{\n+\tstruct odm_dev *odm = dev->fp_obj->dev_private;\n+\n+\tRTE_SET_USED(conf_sz);\n+\treturn odm_vchan_setup(odm, vchan, conf->nb_desc);\n+}\n+\n+static int\n+odm_dmadev_start(struct rte_dma_dev *dev)\n+{\n+\tstruct odm_dev *odm = dev->fp_obj->dev_private;\n+\n+\treturn odm_enable(odm);\n+}\n+\n+static int\n+odm_dmadev_stop(struct rte_dma_dev *dev)\n+{\n+\tstruct odm_dev *odm = dev->fp_obj->dev_private;\n+\n+\treturn odm_disable(odm);\n+}\n+\n+static int\n+odm_dmadev_close(struct rte_dma_dev *dev)\n+{\n+\tstruct odm_dev *odm = dev->fp_obj->dev_private;\n+\n+\todm_disable(odm);\n+\todm_dev_fini(odm);\n+\n+\treturn 0;\n+}\n+\n+static const struct rte_dma_dev_ops odm_dmadev_ops = {\n+\t.dev_close = odm_dmadev_close,\n+\t.dev_configure = odm_dmadev_configure,\n+\t.dev_info_get = odm_dmadev_info_get,\n+\t.dev_start = odm_dmadev_start,\n+\t.dev_stop = odm_dmadev_stop,\n+\t.stats_get = NULL,\n+\t.stats_reset = NULL,\n+\t.vchan_setup = odm_dmadev_vchan_setup,\n+};\n+\n static int\n odm_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev)\n {\n@@ -40,6 +121,10 @@ odm_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_dev\n \todm_info(\"DMA device %s probed\", name);\n \todm = dmadev->data->dev_private;\n \n+\tdmadev->device = &pci_dev->device;\n+\tdmadev->fp_obj->dev_private = odm;\n+\tdmadev->dev_ops = &odm_dmadev_ops;\n+\n \todm->pci_dev = pci_dev;\n \n \trc = odm_dev_init(odm);\n", "prefixes": [ "v2", "4/7" ] }