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GET /api/patches/139434/?format=api
{ "id": 139434, "url": "http://patches.dpdk.org/api/patches/139434/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240417055830.1935-2-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240417055830.1935-2-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240417055830.1935-2-pbhagavatula@marvell.com", "date": "2024-04-17T05:58:30", "name": "[v2,2/2] dma/cnxk: remove completion pool", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "7ecd6687078506ea32adcd324c3097fff2b4ea77", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240417055830.1935-2-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 31763, "url": "http://patches.dpdk.org/api/series/31763/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31763", "date": "2024-04-17T05:58:29", "name": "[v2,1/2] eventdev/dma: reorganize event DMA ops", "version": 2, "mbox": "http://patches.dpdk.org/series/31763/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139434/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/139434/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9633443E8C;\n\tWed, 17 Apr 2024 07:58:48 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E62D0402E3;\n\tWed, 17 Apr 2024 07:58:41 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A4E7F402DC\n for <dev@dpdk.org>; Wed, 17 Apr 2024 07:58:40 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 43GJQeu9016661 for <dev@dpdk.org>; Tue, 16 Apr 2024 22:58:39 -0700", "from dc6wp-exch02.marvell.com ([4.21.29.225])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3xhwera6eb-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 16 Apr 2024 22:58:39 -0700 (PDT)", "from DC6WP-EXCH02.marvell.com (10.76.176.209) by\n DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.4; Tue, 16 Apr 2024 22:58:38 -0700", "from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com\n (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend\n Transport; Tue, 16 Apr 2024 22:58:38 -0700", "from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com\n [10.28.164.106])\n by maili.marvell.com (Postfix) with ESMTP id EDF7E3F707E;\n Tue, 16 Apr 2024 22:58:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=vKtSD5pt5TbnwXmaXWWnU4hkJNgNrMhEAANvcw9XgPc=; b=Clb\n IT9ysOWXAFd9UFUf26JN4ewJsmtwZG4O3tXJNxW16Z/f6a58PhWPmPiVxCAHw/IV\n ADqFFS+cxrLUhEGk2le285jZ0pxZhc+YXcmYorzsK+fjtzcP7nAmaLzXFXlz2ZAx\n lsyVzXnCq4dZBb49MSW0TkC5Sx+o4SZb7epakCcKM0bep0ecSnuPKmje+Eo5d9xI\n bYAWMfw2j5N0DDtGPIZIlf2bHfDV6455k2Rmlm8Io+Miovs7+ZbvudFFd8tU5+2C\n tLg6/cHOYiOSV4XGISM9ENRpDLTEWxs7oanhOKjRKzJZwMMQCFV8Lo1SoUwjrmz7\n UWhyrns49//1YouaPmA==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>, \"Pavan\n Nikhilesh\" <pbhagavatula@marvell.com>,\n Shijith Thotton <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 2/2] dma/cnxk: remove completion pool", "Date": "Wed, 17 Apr 2024 11:28:30 +0530", "Message-ID": "<20240417055830.1935-2-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240417055830.1935-1-pbhagavatula@marvell.com>", "References": "<20240406101311.11044-1-pbhagavatula@marvell.com>\n <20240417055830.1935-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "zKdIG-pizI5Jh2eYCb0IW3XH5jxYQDZO", "X-Proofpoint-ORIG-GUID": "zKdIG-pizI5Jh2eYCb0IW3XH5jxYQDZO", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-04-17_05,2024-04-16_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nUse DMA ops to store metadata, remove use of completion pool.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nAcked-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/dma/cnxk/cnxk_dmadev.c | 53 ++++++----------\n drivers/dma/cnxk/cnxk_dmadev.h | 24 +------\n drivers/dma/cnxk/cnxk_dmadev_fp.c | 79 +++++-------------------\n drivers/event/cnxk/cnxk_eventdev_adptr.c | 47 +++-----------\n 4 files changed, 45 insertions(+), 158 deletions(-)", "diff": "diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c\nindex 4ab3cfbdf2..dfd7222713 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev.c\n+++ b/drivers/dma/cnxk/cnxk_dmadev.c\n@@ -2,6 +2,8 @@\n * Copyright (C) 2021 Marvell International Ltd.\n */\n \n+#include <rte_event_dma_adapter.h>\n+\n #include <cnxk_dmadev.h>\n \n static int cnxk_stats_reset(struct rte_dma_dev *dev, uint16_t vchan);\n@@ -30,8 +32,7 @@ cnxk_dmadev_vchan_free(struct cnxk_dpi_vf_s *dpivf, uint16_t vchan)\n {\n \tstruct cnxk_dpi_conf *dpi_conf;\n \tuint16_t num_vchans;\n-\tuint16_t max_desc;\n-\tint i, j;\n+\tint i;\n \n \tif (vchan == RTE_DMA_ALL_VCHAN) {\n \t\tnum_vchans = dpivf->num_vchans;\n@@ -46,12 +47,6 @@ cnxk_dmadev_vchan_free(struct cnxk_dpi_vf_s *dpivf, uint16_t vchan)\n \n \tfor (; i < num_vchans; i++) {\n \t\tdpi_conf = &dpivf->conf[i];\n-\t\tmax_desc = dpi_conf->c_desc.max_cnt + 1;\n-\t\tif (dpi_conf->c_desc.compl_ptr) {\n-\t\t\tfor (j = 0; j < max_desc; j++)\n-\t\t\t\trte_free(dpi_conf->c_desc.compl_ptr[j]);\n-\t\t}\n-\n \t\trte_free(dpi_conf->c_desc.compl_ptr);\n \t\tdpi_conf->c_desc.compl_ptr = NULL;\n \t}\n@@ -261,7 +256,7 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,\n \tif (max_desc > CNXK_DPI_MAX_DESC)\n \t\tmax_desc = CNXK_DPI_MAX_DESC;\n \n-\tsize = (max_desc * sizeof(struct cnxk_dpi_compl_s *));\n+\tsize = (max_desc * sizeof(uint8_t) * CNXK_DPI_COMPL_OFFSET);\n \tdpi_conf->c_desc.compl_ptr = rte_zmalloc(NULL, size, 0);\n \n \tif (dpi_conf->c_desc.compl_ptr == NULL) {\n@@ -269,16 +264,8 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,\n \t\treturn -ENOMEM;\n \t}\n \n-\tfor (i = 0; i < max_desc; i++) {\n-\t\tdpi_conf->c_desc.compl_ptr[i] =\n-\t\t\trte_zmalloc(NULL, sizeof(struct cnxk_dpi_compl_s), 0);\n-\t\tif (!dpi_conf->c_desc.compl_ptr[i]) {\n-\t\t\tplt_err(\"Failed to allocate for descriptor memory\");\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\n-\t\tdpi_conf->c_desc.compl_ptr[i]->cdata = CNXK_DPI_REQ_CDATA;\n-\t}\n+\tfor (i = 0; i < max_desc; i++)\n+\t\tdpi_conf->c_desc.compl_ptr[i * CNXK_DPI_COMPL_OFFSET] = CNXK_DPI_REQ_CDATA;\n \n \tdpi_conf->c_desc.max_cnt = (max_desc - 1);\n \n@@ -301,10 +288,8 @@ cnxk_dmadev_start(struct rte_dma_dev *dev)\n \t\tdpi_conf->pnum_words = 0;\n \t\tdpi_conf->pending = 0;\n \t\tdpi_conf->desc_idx = 0;\n-\t\tfor (j = 0; j < dpi_conf->c_desc.max_cnt + 1; j++) {\n-\t\t\tif (dpi_conf->c_desc.compl_ptr[j])\n-\t\t\t\tdpi_conf->c_desc.compl_ptr[j]->cdata = CNXK_DPI_REQ_CDATA;\n-\t\t}\n+\t\tfor (j = 0; j < dpi_conf->c_desc.max_cnt + 1; j++)\n+\t\t\tdpi_conf->c_desc.compl_ptr[j * CNXK_DPI_COMPL_OFFSET] = CNXK_DPI_REQ_CDATA;\n \t\tnb_desc += dpi_conf->c_desc.max_cnt + 1;\n \t\tcnxk_stats_reset(dev, i);\n \t\tdpi_conf->completed_offset = 0;\n@@ -382,22 +367,22 @@ cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,\n \tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n \tstruct cnxk_dpi_conf *dpi_conf = &dpivf->conf[vchan];\n \tstruct cnxk_dpi_cdesc_data_s *c_desc = &dpi_conf->c_desc;\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tuint8_t status;\n \tint cnt;\n \n \tfor (cnt = 0; cnt < nb_cpls; cnt++) {\n-\t\tcomp_ptr = c_desc->compl_ptr[c_desc->head];\n-\n-\t\tif (comp_ptr->cdata) {\n-\t\t\tif (comp_ptr->cdata == CNXK_DPI_REQ_CDATA)\n+\t\tstatus = c_desc->compl_ptr[c_desc->head * CNXK_DPI_COMPL_OFFSET];\n+\t\tif (status) {\n+\t\t\tif (status == CNXK_DPI_REQ_CDATA)\n \t\t\t\tbreak;\n \t\t\t*has_error = 1;\n \t\t\tdpi_conf->stats.errors++;\n+\t\t\tc_desc->compl_ptr[c_desc->head * CNXK_DPI_COMPL_OFFSET] =\n+\t\t\t\tCNXK_DPI_REQ_CDATA;\n \t\t\tCNXK_DPI_STRM_INC(*c_desc, head);\n \t\t\tbreak;\n \t\t}\n-\n-\t\tcomp_ptr->cdata = CNXK_DPI_REQ_CDATA;\n+\t\tc_desc->compl_ptr[c_desc->head * CNXK_DPI_COMPL_OFFSET] = CNXK_DPI_REQ_CDATA;\n \t\tCNXK_DPI_STRM_INC(*c_desc, head);\n \t}\n \n@@ -414,19 +399,17 @@ cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan, const uint16_t n\n \tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n \tstruct cnxk_dpi_conf *dpi_conf = &dpivf->conf[vchan];\n \tstruct cnxk_dpi_cdesc_data_s *c_desc = &dpi_conf->c_desc;\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n \tint cnt;\n \n \tfor (cnt = 0; cnt < nb_cpls; cnt++) {\n-\t\tcomp_ptr = c_desc->compl_ptr[c_desc->head];\n-\t\tstatus[cnt] = comp_ptr->cdata;\n+\t\tstatus[cnt] = c_desc->compl_ptr[c_desc->head * CNXK_DPI_COMPL_OFFSET];\n \t\tif (status[cnt]) {\n \t\t\tif (status[cnt] == CNXK_DPI_REQ_CDATA)\n \t\t\t\tbreak;\n \n \t\t\tdpi_conf->stats.errors++;\n \t\t}\n-\t\tcomp_ptr->cdata = CNXK_DPI_REQ_CDATA;\n+\t\tc_desc->compl_ptr[c_desc->head * CNXK_DPI_COMPL_OFFSET] = CNXK_DPI_REQ_CDATA;\n \t\tCNXK_DPI_STRM_INC(*c_desc, head);\n \t}\n \n@@ -593,7 +576,7 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_de\n \trdpi = &dpivf->rdpi;\n \n \trdpi->pci_dev = pci_dev;\n-\trc = roc_dpi_dev_init(rdpi, offsetof(struct cnxk_dpi_compl_s, wqecs));\n+\trc = roc_dpi_dev_init(rdpi, offsetof(struct rte_event_dma_adapter_op, impl_opaque));\n \tif (rc < 0)\n \t\tgoto err_out_free;\n \ndiff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h\nindex 610a360ba2..a80db333a0 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev.h\n+++ b/drivers/dma/cnxk/cnxk_dmadev.h\n@@ -37,17 +37,12 @@\n #define CNXK_DPI_MAX_CMD_SZ\t\t CNXK_DPI_CMD_LEN(CNXK_DPI_MAX_POINTER,\t\t\\\n \t\t\t\t\t\t\t CNXK_DPI_MAX_POINTER)\n #define CNXK_DPI_CHUNKS_FROM_DESC(cz, desc) (((desc) / (((cz) / 8) / CNXK_DPI_MAX_CMD_SZ)) + 1)\n-\n+#define CNXK_DPI_COMPL_OFFSET\t\t ROC_CACHE_LINE_SZ\n /* Set Completion data to 0xFF when request submitted,\n * upon successful request completion engine reset to completion status\n */\n #define CNXK_DPI_REQ_CDATA 0xFF\n \n-/* Set Completion data to 0xDEADBEEF when request submitted for SSO.\n- * This helps differentiate if the dequeue is called after cnxk enueue.\n- */\n-#define CNXK_DPI_REQ_SSO_CDATA 0xDEADBEEF\n-\n union cnxk_dpi_instr_cmd {\n \tuint64_t u;\n \tstruct cn9k_dpi_instr_cmd {\n@@ -91,24 +86,11 @@ union cnxk_dpi_instr_cmd {\n \t} cn10k;\n };\n \n-struct cnxk_dpi_compl_s {\n-\tuint64_t cdata;\n-\tvoid *op;\n-\tuint16_t dev_id;\n-\tuint16_t vchan;\n-\tuint32_t wqecs;\n-};\n-\n struct cnxk_dpi_cdesc_data_s {\n-\tstruct cnxk_dpi_compl_s **compl_ptr;\n \tuint16_t max_cnt;\n \tuint16_t head;\n \tuint16_t tail;\n-};\n-\n-struct cnxk_dma_adapter_info {\n-\tbool enabled; /* Set if vchan queue is added to dma adapter. */\n-\tstruct rte_mempool *req_mp; /* DMA inflight request mempool. */\n+\tuint8_t *compl_ptr;\n };\n \n struct cnxk_dpi_conf {\n@@ -119,7 +101,7 @@ struct cnxk_dpi_conf {\n \tuint16_t desc_idx;\n \tstruct rte_dma_stats stats;\n \tuint64_t completed_offset;\n-\tstruct cnxk_dma_adapter_info adapter_info;\n+\tbool adapter_enabled;\n };\n \n struct cnxk_dpi_vf_s {\ndiff --git a/drivers/dma/cnxk/cnxk_dmadev_fp.c b/drivers/dma/cnxk/cnxk_dmadev_fp.c\nindex 9f7f9b2eed..38f4524439 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev_fp.c\n+++ b/drivers/dma/cnxk/cnxk_dmadev_fp.c\n@@ -245,14 +245,14 @@ cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t d\n \tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n \tstruct cnxk_dpi_conf *dpi_conf = &dpivf->conf[vchan];\n \tuint64_t cmd[CNXK_DPI_DW_PER_SINGLE_CMD];\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tuint8_t *comp_ptr;\n \tint rc;\n \n \tif (unlikely(((dpi_conf->c_desc.tail + 1) & dpi_conf->c_desc.max_cnt) ==\n \t\t dpi_conf->c_desc.head))\n \t\treturn -ENOSPC;\n \n-\tcomp_ptr = dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail];\n+\tcomp_ptr = &dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail * CNXK_DPI_COMPL_OFFSET];\n \tCNXK_DPI_STRM_INC(dpi_conf->c_desc, tail);\n \n \tcmd[0] = (1UL << 54) | (1UL << 48);\n@@ -301,7 +301,7 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge\n \tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n \tstruct cnxk_dpi_conf *dpi_conf = &dpivf->conf[vchan];\n \tconst struct rte_dma_sge *fptr, *lptr;\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tuint8_t *comp_ptr;\n \tuint64_t hdr[4];\n \tint rc;\n \n@@ -309,7 +309,7 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge\n \t\t dpi_conf->c_desc.head))\n \t\treturn -ENOSPC;\n \n-\tcomp_ptr = dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail];\n+\tcomp_ptr = &dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail * CNXK_DPI_COMPL_OFFSET];\n \tCNXK_DPI_STRM_INC(dpi_conf->c_desc, tail);\n \n \thdr[1] = dpi_conf->cmd.u | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << 37);\n@@ -357,14 +357,14 @@ cn10k_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t\n \tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n \tstruct cnxk_dpi_conf *dpi_conf = &dpivf->conf[vchan];\n \tuint64_t cmd[CNXK_DPI_DW_PER_SINGLE_CMD];\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tuint8_t *comp_ptr;\n \tint rc;\n \n \tif (unlikely(((dpi_conf->c_desc.tail + 1) & dpi_conf->c_desc.max_cnt) ==\n \t\t dpi_conf->c_desc.head))\n \t\treturn -ENOSPC;\n \n-\tcomp_ptr = dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail];\n+\tcomp_ptr = &dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail * CNXK_DPI_COMPL_OFFSET];\n \tCNXK_DPI_STRM_INC(dpi_conf->c_desc, tail);\n \n \tcmd[0] = dpi_conf->cmd.u | (1U << 6) | 1U;\n@@ -403,7 +403,7 @@ cn10k_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge\n {\n \tstruct cnxk_dpi_vf_s *dpivf = dev_private;\n \tstruct cnxk_dpi_conf *dpi_conf = &dpivf->conf[vchan];\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tuint8_t *comp_ptr;\n \tuint64_t hdr[4];\n \tint rc;\n \n@@ -411,7 +411,7 @@ cn10k_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge\n \t\t dpi_conf->c_desc.head))\n \t\treturn -ENOSPC;\n \n-\tcomp_ptr = dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail];\n+\tcomp_ptr = &dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail * CNXK_DPI_COMPL_OFFSET];\n \tCNXK_DPI_STRM_INC(dpi_conf->c_desc, tail);\n \n \thdr[0] = dpi_conf->cmd.u | (nb_dst << 6) | nb_src;\n@@ -454,7 +454,6 @@ cn10k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events)\n {\n \tconst struct rte_dma_sge *src, *dst;\n \tstruct rte_event_dma_adapter_op *op;\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n \tstruct cnxk_dpi_conf *dpi_conf;\n \tstruct cnxk_dpi_vf_s *dpivf;\n \tstruct cn10k_sso_hws *work;\n@@ -471,20 +470,12 @@ cn10k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events)\n \t\tdpivf = rte_dma_fp_objs[op->dma_dev_id].dev_private;\n \t\tdpi_conf = &dpivf->conf[op->vchan];\n \n-\t\tif (unlikely(rte_mempool_get(dpi_conf->adapter_info.req_mp, (void **)&comp_ptr)))\n-\t\t\treturn count;\n-\n-\t\tcomp_ptr->op = op;\n-\t\tcomp_ptr->dev_id = op->dma_dev_id;\n-\t\tcomp_ptr->vchan = op->vchan;\n-\t\tcomp_ptr->cdata = CNXK_DPI_REQ_SSO_CDATA;\n-\n \t\tnb_src = op->nb_src & CNXK_DPI_MAX_POINTER;\n \t\tnb_dst = op->nb_dst & CNXK_DPI_MAX_POINTER;\n \n \t\thdr[0] = dpi_conf->cmd.u | ((uint64_t)DPI_HDR_PT_WQP << 54);\n \t\thdr[0] |= (nb_dst << 6) | nb_src;\n-\t\thdr[1] = ((uint64_t)comp_ptr);\n+\t\thdr[1] = (uint64_t)op;\n \t\thdr[2] = cnxk_dma_adapter_format_event(ev[count].event);\n \n \t\tsrc = &op->src_dst_seg[0];\n@@ -524,7 +515,6 @@ cn9k_dma_adapter_dual_enqueue(void *ws, struct rte_event ev[], uint16_t nb_event\n {\n \tconst struct rte_dma_sge *fptr, *lptr;\n \tstruct rte_event_dma_adapter_op *op;\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n \tstruct cn9k_sso_hws_dual *work;\n \tstruct cnxk_dpi_conf *dpi_conf;\n \tstruct cnxk_dpi_vf_s *dpivf;\n@@ -544,16 +534,8 @@ cn9k_dma_adapter_dual_enqueue(void *ws, struct rte_event ev[], uint16_t nb_event\n \t\tdpivf = rte_dma_fp_objs[op->dma_dev_id].dev_private;\n \t\tdpi_conf = &dpivf->conf[op->vchan];\n \n-\t\tif (unlikely(rte_mempool_get(dpi_conf->adapter_info.req_mp, (void **)&comp_ptr)))\n-\t\t\treturn count;\n-\n-\t\tcomp_ptr->op = op;\n-\t\tcomp_ptr->dev_id = op->dma_dev_id;\n-\t\tcomp_ptr->vchan = op->vchan;\n-\t\tcomp_ptr->cdata = CNXK_DPI_REQ_SSO_CDATA;\n-\n \t\thdr[1] = dpi_conf->cmd.u | ((uint64_t)DPI_HDR_PT_WQP << 36);\n-\t\thdr[2] = (uint64_t)comp_ptr;\n+\t\thdr[2] = (uint64_t)op;\n \n \t\tnb_src = op->nb_src & CNXK_DPI_MAX_POINTER;\n \t\tnb_dst = op->nb_dst & CNXK_DPI_MAX_POINTER;\n@@ -605,7 +587,6 @@ cn9k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events)\n {\n \tconst struct rte_dma_sge *fptr, *lptr;\n \tstruct rte_event_dma_adapter_op *op;\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n \tstruct cnxk_dpi_conf *dpi_conf;\n \tstruct cnxk_dpi_vf_s *dpivf;\n \tstruct cn9k_sso_hws *work;\n@@ -622,16 +603,8 @@ cn9k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events)\n \t\tdpivf = rte_dma_fp_objs[op->dma_dev_id].dev_private;\n \t\tdpi_conf = &dpivf->conf[op->vchan];\n \n-\t\tif (unlikely(rte_mempool_get(dpi_conf->adapter_info.req_mp, (void **)&comp_ptr)))\n-\t\t\treturn count;\n-\n-\t\tcomp_ptr->op = op;\n-\t\tcomp_ptr->dev_id = op->dma_dev_id;\n-\t\tcomp_ptr->vchan = op->vchan;\n-\t\tcomp_ptr->cdata = CNXK_DPI_REQ_SSO_CDATA;\n-\n \t\thdr[1] = dpi_conf->cmd.u | ((uint64_t)DPI_HDR_PT_WQP << 36);\n-\t\thdr[2] = (uint64_t)comp_ptr;\n+\t\thdr[2] = (uint64_t)op;\n \n \t\tnb_src = op->nb_src & CNXK_DPI_MAX_POINTER;\n \t\tnb_dst = op->nb_dst & CNXK_DPI_MAX_POINTER;\n@@ -682,38 +655,20 @@ uintptr_t\n cnxk_dma_adapter_dequeue(uintptr_t get_work1)\n {\n \tstruct rte_event_dma_adapter_op *op;\n-\tstruct cnxk_dpi_compl_s *comp_ptr;\n \tstruct cnxk_dpi_conf *dpi_conf;\n \tstruct cnxk_dpi_vf_s *dpivf;\n-\trte_mcslock_t mcs_lock_me;\n-\tRTE_ATOMIC(uint8_t) *wqecs;\n-\n-\tcomp_ptr = (struct cnxk_dpi_compl_s *)get_work1;\n-\n-\t/* Dequeue can be called without calling cnx_enqueue in case of\n-\t * dma_adapter. When its called from adapter, dma op will not be\n-\t * embedded in completion pointer. In those cases return op.\n-\t */\n-\tif (comp_ptr->cdata != CNXK_DPI_REQ_SSO_CDATA)\n-\t\treturn (uintptr_t)comp_ptr;\n \n-\tdpivf =\trte_dma_fp_objs[comp_ptr->dev_id].dev_private;\n-\tdpi_conf = &dpivf->conf[comp_ptr->vchan];\n+\top = (struct rte_event_dma_adapter_op *)get_work1;\n+\tdpivf = rte_dma_fp_objs[op->dma_dev_id].dev_private;\n+\tdpi_conf = &dpivf->conf[op->vchan];\n \n-\trte_mcslock_lock(&dpivf->mcs_lock, &mcs_lock_me);\n-\twqecs = (uint8_t __rte_atomic *)&comp_ptr->wqecs;\n-\tif (rte_atomic_load_explicit(wqecs, rte_memory_order_relaxed) != 0)\n-\t\tdpi_conf->stats.errors++;\n+\tif (rte_atomic_load_explicit(&op->impl_opaque[0], rte_memory_order_relaxed) != 0)\n+\t\trte_atomic_fetch_add_explicit(&dpi_conf->stats.errors, 1, rte_memory_order_relaxed);\n \n \t/* Take into account errors also. This is similar to\n \t * cnxk_dmadev_completed_status().\n \t */\n-\tdpi_conf->stats.completed++;\n-\trte_mcslock_unlock(&dpivf->mcs_lock, &mcs_lock_me);\n-\n-\top = (struct rte_event_dma_adapter_op *)comp_ptr->op;\n-\n-\trte_mempool_put(dpi_conf->adapter_info.req_mp, comp_ptr);\n+\trte_atomic_fetch_add_explicit(&dpi_conf->stats.completed, 1, rte_memory_order_relaxed);\n \n \treturn (uintptr_t)op;\n }\ndiff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c\nindex a2a59b16c9..98db11ad61 100644\n--- a/drivers/event/cnxk/cnxk_eventdev_adptr.c\n+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c\n@@ -739,31 +739,6 @@ cnxk_crypto_adapter_qp_del(const struct rte_cryptodev *cdev,\n \treturn 0;\n }\n \n-static int\n-dma_adapter_vchan_setup(const int16_t dma_dev_id, struct cnxk_dpi_conf *vchan,\n-\t\t\tuint16_t vchan_id)\n-{\n-\tchar name[RTE_MEMPOOL_NAMESIZE];\n-\tuint32_t cache_size, nb_req;\n-\tunsigned int req_size;\n-\n-\tsnprintf(name, RTE_MEMPOOL_NAMESIZE, \"cnxk_dma_req_%u:%u\", dma_dev_id, vchan_id);\n-\treq_size = sizeof(struct cnxk_dpi_compl_s);\n-\n-\tnb_req = vchan->c_desc.max_cnt;\n-\tcache_size = 16;\n-\tnb_req += (cache_size * rte_lcore_count());\n-\n-\tvchan->adapter_info.req_mp = rte_mempool_create(name, nb_req, req_size, cache_size, 0,\n-\t\t\t\t\t\t\tNULL, NULL, NULL, NULL, rte_socket_id(), 0);\n-\tif (vchan->adapter_info.req_mp == NULL)\n-\t\treturn -ENOMEM;\n-\n-\tvchan->adapter_info.enabled = true;\n-\n-\treturn 0;\n-}\n-\n int\n cnxk_dma_adapter_vchan_add(const struct rte_eventdev *event_dev,\n \t\t\t const int16_t dma_dev_id, uint16_t vchan_id)\n@@ -772,7 +747,6 @@ cnxk_dma_adapter_vchan_add(const struct rte_eventdev *event_dev,\n \tuint32_t adptr_xae_cnt = 0;\n \tstruct cnxk_dpi_vf_s *dpivf;\n \tstruct cnxk_dpi_conf *vchan;\n-\tint ret;\n \n \tdpivf = rte_dma_fp_objs[dma_dev_id].dev_private;\n \tif ((int16_t)vchan_id == -1) {\n@@ -780,19 +754,13 @@ cnxk_dma_adapter_vchan_add(const struct rte_eventdev *event_dev,\n \n \t\tfor (vchan_id = 0; vchan_id < dpivf->num_vchans; vchan_id++) {\n \t\t\tvchan = &dpivf->conf[vchan_id];\n-\t\t\tret = dma_adapter_vchan_setup(dma_dev_id, vchan, vchan_id);\n-\t\t\tif (ret) {\n-\t\t\t\tcnxk_dma_adapter_vchan_del(dma_dev_id, -1);\n-\t\t\t\treturn ret;\n-\t\t\t}\n-\t\t\tadptr_xae_cnt += vchan->adapter_info.req_mp->size;\n+\t\t\tvchan->adapter_enabled = true;\n+\t\t\tadptr_xae_cnt += vchan->c_desc.max_cnt;\n \t\t}\n \t} else {\n \t\tvchan = &dpivf->conf[vchan_id];\n-\t\tret = dma_adapter_vchan_setup(dma_dev_id, vchan, vchan_id);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t\tadptr_xae_cnt = vchan->adapter_info.req_mp->size;\n+\t\tvchan->adapter_enabled = true;\n+\t\tadptr_xae_cnt = vchan->c_desc.max_cnt;\n \t}\n \n \t/* Update dma adapter XAE count */\n@@ -805,8 +773,7 @@ cnxk_dma_adapter_vchan_add(const struct rte_eventdev *event_dev,\n static int\n dma_adapter_vchan_free(struct cnxk_dpi_conf *vchan)\n {\n-\trte_mempool_free(vchan->adapter_info.req_mp);\n-\tvchan->adapter_info.enabled = false;\n+\tvchan->adapter_enabled = false;\n \n \treturn 0;\n }\n@@ -823,12 +790,12 @@ cnxk_dma_adapter_vchan_del(const int16_t dma_dev_id, uint16_t vchan_id)\n \n \t\tfor (vchan_id = 0; vchan_id < dpivf->num_vchans; vchan_id++) {\n \t\t\tvchan = &dpivf->conf[vchan_id];\n-\t\t\tif (vchan->adapter_info.enabled)\n+\t\t\tif (vchan->adapter_enabled)\n \t\t\t\tdma_adapter_vchan_free(vchan);\n \t\t}\n \t} else {\n \t\tvchan = &dpivf->conf[vchan_id];\n-\t\tif (vchan->adapter_info.enabled)\n+\t\tif (vchan->adapter_enabled)\n \t\t\tdma_adapter_vchan_free(vchan);\n \t}\n \n", "prefixes": [ "v2", "2/2" ] }