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GET /api/patches/138882/?format=api
{ "id": 138882, "url": "http://patches.dpdk.org/api/patches/138882/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1711579078-10624-7-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1711579078-10624-7-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1711579078-10624-7-git-send-email-roretzla@linux.microsoft.com", "date": "2024-03-27T22:37:19", "name": "[v3,06/45] net/hns3: use rte stdatomic API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "5f11f4496fd666c705e8409f14f9f5dbc3d13803", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1711579078-10624-7-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31633, "url": "http://patches.dpdk.org/api/series/31633/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31633", "date": "2024-03-27T22:37:13", "name": "use stdatomic API", "version": 3, "mbox": "http://patches.dpdk.org/series/31633/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/138882/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/138882/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DFAEE43D55;\n\tWed, 27 Mar 2024 23:38:41 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3565542D66;\n\tWed, 27 Mar 2024 23:38:10 +0100 (CET)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id 9A674402C0\n for <dev@dpdk.org>; Wed, 27 Mar 2024 23:38:01 +0100 (CET)", "by linux.microsoft.com (Postfix, from userid 1086)\n id 3824620E6948; Wed, 27 Mar 2024 15:37:59 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 3824620E6948", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1711579080;\n bh=pYD7hDp8k7StA1O6X3vDIBJyxcN0mfe4B00G6iVgTio=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=G64WhWdaeXqmv2R4/+OJ+eWmNt4OY7MKUJNJMazYo06jq5N12Tqxk3F0fHwUJcnb+\n InWLsEVXam4+2aouqNVIrXDZX5/xBzJXUxzf76Pz+TA1WTN7tzjW//NIIDz87s/8Em\n y74UOwWnb8IjOhFrYRyMdcNC4tAYE2J53TZqV1Zg=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>,\n\t=?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>,\n Abdullah Sevincer <abdullah.sevincer@intel.com>,\n Ajit Khaparde <ajit.khaparde@broadcom.com>, Alok Prasad <palok@marvell.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Anoob Joseph <anoobj@marvell.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Byron Marohn <byron.marohn@intel.com>, Chenbo Xia <chenbox@nvidia.com>,\n Chengwen Feng <fengchengwen@huawei.com>,\n Ciara Loftus <ciara.loftus@intel.com>, Ciara Power <ciara.power@intel.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, David Hunt <david.hunt@intel.com>,\n Devendra Singh Rawat <dsinghrawat@marvell.com>,\n Erik Gabriel Carrillo <erik.g.carrillo@intel.com>,\n Guoyang Zhou <zhouguoyang@huawei.com>, Harman Kalra <hkalra@marvell.com>,\n Harry van Haaren <harry.van.haaren@intel.com>,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,\n Jakub Grajciar <jgrajcia@cisco.com>, Jerin Jacob <jerinj@marvell.com>,\n Jeroen de Borst <jeroendb@google.com>, Jian Wang <jianwang@trustnetic.com>,\n Jiawen Wu <jiawenwu@trustnetic.com>, Jie Hai <haijie1@huawei.com>,\n Jingjing Wu <jingjing.wu@intel.com>, Joshua Washington <joshwash@google.com>,\n Joyce Kong <joyce.kong@arm.com>, Junfeng Guo <junfeng.guo@intel.com>,\n Kevin Laatz <kevin.laatz@intel.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Liang Ma <liangma@liangbit.com>, Long Li <longli@microsoft.com>,\n Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Nicolas Chautru <nicolas.chautru@intel.com>, Ori Kam <orika@nvidia.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>,\n Peter Mccarthy <peter.mccarthy@intel.com>,\n Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>,\n Reshma Pattan <reshma.pattan@intel.com>, Rosen Xu <rosen.xu@intel.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Rushil Gupta <rushilg@google.com>,\n Sameh Gobriel <sameh.gobriel@intel.com>,\n Sivaprasad Tummala <sivaprasad.tummala@amd.com>,\n Somnath Kotur <somnath.kotur@broadcom.com>,\n Stephen Hemminger <stephen@networkplumber.org>,\n Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,\n Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>,\n Tetsuya Mukawa <mtetsuyah@gmail.com>, Vamsi Attunuru <vattunuru@marvell.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Vladimir Medvedkin <vladimir.medvedkin@intel.com>,\n Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>,\n Yipeng Wang <yipeng1.wang@intel.com>, Yisen Zhuang <yisen.zhuang@huawei.com>,\n Yuying Zhang <Yuying.Zhang@intel.com>, Yuying Zhang <yuying.zhang@intel.com>,\n Ziyang Xuan <xuanziyang2@huawei.com>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v3 06/45] net/hns3: use rte stdatomic API", "Date": "Wed, 27 Mar 2024 15:37:19 -0700", "Message-Id": "<1711579078-10624-7-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1711579078-10624-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1710967892-7046-1-git-send-email-roretzla@linux.microsoft.com>\n <1711579078-10624-1-git-send-email-roretzla@linux.microsoft.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Replace the use of gcc builtin __atomic_xxx intrinsics with\ncorresponding rte_atomic_xxx optional rte stdatomic API.\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\nAcked-by: Stephen Hemminger <stephen@networkplumber.org>\n---\n drivers/net/hns3/hns3_cmd.c | 18 ++++++------\n drivers/net/hns3/hns3_dcb.c | 2 +-\n drivers/net/hns3/hns3_ethdev.c | 36 +++++++++++------------\n drivers/net/hns3/hns3_ethdev.h | 32 ++++++++++-----------\n drivers/net/hns3/hns3_ethdev_vf.c | 60 +++++++++++++++++++--------------------\n drivers/net/hns3/hns3_intr.c | 36 +++++++++++------------\n drivers/net/hns3/hns3_intr.h | 4 +--\n drivers/net/hns3/hns3_mbx.c | 6 ++--\n drivers/net/hns3/hns3_mp.c | 6 ++--\n drivers/net/hns3/hns3_rxtx.c | 10 +++----\n drivers/net/hns3/hns3_tm.c | 4 +--\n 11 files changed, 107 insertions(+), 107 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c\nindex 001ff49..3c5fdbe 100644\n--- a/drivers/net/hns3/hns3_cmd.c\n+++ b/drivers/net/hns3/hns3_cmd.c\n@@ -44,12 +44,12 @@\n hns3_allocate_dma_mem(struct hns3_hw *hw, struct hns3_cmq_ring *ring,\n \t\t uint64_t size, uint32_t alignment)\n {\n-\tstatic uint64_t hns3_dma_memzone_id;\n+\tstatic RTE_ATOMIC(uint64_t) hns3_dma_memzone_id;\n \tconst struct rte_memzone *mz = NULL;\n \tchar z_name[RTE_MEMZONE_NAMESIZE];\n \n \tsnprintf(z_name, sizeof(z_name), \"hns3_dma_%\" PRIu64,\n-\t\t__atomic_fetch_add(&hns3_dma_memzone_id, 1, __ATOMIC_RELAXED));\n+\t\trte_atomic_fetch_add_explicit(&hns3_dma_memzone_id, 1, rte_memory_order_relaxed));\n \tmz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,\n \t\t\t\t\t RTE_MEMZONE_IOVA_CONTIG, alignment,\n \t\t\t\t\t RTE_PGSIZE_2M);\n@@ -198,8 +198,8 @@\n \t\thns3_err(hw, \"wrong cmd addr(%0x) head (%u, %u-%u)\", addr, head,\n \t\t\t csq->next_to_use, csq->next_to_clean);\n \t\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n-\t\t\t__atomic_store_n(&hw->reset.disable_cmd, 1,\n-\t\t\t\t\t __ATOMIC_RELAXED);\n+\t\t\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1,\n+\t\t\t\t\t rte_memory_order_relaxed);\n \t\t\thns3_schedule_delayed_reset(HNS3_DEV_HW_TO_ADAPTER(hw));\n \t\t}\n \n@@ -313,7 +313,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)\n \t\tif (hns3_cmd_csq_done(hw))\n \t\t\treturn 0;\n \n-\t\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {\n+\t\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed)) {\n \t\t\thns3_err(hw,\n \t\t\t\t \"Don't wait for reply because of disable_cmd\");\n \t\t\treturn -EBUSY;\n@@ -360,7 +360,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)\n \tint retval;\n \tuint32_t ntc;\n \n-\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))\n+\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed))\n \t\treturn -EBUSY;\n \n \trte_spinlock_lock(&hw->cmq.csq.lock);\n@@ -747,7 +747,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)\n \t\tret = -EBUSY;\n \t\tgoto err_cmd_init;\n \t}\n-\t__atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.disable_cmd, 0, rte_memory_order_relaxed);\n \n \tret = hns3_cmd_query_firmware_version_and_capability(hw);\n \tif (ret) {\n@@ -790,7 +790,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)\n \treturn 0;\n \n err_cmd_init:\n-\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);\n \treturn ret;\n }\n \n@@ -819,7 +819,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)\n \tif (!hns->is_vf)\n \t\t(void)hns3_firmware_compat_config(hw, false);\n \n-\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);\n \n \t/*\n \t * A delay is added to ensure that the register cleanup operations\ndiff --git a/drivers/net/hns3/hns3_dcb.c b/drivers/net/hns3/hns3_dcb.c\nindex 915e4eb..2f917fe 100644\n--- a/drivers/net/hns3/hns3_dcb.c\n+++ b/drivers/net/hns3/hns3_dcb.c\n@@ -648,7 +648,7 @@\n \t * and configured directly to the hardware in the RESET_STAGE_RESTORE\n \t * stage of the reset process.\n \t */\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0) {\n \t\tfor (i = 0; i < hw->rss_ind_tbl_size; i++)\n \t\t\trss_cfg->rss_indirection_tbl[i] =\n \t\t\t\t\t\t\ti % hw->alloc_rss_size;\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 9730b9a..327f6fe 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -99,7 +99,7 @@ struct hns3_intr_state {\n };\n \n static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,\n-\t\t\t\t\t\t uint64_t *levels);\n+\t\t\t\t\t\t RTE_ATOMIC(uint64_t) *levels);\n static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,\n \t\t\t\t int on);\n@@ -134,7 +134,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n {\n \tstruct hns3_hw *hw = &hns->hw;\n \n-\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);\n \thns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);\n \t*vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);\n \thw->reset.stats.imp_cnt++;\n@@ -148,7 +148,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n {\n \tstruct hns3_hw *hw = &hns->hw;\n \n-\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);\n \thns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);\n \t*vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);\n \thw->reset.stats.global_cnt++;\n@@ -1151,7 +1151,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \t * ensure that the hardware configuration remains unchanged before and\n \t * after reset.\n \t */\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0) {\n \t\thw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;\n \t\thw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;\n \t}\n@@ -1175,7 +1175,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \t * we will restore configurations to hardware in hns3_restore_vlan_table\n \t * and hns3_restore_vlan_conf later.\n \t */\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0) {\n \t\tret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);\n \t\tif (ret) {\n \t\t\thns3_err(hw, \"pvid set fail in pf, ret =%d\", ret);\n@@ -5059,7 +5059,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \tint ret;\n \n \tPMD_INIT_FUNC_TRACE();\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed))\n \t\treturn -EBUSY;\n \n \trte_spinlock_lock(&hw->lock);\n@@ -5150,7 +5150,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \t * during reset and is required to be released after the reset is\n \t * completed.\n \t */\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0)\n \t\thns3_dev_release_mbufs(hns);\n \n \tret = hns3_cfg_mac_mode(hw, false);\n@@ -5158,7 +5158,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \t\treturn ret;\n \thw->mac.link_status = RTE_ETH_LINK_DOWN;\n \n-\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {\n+\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed) == 0) {\n \t\thns3_configure_all_mac_addr(hns, true);\n \t\tret = hns3_reset_all_tqps(hns);\n \t\tif (ret) {\n@@ -5184,7 +5184,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \thns3_stop_rxtx_datapath(dev);\n \n \trte_spinlock_lock(&hw->lock);\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0) {\n \t\thns3_tm_dev_stop_proc(hw);\n \t\thns3_config_mac_tnl_int(hw, false);\n \t\thns3_stop_tqps(hw);\n@@ -5577,7 +5577,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \n \tlast_req = hns3_get_reset_level(hns, &hw->reset.pending);\n \tif (last_req == HNS3_NONE_RESET || last_req < new_req) {\n-\t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\t\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);\n \t\thns3_schedule_delayed_reset(hns);\n \t\thns3_warn(hw, \"High level reset detected, delay do reset\");\n \t\treturn true;\n@@ -5677,7 +5677,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n }\n \n static enum hns3_reset_level\n-hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)\n+hns3_get_reset_level(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels)\n {\n \tstruct hns3_hw *hw = &hns->hw;\n \tenum hns3_reset_level reset_level = HNS3_NONE_RESET;\n@@ -5737,7 +5737,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \t\t * any mailbox handling or command to firmware is only valid\n \t\t * after hns3_cmd_init is called.\n \t\t */\n-\t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\t\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);\n \t\thw->reset.stats.request_cnt++;\n \t\tbreak;\n \tcase HNS3_IMP_RESET:\n@@ -5792,7 +5792,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \t * from table space. Hence, for function reset software intervention is\n \t * required to delete the entries\n \t */\n-\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)\n+\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed) == 0)\n \t\thns3_configure_all_mc_mac_addr(hns, true);\n \trte_spinlock_unlock(&hw->lock);\n \n@@ -5913,10 +5913,10 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \t * The interrupt may have been lost. It is necessary to handle\n \t * the interrupt to recover from the error.\n \t */\n-\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\tif (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==\n \t\t\t SCHEDULE_DEFERRED) {\n-\t\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,\n-\t\t\t\t __ATOMIC_RELAXED);\n+\t\trte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_REQUESTED,\n+\t\t\t\t rte_memory_order_relaxed);\n \t\thns3_err(hw, \"Handling interrupts in delayed tasks\");\n \t\thns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);\n \t\treset_level = hns3_get_reset_level(hns, &hw->reset.pending);\n@@ -5925,7 +5925,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \t\t\thns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);\n \t\t}\n \t}\n-\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_NONE, rte_memory_order_relaxed);\n \n \t/*\n \t * Check if there is any ongoing reset in the hardware. This status can\n@@ -6576,7 +6576,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,\n \n \thw->adapter_state = HNS3_NIC_INITIALIZED;\n \n-\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\tif (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==\n \t\t\t SCHEDULE_PENDING) {\n \t\thns3_err(hw, \"Reschedule reset service after dev_init\");\n \t\thns3_schedule_reset(hns);\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex e70c5ff..4c0f076 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -401,17 +401,17 @@ enum hns3_schedule {\n \n struct hns3_reset_data {\n \tenum hns3_reset_stage stage;\n-\tuint16_t schedule;\n+\tRTE_ATOMIC(uint16_t) schedule;\n \t/* Reset flag, covering the entire reset process */\n-\tuint16_t resetting;\n+\tRTE_ATOMIC(uint16_t) resetting;\n \t/* Used to disable sending cmds during reset */\n-\tuint16_t disable_cmd;\n+\tRTE_ATOMIC(uint16_t) disable_cmd;\n \t/* The reset level being processed */\n \tenum hns3_reset_level level;\n \t/* Reset level set, each bit represents a reset level */\n-\tuint64_t pending;\n+\tRTE_ATOMIC(uint64_t) pending;\n \t/* Request reset level set, from interrupt or mailbox */\n-\tuint64_t request;\n+\tRTE_ATOMIC(uint64_t) request;\n \tint attempts; /* Reset failure retry */\n \tint retries; /* Timeout failure retry in reset_post */\n \t/*\n@@ -499,7 +499,7 @@ struct hns3_hw {\n \t * by dev_set_link_up() or dev_start().\n \t */\n \tbool set_link_down;\n-\tunsigned int secondary_cnt; /* Number of secondary processes init'd. */\n+\tRTE_ATOMIC(unsigned int) secondary_cnt; /* Number of secondary processes init'd. */\n \tstruct hns3_tqp_stats tqp_stats;\n \t/* Include Mac stats | Rx stats | Tx stats */\n \tstruct hns3_mac_stats mac_stats;\n@@ -844,7 +844,7 @@ struct hns3_vf {\n \tstruct hns3_adapter *adapter;\n \n \t/* Whether PF support push link status change to VF */\n-\tuint16_t pf_push_lsc_cap;\n+\tRTE_ATOMIC(uint16_t) pf_push_lsc_cap;\n \n \t/*\n \t * If PF support push link status change, VF still need send request to\n@@ -853,7 +853,7 @@ struct hns3_vf {\n \t */\n \tuint16_t req_link_info_cnt;\n \n-\tuint16_t poll_job_started; /* whether poll job is started */\n+\tRTE_ATOMIC(uint16_t) poll_job_started; /* whether poll job is started */\n };\n \n struct hns3_adapter {\n@@ -997,32 +997,32 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg)\n \thns3_read_reg((a)->io_base, (reg))\n \n static inline uint64_t\n-hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)\n+hns3_atomic_test_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr)\n {\n \tuint64_t res;\n \n-\tres = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;\n+\tres = (rte_atomic_load_explicit(addr, rte_memory_order_relaxed) & (1UL << nr)) != 0;\n \treturn res;\n }\n \n static inline void\n-hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)\n+hns3_atomic_set_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr)\n {\n-\t__atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);\n+\trte_atomic_fetch_or_explicit(addr, (1UL << nr), rte_memory_order_relaxed);\n }\n \n static inline void\n-hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)\n+hns3_atomic_clear_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr)\n {\n-\t__atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);\n+\trte_atomic_fetch_and_explicit(addr, ~(1UL << nr), rte_memory_order_relaxed);\n }\n \n static inline uint64_t\n-hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)\n+hns3_test_and_clear_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr)\n {\n \tuint64_t mask = (1UL << nr);\n \n-\treturn __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;\n+\treturn rte_atomic_fetch_and_explicit(addr, ~mask, rte_memory_order_relaxed) & mask;\n }\n \n int\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex 4eeb46a..b83d5b9 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -37,7 +37,7 @@ enum hns3vf_evt_cause {\n };\n \n static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,\n-\t\t\t\t\t\t uint64_t *levels);\n+\t\t\t\t\t\t RTE_ATOMIC(uint64_t) *levels);\n static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);\n \n@@ -484,7 +484,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t * MTU value issued by hns3 VF PMD must be less than or equal to\n \t * PF's MTU.\n \t */\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {\n \t\thns3_err(hw, \"Failed to set mtu during resetting\");\n \t\treturn -EIO;\n \t}\n@@ -565,7 +565,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t\trst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);\n \t\thns3_warn(hw, \"resetting reg: 0x%x\", rst_ing_reg);\n \t\thns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);\n-\t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\t\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);\n \t\tval = hns3_read_dev(hw, HNS3_VF_RST_ING);\n \t\thns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);\n \t\tval = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);\n@@ -634,8 +634,8 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \tstruct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);\n \n \tif (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)\n-\t\t__atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,\n-\t\t\t\t\t __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);\n+\t\trte_atomic_compare_exchange_strong_explicit(&vf->pf_push_lsc_cap, &exp, val,\n+\t\t\t\t\t rte_memory_order_acquire, rte_memory_order_acquire);\n }\n \n static void\n@@ -650,8 +650,8 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \tstruct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);\n \tstruct hns3_vf_to_pf_msg req;\n \n-\t__atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,\n-\t\t\t __ATOMIC_RELEASE);\n+\trte_atomic_store_explicit(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,\n+\t\t\t rte_memory_order_release);\n \n \thns3vf_mbx_setup(&req, HNS3_MBX_GET_LINK_STATUS, 0);\n \t(void)hns3vf_mbx_send(hw, &req, false, NULL, 0);\n@@ -666,7 +666,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t\t * mailbox from PF driver to get this capability.\n \t\t */\n \t\thns3vf_handle_mbx_msg(hw);\n-\t\tif (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=\n+\t\tif (rte_atomic_load_explicit(&vf->pf_push_lsc_cap, rte_memory_order_acquire) !=\n \t\t\tHNS3_PF_PUSH_LSC_CAP_UNKNOWN)\n \t\t\tbreak;\n \t\tremain_ms--;\n@@ -677,10 +677,10 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t * state: unknown (means pf not ack), not_supported, supported.\n \t * Here config it as 'not_supported' when it's 'unknown' state.\n \t */\n-\t__atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,\n-\t\t\t\t __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);\n+\trte_atomic_compare_exchange_strong_explicit(&vf->pf_push_lsc_cap, &exp, val,\n+\t\t\t\t rte_memory_order_acquire, rte_memory_order_acquire);\n \n-\tif (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==\n+\tif (rte_atomic_load_explicit(&vf->pf_push_lsc_cap, rte_memory_order_acquire) ==\n \t\tHNS3_PF_PUSH_LSC_CAP_SUPPORTED) {\n \t\thns3_info(hw, \"detect PF support push link status change!\");\n \t} else {\n@@ -920,7 +920,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \tbool send_req;\n \tint ret;\n \n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed))\n \t\treturn;\n \n \tsend_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||\n@@ -956,7 +956,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t * sending request to PF kernel driver, then could update link status by\n \t * process PF kernel driver's link status mailbox message.\n \t */\n-\tif (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))\n+\tif (!rte_atomic_load_explicit(&vf->poll_job_started, rte_memory_order_relaxed))\n \t\treturn;\n \n \tif (hw->adapter_state != HNS3_NIC_STARTED)\n@@ -994,7 +994,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \tstruct hns3_hw *hw = &hns->hw;\n \tint ret;\n \n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {\n \t\thns3_err(hw,\n \t\t\t \"vf set vlan id failed during resetting, vlan_id =%u\",\n \t\t\t vlan_id);\n@@ -1059,7 +1059,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \tunsigned int tmp_mask;\n \tint ret = 0;\n \n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {\n \t\thns3_err(hw, \"vf set vlan offload failed during resetting, mask = 0x%x\",\n \t\t\t mask);\n \t\treturn -EIO;\n@@ -1252,7 +1252,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \tif (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)\n \t\tvf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;\n \n-\t__atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&vf->poll_job_started, 1, rte_memory_order_relaxed);\n \n \thns3vf_service_handler(dev);\n }\n@@ -1264,7 +1264,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \n \trte_eal_alarm_cancel(hns3vf_service_handler, dev);\n \n-\t__atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&vf->poll_job_started, 0, rte_memory_order_relaxed);\n }\n \n static int\n@@ -1500,10 +1500,10 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t * during reset and is required to be released after the reset is\n \t * completed.\n \t */\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0)\n \t\thns3_dev_release_mbufs(hns);\n \n-\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {\n+\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed) == 0) {\n \t\thns3_configure_all_mac_addr(hns, true);\n \t\tret = hns3_reset_all_tqps(hns);\n \t\tif (ret) {\n@@ -1528,7 +1528,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \thns3_stop_rxtx_datapath(dev);\n \n \trte_spinlock_lock(&hw->lock);\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0) {\n \t\thns3_stop_tqps(hw);\n \t\thns3vf_do_stop(hns);\n \t\thns3_unmap_rx_interrupt(dev);\n@@ -1643,7 +1643,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \tint ret;\n \n \tPMD_INIT_FUNC_TRACE();\n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed))\n \t\treturn -EBUSY;\n \n \trte_spinlock_lock(&hw->lock);\n@@ -1773,7 +1773,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \n \tlast_req = hns3vf_get_reset_level(hw, &hw->reset.pending);\n \tif (last_req == HNS3_NONE_RESET || last_req < new_req) {\n-\t\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\t\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);\n \t\thns3_schedule_delayed_reset(hns);\n \t\thns3_warn(hw, \"High level reset detected, delay do reset\");\n \t\treturn true;\n@@ -1847,7 +1847,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n-\t__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);\n \n \treturn 0;\n }\n@@ -1888,7 +1888,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t * from table space. Hence, for function reset software intervention is\n \t * required to delete the entries.\n \t */\n-\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)\n+\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed) == 0)\n \t\thns3_configure_all_mc_mac_addr(hns, true);\n \trte_spinlock_unlock(&hw->lock);\n \n@@ -2030,7 +2030,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n }\n \n static enum hns3_reset_level\n-hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)\n+hns3vf_get_reset_level(struct hns3_hw *hw, RTE_ATOMIC(uint64_t) *levels)\n {\n \tenum hns3_reset_level reset_level;\n \n@@ -2070,10 +2070,10 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t * The interrupt may have been lost. It is necessary to handle\n \t * the interrupt to recover from the error.\n \t */\n-\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\tif (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==\n \t\t\t SCHEDULE_DEFERRED) {\n-\t\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,\n-\t\t\t\t __ATOMIC_RELAXED);\n+\t\trte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_REQUESTED,\n+\t\t\t\t rte_memory_order_relaxed);\n \t\thns3_err(hw, \"Handling interrupts in delayed tasks\");\n \t\thns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);\n \t\treset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);\n@@ -2082,7 +2082,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \t\t\thns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);\n \t\t}\n \t}\n-\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_NONE, rte_memory_order_relaxed);\n \n \t/*\n \t * Hardware reset has been notified, we now have to poll & check if\n@@ -2278,7 +2278,7 @@ static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,\n \n \thw->adapter_state = HNS3_NIC_INITIALIZED;\n \n-\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\tif (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==\n \t\t\t SCHEDULE_PENDING) {\n \t\thns3_err(hw, \"Reschedule reset service after dev_init\");\n \t\thns3_schedule_reset(hns);\ndiff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c\nindex 916bf30..26fa2eb 100644\n--- a/drivers/net/hns3/hns3_intr.c\n+++ b/drivers/net/hns3/hns3_intr.c\n@@ -2033,7 +2033,7 @@ enum hns3_hw_err_report_type {\n \n static int\n hns3_handle_hw_error(struct hns3_adapter *hns, struct hns3_cmd_desc *desc,\n-\t\t int num, uint64_t *levels,\n+\t\t int num, RTE_ATOMIC(uint64_t) *levels,\n \t\t enum hns3_hw_err_report_type err_type)\n {\n \tconst struct hns3_hw_error_desc *err = pf_ras_err_tbl;\n@@ -2104,7 +2104,7 @@ enum hns3_hw_err_report_type {\n }\n \n void\n-hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)\n+hns3_handle_msix_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels)\n {\n \tuint32_t mpf_bd_num, pf_bd_num, bd_num;\n \tstruct hns3_hw *hw = &hns->hw;\n@@ -2151,7 +2151,7 @@ enum hns3_hw_err_report_type {\n }\n \n void\n-hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels)\n+hns3_handle_ras_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels)\n {\n \tuint32_t mpf_bd_num, pf_bd_num, bd_num;\n \tstruct hns3_hw *hw = &hns->hw;\n@@ -2402,7 +2402,7 @@ enum hns3_hw_err_report_type {\n \thw->reset.request = 0;\n \thw->reset.pending = 0;\n \thw->reset.resetting = 0;\n-\t__atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.disable_cmd, 0, rte_memory_order_relaxed);\n \thw->reset.wait_data = rte_zmalloc(\"wait_data\",\n \t\t\t\t\t sizeof(struct hns3_wait_data), 0);\n \tif (!hw->reset.wait_data) {\n@@ -2419,8 +2419,8 @@ enum hns3_hw_err_report_type {\n \n \t/* Reschedule the reset process after successful initialization */\n \tif (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {\n-\t\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_PENDING,\n-\t\t\t\t __ATOMIC_RELAXED);\n+\t\trte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_PENDING,\n+\t\t\t\t rte_memory_order_relaxed);\n \t\treturn;\n \t}\n \n@@ -2428,15 +2428,15 @@ enum hns3_hw_err_report_type {\n \t\treturn;\n \n \t/* Schedule restart alarm if it is not scheduled yet */\n-\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\tif (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==\n \t\t\tSCHEDULE_REQUESTED)\n \t\treturn;\n-\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==\n+\tif (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==\n \t\t\t SCHEDULE_DEFERRED)\n \t\trte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);\n \n-\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,\n-\t\t\t\t __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_REQUESTED,\n+\t\t\t\t rte_memory_order_relaxed);\n \n \trte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);\n }\n@@ -2453,11 +2453,11 @@ enum hns3_hw_err_report_type {\n \t\treturn;\n \t}\n \n-\tif (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) !=\n+\tif (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) !=\n \t\t\t SCHEDULE_NONE)\n \t\treturn;\n-\t__atomic_store_n(&hw->reset.schedule, SCHEDULE_DEFERRED,\n-\t\t\t __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_DEFERRED,\n+\t\t\t rte_memory_order_relaxed);\n \trte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);\n }\n \n@@ -2537,7 +2537,7 @@ enum hns3_hw_err_report_type {\n }\n \n static void\n-hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)\n+hns3_clear_reset_level(struct hns3_hw *hw, RTE_ATOMIC(uint64_t) *levels)\n {\n \tuint64_t merge_cnt = hw->reset.stats.merge_cnt;\n \tuint64_t tmp;\n@@ -2633,7 +2633,7 @@ enum hns3_hw_err_report_type {\n \t * Regardless of whether the execution is successful or not, the\n \t * flow after execution must be continued.\n \t */\n-\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))\n+\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed))\n \t\t(void)hns3_cmd_init(hw);\n reset_fail:\n \thw->reset.attempts = 0;\n@@ -2661,7 +2661,7 @@ enum hns3_hw_err_report_type {\n \tint ret;\n \n \tif (hw->reset.stage == RESET_STAGE_NONE) {\n-\t\t__atomic_store_n(&hns->hw.reset.resetting, 1, __ATOMIC_RELAXED);\n+\t\trte_atomic_store_explicit(&hns->hw.reset.resetting, 1, rte_memory_order_relaxed);\n \t\thw->reset.stage = RESET_STAGE_DOWN;\n \t\thns3_report_reset_begin(hw);\n \t\tret = hw->reset.ops->stop_service(hns);\n@@ -2750,7 +2750,7 @@ enum hns3_hw_err_report_type {\n \t\thns3_notify_reset_ready(hw, false);\n \t\thns3_clear_reset_level(hw, &hw->reset.pending);\n \t\thns3_clear_reset_status(hw);\n-\t\t__atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);\n+\t\trte_atomic_store_explicit(&hns->hw.reset.resetting, 0, rte_memory_order_relaxed);\n \t\thw->reset.attempts = 0;\n \t\thw->reset.stats.success_cnt++;\n \t\thw->reset.stage = RESET_STAGE_NONE;\n@@ -2812,7 +2812,7 @@ enum hns3_hw_err_report_type {\n \t\thw->reset.mbuf_deferred_free = false;\n \t}\n \trte_spinlock_unlock(&hw->lock);\n-\t__atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);\n+\trte_atomic_store_explicit(&hns->hw.reset.resetting, 0, rte_memory_order_relaxed);\n \thw->reset.stage = RESET_STAGE_NONE;\n \thns3_clock_gettime(&tv);\n \ttimersub(&tv, &hw->reset.start_time, &tv_delta);\ndiff --git a/drivers/net/hns3/hns3_intr.h b/drivers/net/hns3/hns3_intr.h\nindex aca1c07..1edb07d 100644\n--- a/drivers/net/hns3/hns3_intr.h\n+++ b/drivers/net/hns3/hns3_intr.h\n@@ -171,8 +171,8 @@ struct hns3_hw_error_desc {\n };\n \n int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en);\n-void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);\n-void hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels);\n+void hns3_handle_msix_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels);\n+void hns3_handle_ras_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels);\n void hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en);\n void hns3_handle_error(struct hns3_adapter *hns);\n \ndiff --git a/drivers/net/hns3/hns3_mbx.c b/drivers/net/hns3/hns3_mbx.c\nindex 9cdbc16..10c6e3b 100644\n--- a/drivers/net/hns3/hns3_mbx.c\n+++ b/drivers/net/hns3/hns3_mbx.c\n@@ -65,7 +65,7 @@\n \n \tmbx_time_limit = (uint32_t)hns->mbx_time_limit_ms * US_PER_MS;\n \twhile (wait_time < mbx_time_limit) {\n-\t\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {\n+\t\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed)) {\n \t\t\thns3_err(hw, \"Don't wait for mbx response because of \"\n \t\t\t\t \"disable_cmd\");\n \t\t\treturn -EBUSY;\n@@ -382,7 +382,7 @@\n \trte_spinlock_lock(&hw->cmq.crq.lock);\n \n \twhile (!hns3_cmd_crq_empty(hw)) {\n-\t\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {\n+\t\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed)) {\n \t\t\trte_spinlock_unlock(&hw->cmq.crq.lock);\n \t\t\treturn;\n \t\t}\n@@ -457,7 +457,7 @@\n \t}\n \n \twhile (!hns3_cmd_crq_empty(hw)) {\n-\t\tif (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {\n+\t\tif (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed)) {\n \t\t\trte_spinlock_unlock(&hw->cmq.crq.lock);\n \t\t\treturn;\n \t\t}\ndiff --git a/drivers/net/hns3/hns3_mp.c b/drivers/net/hns3/hns3_mp.c\nindex 556f194..ba8f8ec 100644\n--- a/drivers/net/hns3/hns3_mp.c\n+++ b/drivers/net/hns3/hns3_mp.c\n@@ -151,7 +151,7 @@\n \tint i;\n \n \tif (rte_eal_process_type() == RTE_PROC_SECONDARY ||\n-\t\t__atomic_load_n(&hw->secondary_cnt, __ATOMIC_RELAXED) == 0)\n+\t\trte_atomic_load_explicit(&hw->secondary_cnt, rte_memory_order_relaxed) == 0)\n \t\treturn;\n \n \tif (!mp_req_type_is_valid(type)) {\n@@ -277,7 +277,7 @@ void hns3_mp_req_stop_rxtx(struct rte_eth_dev *dev)\n \t\t\t\t ret);\n \t\t\treturn ret;\n \t\t}\n-\t\t__atomic_fetch_add(&hw->secondary_cnt, 1, __ATOMIC_RELAXED);\n+\t\trte_atomic_fetch_add_explicit(&hw->secondary_cnt, 1, rte_memory_order_relaxed);\n \t} else {\n \t\tret = hns3_mp_init_primary();\n \t\tif (ret) {\n@@ -297,7 +297,7 @@ void hns3_mp_uninit(struct rte_eth_dev *dev)\n \tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\t__atomic_fetch_sub(&hw->secondary_cnt, 1, __ATOMIC_RELAXED);\n+\t\trte_atomic_fetch_sub_explicit(&hw->secondary_cnt, 1, rte_memory_order_relaxed);\n \n \tprocess_data.eth_dev_cnt--;\n \tif (process_data.eth_dev_cnt == 0) {\ndiff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex 7e636a0..73a388b 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -4464,7 +4464,7 @@\n \tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n \n \tif (hns->hw.adapter_state == HNS3_NIC_STARTED &&\n-\t __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) {\n+\t rte_atomic_load_explicit(&hns->hw.reset.resetting, rte_memory_order_relaxed) == 0) {\n \t\teth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);\n \t\teth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status;\n \t\teth_dev->tx_pkt_burst = hw->set_link_down ?\n@@ -4530,7 +4530,7 @@\n \n \trte_spinlock_lock(&hw->lock);\n \n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {\n \t\thns3_err(hw, \"fail to start Rx queue during resetting.\");\n \t\trte_spinlock_unlock(&hw->lock);\n \t\treturn -EIO;\n@@ -4586,7 +4586,7 @@\n \n \trte_spinlock_lock(&hw->lock);\n \n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {\n \t\thns3_err(hw, \"fail to stop Rx queue during resetting.\");\n \t\trte_spinlock_unlock(&hw->lock);\n \t\treturn -EIO;\n@@ -4615,7 +4615,7 @@\n \n \trte_spinlock_lock(&hw->lock);\n \n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {\n \t\thns3_err(hw, \"fail to start Tx queue during resetting.\");\n \t\trte_spinlock_unlock(&hw->lock);\n \t\treturn -EIO;\n@@ -4648,7 +4648,7 @@\n \n \trte_spinlock_lock(&hw->lock);\n \n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {\n \t\thns3_err(hw, \"fail to stop Tx queue during resetting.\");\n \t\trte_spinlock_unlock(&hw->lock);\n \t\treturn -EIO;\ndiff --git a/drivers/net/hns3/hns3_tm.c b/drivers/net/hns3/hns3_tm.c\nindex d969164..92a6685 100644\n--- a/drivers/net/hns3/hns3_tm.c\n+++ b/drivers/net/hns3/hns3_tm.c\n@@ -1051,7 +1051,7 @@\n \tif (error == NULL)\n \t\treturn -EINVAL;\n \n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {\n \t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n \t\terror->message = \"device is resetting\";\n \t\t/* don't goto fail_clear, user may try later */\n@@ -1141,7 +1141,7 @@\n \tif (error == NULL)\n \t\treturn -EINVAL;\n \n-\tif (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {\n+\tif (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {\n \t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n \t\terror->message = \"device is resetting\";\n \t\treturn -EBUSY;\n", "prefixes": [ "v3", "06/45" ] }