Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/137870/?format=api
{ "id": 137870, "url": "http://patches.dpdk.org/api/patches/137870/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240304090136.861-32-shaibran@amazon.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240304090136.861-32-shaibran@amazon.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240304090136.861-32-shaibran@amazon.com", "date": "2024-03-04T09:01:34", "name": "[31/33] net/ena: support max large llq depth from the device", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "df9b4d70baa88ab51e18cf9de32df3a580b9c087", "submitter": { "id": 2930, "url": "http://patches.dpdk.org/api/people/2930/?format=api", "name": "Brandes, Shai", "email": "shaibran@amazon.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240304090136.861-32-shaibran@amazon.com/mbox/", "series": [ { "id": 31356, "url": "http://patches.dpdk.org/api/series/31356/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31356", "date": "2024-03-04T09:01:07", "name": "net/ena: v2.9.0 driver release", "version": 1, "mbox": "http://patches.dpdk.org/series/31356/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137870/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137870/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4368C43B9B;\n\tMon, 4 Mar 2024 10:06:44 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 63DFD42E42;\n\tMon, 4 Mar 2024 10:02:34 +0100 (CET)", "from smtp-fw-80008.amazon.com (smtp-fw-80008.amazon.com\n [99.78.197.219]) by mails.dpdk.org (Postfix) with ESMTP id 0006E42E0E\n for <dev@dpdk.org>; Mon, 4 Mar 2024 10:02:27 +0100 (CET)", "from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO\n smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.25.36.214])\n by smtp-border-fw-80008.pdx80.corp.amazon.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2024 09:02:27 +0000", "from EX19MTAEUB001.ant.amazon.com [10.0.43.254:12602]\n by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.41.19:2525]\n with esmtp (Farcaster)\n id 062f0179-614b-43ce-b99d-5076d122ee8c; Mon, 4 Mar 2024 09:02:26 +0000 (UTC)", "from EX19D007EUA001.ant.amazon.com (10.252.50.133) by\n EX19MTAEUB001.ant.amazon.com (10.252.51.26) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.28; Mon, 4 Mar 2024 09:02:25 +0000", "from EX19MTAUEC001.ant.amazon.com (10.252.135.222) by\n EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.28; Mon, 4 Mar 2024 09:02:25 +0000", "from HFA15-CG15235BS.amazon.com (10.1.212.49) by\n mail-relay.amazon.com (10.252.135.200) with Microsoft SMTP Server id\n 15.2.1258.28 via Frontend Transport; Mon, 4 Mar 2024 09:02:24 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209;\n t=1709542948; x=1741078948;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version;\n bh=tWOlgDV0YhYGZSQXEdxty05V+z6RxDwv9vnnB9hQBTk=;\n b=qLq19r23YP7tLHIUkTlkX1YMl1s9QW9iyMa2uR6SjEKoK/N074/kZ+ak\n XazmTyZ/tTarrbCMKcrOiU+jq7OHYa/G03HfNybQnOKHEHosQ23BtAxJ/\n BqQ+8YKpw3ZBHBkGwz2/15TQXvddzNbYyZM2P6lPNglrlI2yMVw/mvJNA w=;", "X-IronPort-AV": "E=Sophos;i=\"6.06,203,1705363200\"; d=\"scan'208\";a=\"70433980\"", "X-Farcaster-Flow-ID": "062f0179-614b-43ce-b99d-5076d122ee8c", "From": "<shaibran@amazon.com>", "To": "<ferruh.yigit@amd.com>", "CC": "<dev@dpdk.org>, Shai Brandes <shaibran@amazon.com>", "Subject": "[PATCH 31/33] net/ena: support max large llq depth from the device", "Date": "Mon, 4 Mar 2024 11:01:34 +0200", "Message-ID": "<20240304090136.861-32-shaibran@amazon.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240304090136.861-1-shaibran@amazon.com>", "References": "<20240304090136.861-1-shaibran@amazon.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Shai Brandes <shaibran@amazon.com>\n\nSelected AWS instances from later generations enable\nlarge LLQ by default, allowing the transmission of\npackets with headers exceeding 96 bytes.\n\nDue to the overall ENA memory BAR size limitation,\nlarge LLQ has the side effect of halving the maximum\nnumber of LLQ entries (from 1024 to 512).\n\nENA-Express, powered by AWS Scalable Reliable Datagram\n(SRD) technology, requires Tx queue with 1024 entries.\nSelected AWS instances from upcoming generations will\nhave double the size of the ENA memory BAR, enabling ENA-Express\nto work with a large LLQ of 1024 entries.\n\nThe initial default large LLQ size will remain 512.\n\nSigned-off-by: Shai Brandes <shaibran@amazon.com>\nReviewed-by: Amit Bernstein <amitbern@amazon.com>\n---\n doc/guides/rel_notes/release_24_03.rst | 2 +\n drivers/net/ena/ena_ethdev.c | 38 ++++++++++++-------\n drivers/net/ena/hal/ena_defs/ena_admin_defs.h | 4 +-\n 3 files changed, 29 insertions(+), 15 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 2a22bb07ed..9823616eeb 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -107,6 +107,8 @@ New Features\n * Added support for sub-optimal configuration notifications from the device.\n * Restructured fast release of mbufs when RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE optimization is enabled.\n * Replaced `enable_llq` and `large_llq_hdr` devargs with a new devarg `llq_policy`.\n+ * Added support for LLQ header size recommendation from the device.\n+ * Allowed large LLQ with 1024 entries when the device supports enlarged memory BAR.\n \n * **Updated Atomic Rules' Arkville driver.**\n \ndiff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex d73e321d0f..43693ee2ee 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -42,6 +42,8 @@\n \n #define DECIMAL_BASE 10\n \n+#define MAX_WIDE_LLQ_DEPTH_UNSUPPORTED 0\n+\n /*\n * We should try to keep ENA_CLEANUP_BUF_SIZE lower than\n * RTE_MEMPOOL_CACHE_MAX_SIZE, so we can fit this in mempool local cache.\n@@ -1071,7 +1073,7 @@ static int\n ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,\n \t\t bool use_large_llq_hdr)\n {\n-\tstruct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;\n+\tstruct ena_admin_feature_llq_desc *dev = &ctx->get_feat_ctx->llq;\n \tstruct ena_com_dev *ena_dev = ctx->ena_dev;\n \tuint32_t max_tx_queue_size;\n \tuint32_t max_rx_queue_size;\n@@ -1086,7 +1088,7 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,\n \t\tif (ena_dev->tx_mem_queue_type ==\n \t\t ENA_ADMIN_PLACEMENT_POLICY_DEV) {\n \t\t\tmax_tx_queue_size = RTE_MIN(max_tx_queue_size,\n-\t\t\t\tllq->max_llq_depth);\n+\t\t\t\tdev->max_llq_depth);\n \t\t} else {\n \t\t\tmax_tx_queue_size = RTE_MIN(max_tx_queue_size,\n \t\t\t\tmax_queue_ext->max_tx_sq_depth);\n@@ -1106,7 +1108,7 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,\n \t\tif (ena_dev->tx_mem_queue_type ==\n \t\t ENA_ADMIN_PLACEMENT_POLICY_DEV) {\n \t\t\tmax_tx_queue_size = RTE_MIN(max_tx_queue_size,\n-\t\t\t\tllq->max_llq_depth);\n+\t\t\t\tdev->max_llq_depth);\n \t\t} else {\n \t\t\tmax_tx_queue_size = RTE_MIN(max_tx_queue_size,\n \t\t\t\tmax_queues->max_sq_depth);\n@@ -1122,18 +1124,28 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,\n \tmax_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);\n \tmax_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);\n \n-\tif (use_large_llq_hdr) {\n-\t\tif ((llq->entry_size_ctrl_supported &\n-\t\t ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&\n-\t\t (ena_dev->tx_mem_queue_type ==\n-\t\t ENA_ADMIN_PLACEMENT_POLICY_DEV)) {\n-\t\t\tmax_tx_queue_size /= 2;\n-\t\t\tPMD_INIT_LOG(INFO,\n-\t\t\t\t\"Forcing large headers and decreasing maximum Tx queue size to %d\\n\",\n+\tif (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && use_large_llq_hdr) {\n+\t\t/* intersection between driver configuration and device capabilities */\n+\t\tif (dev->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {\n+\t\t\tif (dev->max_wide_llq_depth == MAX_WIDE_LLQ_DEPTH_UNSUPPORTED) {\n+\t\t\t\t/* Devices that do not support the double-sized ENA memory BAR will\n+\t\t\t\t * report max_wide_llq_depth as 0. In such case, driver halves the\n+\t\t\t\t * queue depth when working in large llq policy.\n+\t\t\t\t */\n+\t\t\t\tmax_tx_queue_size >>= 1;\n+\t\t\t\tPMD_INIT_LOG(INFO,\n+\t\t\t\t\t\"large LLQ policy requires limiting Tx queue size to %u entries\\n\",\n \t\t\t\tmax_tx_queue_size);\n+\t\t\t} else if (dev->max_wide_llq_depth < max_tx_queue_size) {\n+\t\t\t\t/* In case the queue depth that the driver calculated exceeds\n+\t\t\t\t * the maximal value that the device allows, it will be limited\n+\t\t\t\t * to that maximal value\n+\t\t\t\t */\n+\t\t\t\tmax_tx_queue_size = dev->max_wide_llq_depth;\n+\t\t\t}\n \t\t} else {\n-\t\t\tPMD_INIT_LOG(ERR,\n-\t\t\t\t\"Forcing large headers failed: LLQ is disabled or device does not support large headers\\n\");\n+\t\t\tPMD_INIT_LOG(INFO,\n+\t\t\t\t\"Forcing large LLQ headers failed since device lacks this support\\n\");\n \t\t}\n \t}\n \ndiff --git a/drivers/net/ena/hal/ena_defs/ena_admin_defs.h b/drivers/net/ena/hal/ena_defs/ena_admin_defs.h\nindex 2adce75ed3..cff6451c96 100644\n--- a/drivers/net/ena/hal/ena_defs/ena_admin_defs.h\n+++ b/drivers/net/ena/hal/ena_defs/ena_admin_defs.h\n@@ -696,8 +696,8 @@ struct ena_admin_feature_llq_desc {\n \t */\n \tuint8_t entry_size_recommended;\n \n-\t/* reserved */\n-\tuint8_t reserved1[2];\n+\t/* max depth of wide llq, or 0 for N/A */\n+\tuint16_t max_wide_llq_depth;\n \n \t/* accelerated low latency queues requirement. driver needs to\n \t * support those requirements in order to use accelerated llq\n", "prefixes": [ "31/33" ] }