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GET /api/patches/137853/?format=api
{ "id": 137853, "url": "http://patches.dpdk.org/api/patches/137853/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240304090136.861-13-shaibran@amazon.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240304090136.861-13-shaibran@amazon.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240304090136.861-13-shaibran@amazon.com", "date": "2024-03-04T09:01:15", "name": "[12/33] net/ena/hal: rename fields in completion descriptors", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "39c20667ee5620c586ce9fad0582ab3bef00141e", "submitter": { "id": 2930, "url": "http://patches.dpdk.org/api/people/2930/?format=api", "name": "Brandes, Shai", "email": "shaibran@amazon.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240304090136.861-13-shaibran@amazon.com/mbox/", "series": [ { "id": 31356, "url": "http://patches.dpdk.org/api/series/31356/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31356", "date": "2024-03-04T09:01:07", "name": "net/ena: v2.9.0 driver release", "version": 1, "mbox": "http://patches.dpdk.org/series/31356/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137853/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137853/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 65F3543B9B;\n\tMon, 4 Mar 2024 10:03:54 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6FE6E40EE1;\n\tMon, 4 Mar 2024 10:02:10 +0100 (CET)", "from smtp-fw-2101.amazon.com (smtp-fw-2101.amazon.com\n [72.21.196.25])\n by mails.dpdk.org (Postfix) with ESMTP id 721FF40A7A\n for <dev@dpdk.org>; Mon, 4 Mar 2024 10:02:01 +0100 (CET)", "from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO\n smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.43.8.6])\n by smtp-border-fw-2101.iad2.amazon.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2024 09:01:59 +0000", "from EX19MTAEUB001.ant.amazon.com [10.0.43.254:43533]\n by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.16.96:2525]\n with esmtp (Farcaster)\n id 75048482-0f7e-45f7-9923-95643ce7614f; Mon, 4 Mar 2024 09:01:58 +0000 (UTC)", "from EX19D007EUA002.ant.amazon.com (10.252.50.68) by\n EX19MTAEUB001.ant.amazon.com (10.252.51.26) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.28; Mon, 4 Mar 2024 09:01:58 +0000", "from EX19MTAUEC001.ant.amazon.com (10.252.135.222) by\n EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.28; Mon, 4 Mar 2024 09:01:57 +0000", "from HFA15-CG15235BS.amazon.com (10.1.212.49) by\n mail-relay.amazon.com (10.252.135.200) with Microsoft SMTP Server id\n 15.2.1258.28 via Frontend Transport; Mon, 4 Mar 2024 09:01:56 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209;\n t=1709542921; x=1741078921;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version;\n bh=wwbSIexFtHbaJk0TowRcxhCLpA4fyiMDrVsWrK5MRis=;\n b=BrfrIt7ZXFBCCBJftM4OfFwvVrFcnBHFprRpfy6JK5Rkyi2Ve1MRSSka\n SbzV341R0rJJI9JAkN8Nns8YLq/9H0g5tupORbpSRk4Di705WQUc10GLT\n JgaD+3q2A6172q+vhqo08jSk43oEdICAz6/Y1dvCndsAoXRkm2W6l7IHX U=;", "X-IronPort-AV": "E=Sophos;i=\"6.06,203,1705363200\"; d=\"scan'208\";a=\"385227026\"", "X-Farcaster-Flow-ID": "75048482-0f7e-45f7-9923-95643ce7614f", "From": "<shaibran@amazon.com>", "To": "<ferruh.yigit@amd.com>", "CC": "<dev@dpdk.org>, Shai Brandes <shaibran@amazon.com>", "Subject": "[PATCH 12/33] net/ena/hal: rename fields in completion descriptors", "Date": "Mon, 4 Mar 2024 11:01:15 +0200", "Message-ID": "<20240304090136.861-13-shaibran@amazon.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240304090136.861-1-shaibran@amazon.com>", "References": "<20240304090136.861-1-shaibran@amazon.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Shai Brandes <shaibran@amazon.com>\n\nSeveral reserved bits in ena_eth_io_tx_cdesc and\nena_eth_io_rx_cdesc_base have been renamed explicitly to\nMBZ (Must Be Zero).\nThese bits are set by the device to zero before being sent\nto the driver. The fields are used as an integrity check in\norder to ensure that the received descriptor is not corrupted.\n\nSigned-off-by: Shai Brandes <shaibran@amazon.com>\nReviewed-by: Amit Bernstein <amitbern@amazon.com>\n---\n drivers/net/ena/hal/ena_defs/ena_admin_defs.h | 1 +\n .../net/ena/hal/ena_defs/ena_eth_io_defs.h | 49 +++++++++++++++++--\n 2 files changed, 47 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/ena/hal/ena_defs/ena_admin_defs.h b/drivers/net/ena/hal/ena_defs/ena_admin_defs.h\nindex 670e794c98..438e4a1085 100644\n--- a/drivers/net/ena/hal/ena_defs/ena_admin_defs.h\n+++ b/drivers/net/ena/hal/ena_defs/ena_admin_defs.h\n@@ -84,6 +84,7 @@ enum ena_admin_aq_caps_id {\n \tENA_ADMIN_ENA_SRD_INFO = 1,\n \tENA_ADMIN_CUSTOMER_METRICS = 2,\n \tENA_ADMIN_EXTENDED_RESET_REASONS\t = 3,\n+\tENA_ADMIN_CDESC_MBZ = 4,\n };\n \n enum ena_admin_placement_policy_type {\ndiff --git a/drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h b/drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h\nindex 2107d17fdf..f811dd261e 100644\n--- a/drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h\n+++ b/drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h\n@@ -152,7 +152,8 @@ struct ena_eth_io_tx_cdesc {\n \n \t/* flags\n \t * 0 : phase\n-\t * 7:1 : reserved1\n+\t * 5:1 : reserved1\n+\t * 7:6 : mbz6 - MBZ\n \t */\n \tuint8_t flags;\n \n@@ -198,7 +199,7 @@ struct ena_eth_io_rx_desc {\n struct ena_eth_io_rx_cdesc_base {\n \t/* 4:0 : l3_proto_idx\n \t * 6:5 : src_vlan_cnt\n-\t * 7 : reserved7 - MBZ\n+\t * 7 : mbz7 - MBZ\n \t * 12:8 : l4_proto_idx\n \t * 13 : l3_csum_err - when set, either the L3\n \t * checksum error detected, or, the controller didn't\n@@ -214,7 +215,8 @@ struct ena_eth_io_rx_cdesc_base {\n \t * 16 : l4_csum_checked - L4 checksum was verified\n \t * (could be OK or error), when cleared the status of\n \t * checksum is unknown\n-\t * 23:17 : reserved17 - MBZ\n+\t * 17 : mbz17 - MBZ\n+\t * 23:18 : reserved18\n \t * 24 : phase\n \t * 25 : l3_csum2 - second checksum engine result\n \t * 26 : first - Indicates first descriptor in\n@@ -341,6 +343,8 @@ struct ena_eth_io_numa_node_cfg_reg {\n \n /* tx_cdesc */\n #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)\n+#define ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT 6\n+#define ENA_ETH_IO_TX_CDESC_MBZ6_MASK GENMASK(7, 6)\n \n /* rx_desc */\n #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)\n@@ -355,6 +359,8 @@ struct ena_eth_io_numa_node_cfg_reg {\n #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)\n #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5\n #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)\n+#define ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT 7\n+#define ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK BIT(7)\n #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8\n #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)\n #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13\n@@ -365,6 +371,8 @@ struct ena_eth_io_numa_node_cfg_reg {\n #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)\n #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16\n #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)\n+#define ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT 17\n+#define ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK BIT(17)\n #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24\n #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)\n #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25\n@@ -731,6 +739,15 @@ static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p,\n \tp->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK;\n }\n \n+static inline uint8_t get_ena_eth_io_tx_cdesc_mbz6(const struct ena_eth_io_tx_cdesc *p)\n+{\n+\treturn (p->flags & ENA_ETH_IO_TX_CDESC_MBZ6_MASK) >> ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT;\n+}\n+static inline void set_ena_eth_io_tx_cdesc_mbz6(struct ena_eth_io_tx_cdesc *p, uint8_t val)\n+{\n+\tp->flags |= (val << ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT) & ENA_ETH_IO_TX_CDESC_MBZ6_MASK;\n+}\n+\n static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p)\n {\n \treturn p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK;\n@@ -791,6 +808,19 @@ static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_r\n \tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;\n }\n \n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_mbz7(const struct ena_eth_io_rx_cdesc_base *p)\n+{\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK) >>\n+\t\tENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT;\n+}\n+\n+static inline void set_ena_eth_io_rx_cdesc_base_mbz7(struct ena_eth_io_rx_cdesc_base *p,\n+\t\t\t\t\t\t\t uint32_t val)\n+{\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT) &\n+\t\t ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK;\n+}\n+\n static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)\n {\n \treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;\n@@ -841,6 +871,19 @@ static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_i\n \tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK;\n }\n \n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_mbz17(const struct ena_eth_io_rx_cdesc_base *p)\n+{\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK) >>\n+\t\tENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT;\n+}\n+\n+static inline void set_ena_eth_io_rx_cdesc_base_mbz17(struct ena_eth_io_rx_cdesc_base *p,\n+\t\t\t\t\t\t\t\tuint32_t val)\n+{\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT) &\n+\t\t ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK;\n+}\n+\n static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p)\n {\n \treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;\n", "prefixes": [ "12/33" ] }