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GET /api/patches/137816/?format=api
{ "id": 137816, "url": "http://patches.dpdk.org/api/patches/137816/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240303173833.100039-3-hkalra@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240303173833.100039-3-hkalra@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240303173833.100039-3-hkalra@marvell.com", "date": "2024-03-03T17:38:12", "name": "[v6,02/23] net/cnxk: implementing eswitch device", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "53c090e14764810918fb227402ce3fc99ba3e8bb", "submitter": { "id": 1182, "url": "http://patches.dpdk.org/api/people/1182/?format=api", "name": "Harman Kalra", "email": "hkalra@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240303173833.100039-3-hkalra@marvell.com/mbox/", "series": [ { "id": 31353, "url": "http://patches.dpdk.org/api/series/31353/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31353", "date": "2024-03-03T17:38:10", "name": "net/cnxk: support for port representors", "version": 6, "mbox": "http://patches.dpdk.org/series/31353/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137816/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137816/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8F2C943C3E;\n\tSun, 3 Mar 2024 18:38:57 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2106242E76;\n\tSun, 3 Mar 2024 18:38:49 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 497AE42EEC\n for <dev@dpdk.org>; Sun, 3 Mar 2024 18:38:47 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 423DOJuL029127; Sun, 3 Mar 2024 09:38:46 -0800", "from dc6wp-exch02.marvell.com ([4.21.29.225])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wm2bptrsf-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Sun, 03 Mar 2024 09:38:45 -0800 (PST)", "from DC6WP-EXCH02.marvell.com (10.76.176.209) by\n DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.12; Sun, 3 Mar 2024 09:38:44 -0800", "from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com\n (10.76.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend\n Transport; Sun, 3 Mar 2024 09:38:44 -0800", "from localhost.localdomain (unknown [10.29.52.211])\n by maili.marvell.com (Postfix) with ESMTP id 871853F718E;\n Sun, 3 Mar 2024 09:38:41 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-type; s=pfpt0220; bh=J7D99jccCtAsGteMD0/hI\n CDxtTl8Q+BaIgD26YnNFhY=; b=WHgglOuK9elii7YQ/QdspIvfV+//TpEVdioFA\n mEQYCtbbchzPWfeNUAeQ6T3qJZdrMXFU2rhR9YG/HMpqlWoUDU+HcMuBWlsQbBEf\n WlB8F9Ay4fvo89WjYcie/dtIMXM+Nl5pxGAxjQOjduT7i8g5hOihCBSPVVNnc12X\n pW5OaIAKGCuBx4G4sBP3wQGNZ06UeQjQwOcYG6/lolO55wCw6Di+cLKv/p6+z3lA\n mN6PS6xHctHdWa07wfiV71L/lQNTFFIG4qdvHzh95nCkphoWyRDx+9E/gfNSwHea\n DI71BxJXS5pEYufPeryR5GwI6qcV60ZMVJIo4aB78+vfsWCcw==", "From": "Harman Kalra <hkalra@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Harman Kalra <hkalra@marvell.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v6 02/23] net/cnxk: implementing eswitch device", "Date": "Sun, 3 Mar 2024 23:08:12 +0530", "Message-ID": "<20240303173833.100039-3-hkalra@marvell.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<20240303173833.100039-1-hkalra@marvell.com>", "References": "<20230811163419.165790-1-hkalra@marvell.com>\n <20240303173833.100039-1-hkalra@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "CHyA-OCfBoyAoirFZoMx3JnKtlGmTv93", "X-Proofpoint-ORIG-GUID": "CHyA-OCfBoyAoirFZoMx3JnKtlGmTv93", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-03-03_08,2024-03-01_03,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Eswitch device is a parent or base device behind all the representors,\nacting as transport layer between representors and representees\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/net/cnxk/cnxk_eswitch.c | 379 ++++++++++++++++++++++++++++++++\n drivers/net/cnxk/cnxk_eswitch.h | 103 +++++++++\n drivers/net/cnxk/meson.build | 1 +\n 3 files changed, 483 insertions(+)\n create mode 100644 drivers/net/cnxk/cnxk_eswitch.c\n create mode 100644 drivers/net/cnxk/cnxk_eswitch.h", "diff": "diff --git a/drivers/net/cnxk/cnxk_eswitch.c b/drivers/net/cnxk/cnxk_eswitch.c\nnew file mode 100644\nindex 0000000000..8f216d7c88\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_eswitch.c\n@@ -0,0 +1,379 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2024 Marvell.\n+ */\n+\n+#include <cnxk_eswitch.h>\n+\n+#define CNXK_NIX_DEF_SQ_COUNT 512\n+\n+static int\n+cnxk_eswitch_dev_remove(struct rte_pci_device *pci_dev)\n+{\n+\tstruct cnxk_eswitch_dev *eswitch_dev;\n+\tint rc = 0;\n+\n+\tPLT_SET_USED(pci_dev);\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\teswitch_dev = cnxk_eswitch_pmd_priv();\n+\tif (!eswitch_dev) {\n+\t\trc = -EINVAL;\n+\t\tgoto exit;\n+\t}\n+\n+\trte_free(eswitch_dev);\n+exit:\n+\treturn rc;\n+}\n+\n+int\n+cnxk_eswitch_nix_rsrc_start(struct cnxk_eswitch_dev *eswitch_dev)\n+{\n+\tint rc;\n+\n+\t/* Enable Rx in NPC */\n+\trc = roc_nix_npc_rx_ena_dis(&eswitch_dev->nix, true);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to enable NPC rx %d\", rc);\n+\t\tgoto done;\n+\t}\n+\n+\trc = roc_npc_mcam_enable_all_entries(&eswitch_dev->npc, 1);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to enable NPC entries %d\", rc);\n+\t\tgoto done;\n+\t}\n+\n+done:\n+\treturn 0;\n+}\n+\n+int\n+cnxk_eswitch_txq_start(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid)\n+{\n+\tstruct roc_nix_sq *sq = &eswitch_dev->txq[qid].sqs;\n+\tint rc = -EINVAL;\n+\n+\tif (eswitch_dev->txq[qid].state == CNXK_ESWITCH_QUEUE_STATE_STARTED)\n+\t\treturn 0;\n+\n+\tif (eswitch_dev->txq[qid].state != CNXK_ESWITCH_QUEUE_STATE_CONFIGURED) {\n+\t\tplt_err(\"Eswitch txq %d not configured yet\", qid);\n+\t\tgoto done;\n+\t}\n+\n+\trc = roc_nix_sq_ena_dis(sq, true);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to enable sq aura fc, txq=%u, rc=%d\", qid, rc);\n+\t\tgoto done;\n+\t}\n+\n+\teswitch_dev->txq[qid].state = CNXK_ESWITCH_QUEUE_STATE_STARTED;\n+done:\n+\treturn rc;\n+}\n+\n+int\n+cnxk_eswitch_txq_stop(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid)\n+{\n+\tstruct roc_nix_sq *sq = &eswitch_dev->txq[qid].sqs;\n+\tint rc = -EINVAL;\n+\n+\tif (eswitch_dev->txq[qid].state == CNXK_ESWITCH_QUEUE_STATE_STOPPED ||\n+\t eswitch_dev->txq[qid].state == CNXK_ESWITCH_QUEUE_STATE_RELEASED)\n+\t\treturn 0;\n+\n+\tif (eswitch_dev->txq[qid].state != CNXK_ESWITCH_QUEUE_STATE_STARTED) {\n+\t\tplt_err(\"Eswitch txq %d not started\", qid);\n+\t\tgoto done;\n+\t}\n+\n+\trc = roc_nix_sq_ena_dis(sq, false);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to disable sqb aura fc, txq=%u, rc=%d\", qid, rc);\n+\t\tgoto done;\n+\t}\n+\n+\teswitch_dev->txq[qid].state = CNXK_ESWITCH_QUEUE_STATE_STOPPED;\n+done:\n+\treturn rc;\n+}\n+\n+int\n+cnxk_eswitch_rxq_start(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid)\n+{\n+\tstruct roc_nix_rq *rq = &eswitch_dev->rxq[qid].rqs;\n+\tint rc = -EINVAL;\n+\n+\tif (eswitch_dev->rxq[qid].state == CNXK_ESWITCH_QUEUE_STATE_STARTED)\n+\t\treturn 0;\n+\n+\tif (eswitch_dev->rxq[qid].state != CNXK_ESWITCH_QUEUE_STATE_CONFIGURED) {\n+\t\tplt_err(\"Eswitch rxq %d not configured yet\", qid);\n+\t\tgoto done;\n+\t}\n+\n+\trc = roc_nix_rq_ena_dis(rq, true);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to enable rxq=%u, rc=%d\", qid, rc);\n+\t\tgoto done;\n+\t}\n+\n+\teswitch_dev->rxq[qid].state = CNXK_ESWITCH_QUEUE_STATE_STARTED;\n+done:\n+\treturn rc;\n+}\n+\n+int\n+cnxk_eswitch_rxq_stop(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid)\n+{\n+\tstruct roc_nix_rq *rq = &eswitch_dev->rxq[qid].rqs;\n+\tint rc = -EINVAL;\n+\n+\tif (eswitch_dev->rxq[qid].state == CNXK_ESWITCH_QUEUE_STATE_STOPPED ||\n+\t eswitch_dev->rxq[qid].state == CNXK_ESWITCH_QUEUE_STATE_RELEASED)\n+\t\treturn 0;\n+\n+\tif (eswitch_dev->rxq[qid].state != CNXK_ESWITCH_QUEUE_STATE_STARTED) {\n+\t\tplt_err(\"Eswitch rxq %d not started\", qid);\n+\t\tgoto done;\n+\t}\n+\n+\trc = roc_nix_rq_ena_dis(rq, false);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to disable rxq=%u, rc=%d\", qid, rc);\n+\t\tgoto done;\n+\t}\n+\n+\teswitch_dev->rxq[qid].state = CNXK_ESWITCH_QUEUE_STATE_STOPPED;\n+done:\n+\treturn rc;\n+}\n+\n+int\n+cnxk_eswitch_rxq_release(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid)\n+{\n+\tstruct roc_nix_rq *rq;\n+\tstruct roc_nix_cq *cq;\n+\tint rc;\n+\n+\tif (eswitch_dev->rxq[qid].state == CNXK_ESWITCH_QUEUE_STATE_RELEASED)\n+\t\treturn 0;\n+\n+\t/* Cleanup ROC SQ */\n+\trq = &eswitch_dev->rxq[qid].rqs;\n+\trc = roc_nix_rq_fini(rq);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to cleanup sq, rc=%d\", rc);\n+\t\tgoto fail;\n+\t}\n+\n+\teswitch_dev->rxq[qid].state = CNXK_ESWITCH_QUEUE_STATE_RELEASED;\n+\n+\t/* Cleanup ROC CQ */\n+\tcq = &eswitch_dev->cxq[qid].cqs;\n+\trc = roc_nix_cq_fini(cq);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to cleanup cq, rc=%d\", rc);\n+\t\tgoto fail;\n+\t}\n+\n+\teswitch_dev->cxq[qid].state = CNXK_ESWITCH_QUEUE_STATE_RELEASED;\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+cnxk_eswitch_rxq_setup(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid, uint16_t nb_desc,\n+\t\t const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp)\n+{\n+\tstruct roc_nix *nix = &eswitch_dev->nix;\n+\tstruct rte_mempool *lpb_pool = mp;\n+\tstruct rte_mempool_ops *ops;\n+\tconst char *platform_ops;\n+\tstruct roc_nix_rq *rq;\n+\tstruct roc_nix_cq *cq;\n+\tuint16_t first_skip;\n+\tint rc = -EINVAL;\n+\n+\tif (eswitch_dev->rxq[qid].state != CNXK_ESWITCH_QUEUE_STATE_RELEASED ||\n+\t eswitch_dev->cxq[qid].state != CNXK_ESWITCH_QUEUE_STATE_RELEASED) {\n+\t\tplt_err(\"Queue %d is in invalid state %d, cannot be setup\", qid,\n+\t\t\teswitch_dev->txq[qid].state);\n+\t\tgoto fail;\n+\t}\n+\n+\tRTE_SET_USED(rx_conf);\n+\tplatform_ops = rte_mbuf_platform_mempool_ops();\n+\t/* This driver needs cnxk_npa mempool ops to work */\n+\tops = rte_mempool_get_ops(lpb_pool->ops_index);\n+\tif (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {\n+\t\tplt_err(\"mempool ops should be of cnxk_npa type\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (lpb_pool->pool_id == 0) {\n+\t\tplt_err(\"Invalid pool_id\");\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Setup ROC CQ */\n+\tcq = &eswitch_dev->cxq[qid].cqs;\n+\tmemset(cq, 0, sizeof(struct roc_nix_cq));\n+\tcq->qid = qid;\n+\tcq->nb_desc = nb_desc;\n+\trc = roc_nix_cq_init(nix, cq);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init roc cq for rq=%d, rc=%d\", qid, rc);\n+\t\tgoto fail;\n+\t}\n+\teswitch_dev->cxq[qid].state = CNXK_ESWITCH_QUEUE_STATE_CONFIGURED;\n+\n+\t/* Setup ROC RQ */\n+\trq = &eswitch_dev->rxq[qid].rqs;\n+\tmemset(rq, 0, sizeof(struct roc_nix_rq));\n+\trq->qid = qid;\n+\trq->cqid = cq->qid;\n+\trq->aura_handle = lpb_pool->pool_id;\n+\trq->flow_tag_width = 32;\n+\trq->sso_ena = false;\n+\n+\t/* Calculate first mbuf skip */\n+\tfirst_skip = (sizeof(struct rte_mbuf));\n+\tfirst_skip += RTE_PKTMBUF_HEADROOM;\n+\tfirst_skip += rte_pktmbuf_priv_size(lpb_pool);\n+\trq->first_skip = first_skip;\n+\trq->later_skip = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(lpb_pool);\n+\trq->lpb_size = lpb_pool->elt_size;\n+\tif (roc_errata_nix_no_meta_aura())\n+\t\trq->lpb_drop_ena = true;\n+\n+\trc = roc_nix_rq_init(nix, rq, true);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init roc rq for rq=%d, rc=%d\", qid, rc);\n+\t\tgoto cq_fini;\n+\t}\n+\teswitch_dev->rxq[qid].state = CNXK_ESWITCH_QUEUE_STATE_CONFIGURED;\n+\n+\treturn 0;\n+cq_fini:\n+\trc |= roc_nix_cq_fini(cq);\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+cnxk_eswitch_txq_release(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid)\n+{\n+\tstruct roc_nix_sq *sq;\n+\tint rc = 0;\n+\n+\tif (eswitch_dev->txq[qid].state == CNXK_ESWITCH_QUEUE_STATE_RELEASED)\n+\t\treturn 0;\n+\n+\t/* Cleanup ROC SQ */\n+\tsq = &eswitch_dev->txq[qid].sqs;\n+\trc = roc_nix_sq_fini(sq);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to cleanup sq, rc=%d\", rc);\n+\t\tgoto fail;\n+\t}\n+\n+\teswitch_dev->txq[qid].state = CNXK_ESWITCH_QUEUE_STATE_RELEASED;\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+cnxk_eswitch_txq_setup(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid, uint16_t nb_desc,\n+\t\t const struct rte_eth_txconf *tx_conf)\n+{\n+\tstruct roc_nix_sq *sq;\n+\tint rc = 0;\n+\n+\tif (eswitch_dev->txq[qid].state != CNXK_ESWITCH_QUEUE_STATE_RELEASED) {\n+\t\tplt_err(\"Queue %d is in invalid state %d, cannot be setup\", qid,\n+\t\t\teswitch_dev->txq[qid].state);\n+\t\trc = -EINVAL;\n+\t\tgoto fail;\n+\t}\n+\tRTE_SET_USED(tx_conf);\n+\t/* Setup ROC SQ */\n+\tsq = &eswitch_dev->txq[qid].sqs;\n+\tmemset(sq, 0, sizeof(struct roc_nix_sq));\n+\tsq->qid = qid;\n+\tsq->nb_desc = nb_desc;\n+\tsq->max_sqe_sz = NIX_MAXSQESZ_W8;\n+\tif (sq->nb_desc >= CNXK_NIX_DEF_SQ_COUNT)\n+\t\tsq->fc_hyst_bits = 0x1;\n+\n+\trc = roc_nix_sq_init(&eswitch_dev->nix, sq);\n+\tif (rc)\n+\t\tplt_err(\"Failed to init sq=%d, rc=%d\", qid, rc);\n+\n+\teswitch_dev->txq[qid].state = CNXK_ESWITCH_QUEUE_STATE_CONFIGURED;\n+\n+fail:\n+\treturn rc;\n+}\n+\n+static int\n+cnxk_eswitch_dev_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n+{\n+\tstruct cnxk_eswitch_dev *eswitch_dev;\n+\tconst struct rte_memzone *mz = NULL;\n+\tint rc = -ENOMEM;\n+\n+\tRTE_SET_USED(pci_drv);\n+\n+\teswitch_dev = cnxk_eswitch_pmd_priv();\n+\tif (!eswitch_dev) {\n+\t\trc = roc_plt_init();\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to initialize platform model, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\t\treturn 0;\n+\n+\t\tmz = rte_memzone_reserve_aligned(CNXK_REP_ESWITCH_DEV_MZ, sizeof(*eswitch_dev),\n+\t\t\t\t\t\t SOCKET_ID_ANY, 0, RTE_CACHE_LINE_SIZE);\n+\t\tif (mz == NULL) {\n+\t\t\tplt_err(\"Failed to reserve a memzone\");\n+\t\t\tgoto fail;\n+\t\t}\n+\n+\t\teswitch_dev = mz->addr;\n+\t\teswitch_dev->pci_dev = pci_dev;\n+\t}\n+\n+\t/* Spinlock for synchronization between representors traffic and control\n+\t * messages\n+\t */\n+\trte_spinlock_init(&eswitch_dev->rep_lock);\n+\n+\treturn rc;\n+fail:\n+\treturn rc;\n+}\n+\n+static const struct rte_pci_id cnxk_eswitch_pci_map[] = {\n+\t{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_RVU_ESWITCH_PF)},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static struct rte_pci_driver cnxk_eswitch_pci = {\n+\t.id_table = cnxk_eswitch_pci_map,\n+\t.drv_flags =\n+\t\tRTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA | RTE_PCI_DRV_PROBE_AGAIN,\n+\t.probe = cnxk_eswitch_dev_probe,\n+\t.remove = cnxk_eswitch_dev_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(cnxk_eswitch, cnxk_eswitch_pci);\n+RTE_PMD_REGISTER_PCI_TABLE(cnxk_eswitch, cnxk_eswitch_pci_map);\n+RTE_PMD_REGISTER_KMOD_DEP(cnxk_eswitch, \"vfio-pci\");\ndiff --git a/drivers/net/cnxk/cnxk_eswitch.h b/drivers/net/cnxk/cnxk_eswitch.h\nnew file mode 100644\nindex 0000000000..d1b4fa8761\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_eswitch.h\n@@ -0,0 +1,103 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2024 Marvell.\n+ */\n+\n+#ifndef __CNXK_ESWITCH_H__\n+#define __CNXK_ESWITCH_H__\n+\n+#include <sys/socket.h>\n+#include <sys/un.h>\n+\n+#include <cnxk_ethdev.h>\n+\n+#include \"cn10k_tx.h\"\n+\n+#define CNXK_ESWITCH_CTRL_MSG_SOCK_PATH \"/tmp/cxk_rep_ctrl_msg_sock\"\n+#define CNXK_REP_ESWITCH_DEV_MZ\t\t\"cnxk_eswitch_dev\"\n+#define CNXK_ESWITCH_VLAN_TPID\t\t0x8100\n+#define CNXK_ESWITCH_MAX_TXQ\t\t256\n+#define CNXK_ESWITCH_MAX_RXQ\t\t256\n+#define CNXK_ESWITCH_LBK_CHAN\t\t63\n+#define CNXK_ESWITCH_VFPF_SHIFT\t\t8\n+\n+#define CNXK_ESWITCH_QUEUE_STATE_RELEASED 0\n+#define CNXK_ESWITCH_QUEUE_STATE_CONFIGURED 1\n+#define CNXK_ESWITCH_QUEUE_STATE_STARTED 2\n+#define CNXK_ESWITCH_QUEUE_STATE_STOPPED 3\n+\n+struct cnxk_rep_info {\n+\tstruct rte_eth_dev *rep_eth_dev;\n+};\n+\n+struct cnxk_eswitch_txq {\n+\tstruct roc_nix_sq sqs;\n+\tuint8_t state;\n+};\n+\n+struct cnxk_eswitch_rxq {\n+\tstruct roc_nix_rq rqs;\n+\tuint8_t state;\n+};\n+\n+struct cnxk_eswitch_cxq {\n+\tstruct roc_nix_cq cqs;\n+\tuint8_t state;\n+};\n+\n+TAILQ_HEAD(eswitch_flow_list, roc_npc_flow);\n+struct cnxk_eswitch_dev {\n+\t/* Input parameters */\n+\tstruct plt_pci_device *pci_dev;\n+\t/* ROC NIX */\n+\tstruct roc_nix nix;\n+\n+\t/* ROC NPC */\n+\tstruct roc_npc npc;\n+\n+\t/* ROC NPA */\n+\tstruct rte_mempool *ctrl_chan_pool;\n+\tconst struct plt_memzone *pktmem_mz;\n+\tuint64_t pkt_aura;\n+\n+\t/* Eswitch RQs, SQs and CQs */\n+\tstruct cnxk_eswitch_txq *txq;\n+\tstruct cnxk_eswitch_rxq *rxq;\n+\tstruct cnxk_eswitch_cxq *cxq;\n+\n+\t/* Configured queue count */\n+\tuint16_t nb_rxq;\n+\tuint16_t nb_txq;\n+\tuint16_t rep_cnt;\n+\tuint8_t configured;\n+\n+\t/* Port representor fields */\n+\trte_spinlock_t rep_lock;\n+\tuint16_t switch_domain_id;\n+\tuint16_t eswitch_vdev;\n+\tstruct cnxk_rep_info *rep_info;\n+};\n+\n+static inline struct cnxk_eswitch_dev *\n+cnxk_eswitch_pmd_priv(void)\n+{\n+\tconst struct rte_memzone *mz;\n+\n+\tmz = rte_memzone_lookup(CNXK_REP_ESWITCH_DEV_MZ);\n+\tif (!mz)\n+\t\treturn NULL;\n+\n+\treturn mz->addr;\n+}\n+\n+int cnxk_eswitch_nix_rsrc_start(struct cnxk_eswitch_dev *eswitch_dev);\n+int cnxk_eswitch_txq_setup(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid, uint16_t nb_desc,\n+\t\t\t const struct rte_eth_txconf *tx_conf);\n+int cnxk_eswitch_txq_release(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);\n+int cnxk_eswitch_rxq_setup(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid, uint16_t nb_desc,\n+\t\t\t const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp);\n+int cnxk_eswitch_rxq_release(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);\n+int cnxk_eswitch_rxq_start(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);\n+int cnxk_eswitch_rxq_stop(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);\n+int cnxk_eswitch_txq_start(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);\n+int cnxk_eswitch_txq_stop(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid);\n+#endif /* __CNXK_ESWITCH_H__ */\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex e83f3c9050..012d098f80 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -28,6 +28,7 @@ sources = files(\n 'cnxk_ethdev_sec.c',\n 'cnxk_ethdev_telemetry.c',\n 'cnxk_ethdev_sec_telemetry.c',\n+ 'cnxk_eswitch.c',\n 'cnxk_link.c',\n 'cnxk_lookup.c',\n 'cnxk_ptp.c',\n", "prefixes": [ "v6", "02/23" ] }