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GET /api/patches/137684/?format=api
{ "id": 137684, "url": "http://patches.dpdk.org/api/patches/137684/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240301162553.30523-3-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240301162553.30523-3-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240301162553.30523-3-rnagadheeraj@marvell.com", "date": "2024-03-01T16:25:48", "name": "[v4,2/7] drivers/compress: add Nitrox driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "030e05c28706713c22c0d27626b17d82ba66f5c3", "submitter": { "id": 1365, "url": "http://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240301162553.30523-3-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 31338, "url": "http://patches.dpdk.org/api/series/31338/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31338", "date": "2024-03-01T16:25:46", "name": "add Nitrox compress device support", "version": 1, "mbox": "http://patches.dpdk.org/series/31338/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137684/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137684/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6E78A43C0C;\n\tFri, 1 Mar 2024 17:26:20 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3FE6242D66;\n\tFri, 1 Mar 2024 17:26:11 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 6C18D43251\n for <dev@dpdk.org>; Fri, 1 Mar 2024 17:26:09 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 4219mtgk013852; Fri, 1 Mar 2024 08:26:08 -0800", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wkcq593tk-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Fri, 01 Mar 2024 08:26:08 -0800 (PST)", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Fri, 1 Mar\n 2024 08:26:07 -0800", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id\n 15.0.1497.48; Fri, 1 Mar 2024 08:26:05 -0800", "from hyd1399.caveonetworks.com.com (10.69.176.80) by\n DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id\n 15.2.1258.12 via Frontend Transport; Fri, 1 Mar 2024 08:26:03 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=y2/NENeEFH+odg7bfeex0vJ9Sjt94RiccQ60l7GOVpM=; b=e8/\n /7Z3UOAiFN9IW54LDWP4vkllyygk20Y2HJ4VRPXGbtIG2WhFBHoSviwMFrjZkjAZ\n 17S6ihhYvF8K89HsbRBZb4wHyRQkJNZeKHYrQQPjHUXq00om/+JEiSLMHDixHosO\n OE7NuRq9XVLiQewzdIYw7yB8m2JHVTt8lR3erkAK2neGrhpv3nOA4BNP8FAtUJfU\n 3RDjKv8E1c5ke3OjxybiyGWhMV1RhiIPlsEeLpvnuKe0v3+cQbQilToCEXmLhCwO\n Pbtx3LqD95amk8vnx2DIosmq6Wy4zDvp0+8Mf+v9r2VRQ9t+Tyb35nWDOTm4+jyd\n tOib82gldcqQDCokJCg==", "From": "Nagadheeraj Rottela <rnagadheeraj@marvell.com>", "To": "<gakhil@marvell.com>, <fanzhang.oss@gmail.com>, <ashishg@marvell.com>", "CC": "<dev@dpdk.org>, Nagadheeraj Rottela <rnagadheeraj@marvell.com>", "Subject": "[PATCH v4 2/7] drivers/compress: add Nitrox driver", "Date": "Fri, 1 Mar 2024 21:55:48 +0530", "Message-ID": "<20240301162553.30523-3-rnagadheeraj@marvell.com>", "X-Mailer": "git-send-email 2.42.0", "In-Reply-To": "<20240301162553.30523-1-rnagadheeraj@marvell.com>", "References": "<20240301162553.30523-1-rnagadheeraj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "m-pKAQODtgEJwoivdcewm3OmnSxgl-vr", "X-Proofpoint-ORIG-GUID": "m-pKAQODtgEJwoivdcewm3OmnSxgl-vr", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-03-01_17,2024-03-01_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Introduce Nitrox compressdev driver.\nThis patch implements below operations\n- dev_configure\n- dev_close\n- dev_infos_get\n- private_xform_create\n- private_xform_free\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n MAINTAINERS | 7 +\n doc/guides/compressdevs/features/nitrox.ini | 17 +\n doc/guides/compressdevs/index.rst | 1 +\n doc/guides/compressdevs/nitrox.rst | 50 +++\n doc/guides/rel_notes/release_24_03.rst | 3 +\n drivers/common/nitrox/meson.build | 1 +\n drivers/common/nitrox/nitrox_device.c | 37 +-\n drivers/common/nitrox/nitrox_device.h | 3 +\n drivers/compress/nitrox/meson.build | 15 +\n drivers/compress/nitrox/nitrox_comp.c | 353 +++++++++++++++++++\n drivers/compress/nitrox/nitrox_comp.h | 33 ++\n drivers/compress/nitrox/nitrox_comp_reqmgr.h | 40 +++\n 12 files changed, 555 insertions(+), 5 deletions(-)\n create mode 100644 doc/guides/compressdevs/features/nitrox.ini\n create mode 100644 doc/guides/compressdevs/nitrox.rst\n create mode 100644 drivers/compress/nitrox/meson.build\n create mode 100644 drivers/compress/nitrox/nitrox_comp.c\n create mode 100644 drivers/compress/nitrox/nitrox_comp.h\n create mode 100644 drivers/compress/nitrox/nitrox_comp_reqmgr.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex d6abebc55c..a6e2cf6eae 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1215,6 +1215,13 @@ F: drivers/compress/isal/\n F: doc/guides/compressdevs/isal.rst\n F: doc/guides/compressdevs/features/isal.ini\n \n+Marvell Nitrox\n+M: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n+F: drivers/compress/nitrox/\n+F: drivers/common/nitrox/\n+F: doc/guides/compressdevs/nitrox.rst\n+F: doc/guides/compressdevs/features/nitrox.ini\n+\n NVIDIA mlx5\n M: Matan Azrad <matan@nvidia.com>\n F: drivers/compress/mlx5/\ndiff --git a/doc/guides/compressdevs/features/nitrox.ini b/doc/guides/compressdevs/features/nitrox.ini\nnew file mode 100644\nindex 0000000000..1b6a96ac6d\n--- /dev/null\n+++ b/doc/guides/compressdevs/features/nitrox.ini\n@@ -0,0 +1,17 @@\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+; Supported features of 'nitrox' compression driver.\n+;\n+[Features]\n+HW Accelerated = Y\n+Stateful Compression = Y\n+Stateful Decompression = Y\n+OOP SGL In SGL Out = Y\n+OOP SGL In LB Out = Y\n+OOP LB In SGL Out = Y\n+Deflate = Y\n+Adler32 = Y\n+Crc32 = Y\n+Fixed = Y\n+Dynamic = Y\ndiff --git a/doc/guides/compressdevs/index.rst b/doc/guides/compressdevs/index.rst\nindex 54a3ef4273..849f211688 100644\n--- a/doc/guides/compressdevs/index.rst\n+++ b/doc/guides/compressdevs/index.rst\n@@ -12,6 +12,7 @@ Compression Device Drivers\n overview\n isal\n mlx5\n+ nitrox\n octeontx\n qat_comp\n zlib\ndiff --git a/doc/guides/compressdevs/nitrox.rst b/doc/guides/compressdevs/nitrox.rst\nnew file mode 100644\nindex 0000000000..840fd7241a\n--- /dev/null\n+++ b/doc/guides/compressdevs/nitrox.rst\n@@ -0,0 +1,50 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2024 Marvell.\n+\n+Marvell NITROX Compression Poll Mode Driver\n+===========================================\n+\n+The Nitrox compression poll mode driver provides support for offloading\n+compression and decompression operations to the NITROX V processor.\n+Detailed information about the NITROX V processor can be obtained here:\n+\n+* https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/\n+\n+Features\n+--------\n+\n+NITROX V compression PMD has support for:\n+\n+Compression/Decompression algorithm:\n+\n+* DEFLATE\n+\n+Huffman code type:\n+\n+* FIXED\n+* DYNAMIC\n+\n+Window size support:\n+\n+* Min - 2 bytes\n+* Max - 32KB\n+\n+Checksum generation:\n+\n+* CRC32, Adler\n+\n+Limitations\n+-----------\n+\n+* Compressdev level 0, no compression, is not supported.\n+\n+Initialization\n+--------------\n+\n+Nitrox compression PMD depends on Nitrox kernel PF driver being installed on\n+the platform. Nitrox PF driver is required to create VF devices which will\n+be used by the PMD. Each VF device can enable one compressdev PMD.\n+\n+Nitrox kernel PF driver is available as part of CNN55XX-Driver SDK. The SDK\n+and it's installation instructions can be obtained from:\n+`Marvell Customer Portal <https://www.marvell.com/support/extranets.html>`_.\ndiff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 879bb4944c..bb91953a23 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -138,6 +138,9 @@ New Features\n to support TLS v1.2, TLS v1.3 and DTLS v1.2.\n * Added PMD API to allow raw submission of instructions to CPT.\n \n+* **Added Marvell NITROX compression PMD.**\n+\n+ * Added support for DEFLATE compression and decompression.\n \n Removed Items\n -------------\ndiff --git a/drivers/common/nitrox/meson.build b/drivers/common/nitrox/meson.build\nindex 99fadbbfc9..f3cb42f006 100644\n--- a/drivers/common/nitrox/meson.build\n+++ b/drivers/common/nitrox/meson.build\n@@ -16,3 +16,4 @@ sources += files(\n )\n \n includes += include_directories('../../crypto/nitrox')\n+includes += include_directories('../../compress/nitrox')\ndiff --git a/drivers/common/nitrox/nitrox_device.c b/drivers/common/nitrox/nitrox_device.c\nindex b2f638ec8a..39edc440a7 100644\n--- a/drivers/common/nitrox/nitrox_device.c\n+++ b/drivers/common/nitrox/nitrox_device.c\n@@ -7,6 +7,7 @@\n #include \"nitrox_device.h\"\n #include \"nitrox_hal.h\"\n #include \"nitrox_sym.h\"\n+#include \"nitrox_comp.h\"\n \n #define PCI_VENDOR_ID_CAVIUM\t0x177d\n #define NITROX_V_PCI_VF_DEV_ID\t0x13\n@@ -67,7 +68,7 @@ nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\tstruct rte_pci_device *pdev)\n {\n \tstruct nitrox_device *ndev;\n-\tint err;\n+\tint err = -1;\n \n \t/* Nitrox CSR space */\n \tif (!pdev->mem_resource[0].addr)\n@@ -79,12 +80,20 @@ nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \n \tndev_init(ndev, pdev);\n \terr = nitrox_sym_pmd_create(ndev);\n-\tif (err) {\n-\t\tndev_release(ndev);\n-\t\treturn err;\n-\t}\n+\tif (err)\n+\t\tgoto sym_pmd_err;\n+\n+\terr = nitrox_comp_pmd_create(ndev);\n+\tif (err)\n+\t\tgoto comp_pmd_err;\n \n \treturn 0;\n+\n+comp_pmd_err:\n+\tnitrox_sym_pmd_destroy(ndev);\n+sym_pmd_err:\n+\tndev_release(ndev);\n+\treturn err;\n }\n \n static int\n@@ -101,6 +110,10 @@ nitrox_pci_remove(struct rte_pci_device *pdev)\n \tif (err)\n \t\treturn err;\n \n+\terr = nitrox_comp_pmd_destroy(ndev);\n+\tif (err)\n+\t\treturn err;\n+\n \tndev_release(ndev);\n \treturn 0;\n }\n@@ -134,5 +147,19 @@ nitrox_sym_pmd_destroy(struct nitrox_device *ndev)\n \treturn 0;\n }\n \n+__rte_weak int\n+nitrox_comp_pmd_create(struct nitrox_device *ndev)\n+{\n+\tRTE_SET_USED(ndev);\n+\treturn 0;\n+}\n+\n+__rte_weak int\n+nitrox_comp_pmd_destroy(struct nitrox_device *ndev)\n+{\n+\tRTE_SET_USED(ndev);\n+\treturn 0;\n+}\n+\n RTE_PMD_REGISTER_PCI(nitrox, nitrox_pmd);\n RTE_PMD_REGISTER_PCI_TABLE(nitrox, pci_id_nitrox_map);\ndiff --git a/drivers/common/nitrox/nitrox_device.h b/drivers/common/nitrox/nitrox_device.h\nindex b7c7ffd772..877bccb321 100644\n--- a/drivers/common/nitrox/nitrox_device.h\n+++ b/drivers/common/nitrox/nitrox_device.h\n@@ -8,13 +8,16 @@\n #include <bus_pci_driver.h>\n \n struct nitrox_sym_device;\n+struct nitrox_comp_device;\n \n struct nitrox_device {\n \tTAILQ_ENTRY(nitrox_device) next;\n \tstruct rte_pci_device *pdev;\n \tuint8_t *bar_addr;\n \tstruct nitrox_sym_device *sym_dev;\n+\tstruct nitrox_comp_device *comp_dev;\n \tstruct rte_device rte_sym_dev;\n+\tstruct rte_device rte_comp_dev;\n \tuint16_t nr_queues;\n };\n \ndiff --git a/drivers/compress/nitrox/meson.build b/drivers/compress/nitrox/meson.build\nnew file mode 100644\nindex 0000000000..f137303689\n--- /dev/null\n+++ b/drivers/compress/nitrox/meson.build\n@@ -0,0 +1,15 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright (c) 2024 Marvell.\n+\n+if not is_linux\n+ build = false\n+ reason = 'only supported on Linux'\n+endif\n+\n+deps += ['common_nitrox', 'bus_pci', 'compressdev']\n+\n+sources += files(\n+ 'nitrox_comp.c',\n+)\n+\n+includes += include_directories('../../common/nitrox')\ndiff --git a/drivers/compress/nitrox/nitrox_comp.c b/drivers/compress/nitrox/nitrox_comp.c\nnew file mode 100644\nindex 0000000000..e97a686fbf\n--- /dev/null\n+++ b/drivers/compress/nitrox/nitrox_comp.c\n@@ -0,0 +1,353 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2024 Marvell.\n+ */\n+\n+#include <rte_compressdev_pmd.h>\n+#include <rte_comp.h>\n+#include <rte_errno.h>\n+\n+#include \"nitrox_comp.h\"\n+#include \"nitrox_device.h\"\n+#include \"nitrox_logs.h\"\n+#include \"nitrox_comp_reqmgr.h\"\n+\n+static const char nitrox_comp_drv_name[] = RTE_STR(COMPRESSDEV_NAME_NITROX_PMD);\n+static const struct rte_driver nitrox_rte_comp_drv = {\n+\t.name = nitrox_comp_drv_name,\n+\t.alias = nitrox_comp_drv_name\n+};\n+\n+static const struct rte_compressdev_capabilities\n+\t\t\t\tnitrox_comp_pmd_capabilities[] = {\n+\t{\t.algo = RTE_COMP_ALGO_DEFLATE,\n+\t\t.comp_feature_flags = RTE_COMP_FF_HUFFMAN_FIXED |\n+\t\t\t\t RTE_COMP_FF_HUFFMAN_DYNAMIC |\n+\t\t\t\t RTE_COMP_FF_CRC32_CHECKSUM |\n+\t\t\t\t RTE_COMP_FF_ADLER32_CHECKSUM |\n+\t\t\t\t RTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n+\t\t\t\t RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |\n+\t\t\t\t RTE_COMP_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\t\t RTE_COMP_FF_OOP_LB_IN_SGL_OUT,\n+\t\t.window_size = {\n+\t\t\t.min = NITROX_COMP_WINDOW_SIZE_MIN,\n+\t\t\t.max = NITROX_COMP_WINDOW_SIZE_MAX,\n+\t\t\t.increment = 1\n+\t\t},\n+\t},\n+\tRTE_COMP_END_OF_CAPABILITIES_LIST()\n+};\n+\n+static int nitrox_comp_dev_configure(struct rte_compressdev *dev,\n+\t\t\t\t struct rte_compressdev_config *config)\n+{\n+\tstruct nitrox_comp_device *comp_dev = dev->data->dev_private;\n+\tstruct nitrox_device *ndev = comp_dev->ndev;\n+\tuint32_t xform_cnt;\n+\tchar name[RTE_MEMPOOL_NAMESIZE];\n+\n+\tif (config->nb_queue_pairs > ndev->nr_queues) {\n+\t\tNITROX_LOG(ERR, \"Invalid queue pairs, max supported %d\\n\",\n+\t\t\t ndev->nr_queues);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\txform_cnt = config->max_nb_priv_xforms + config->max_nb_streams;\n+\tif (unlikely(xform_cnt == 0)) {\n+\t\tNITROX_LOG(ERR, \"Invalid configuration with 0 xforms\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsnprintf(name, sizeof(name), \"%s_xform\", dev->data->name);\n+\tcomp_dev->xform_pool = rte_mempool_create(name,\n+\t\t\txform_cnt, sizeof(struct nitrox_comp_xform),\n+\t\t\t0, 0, NULL, NULL, NULL, NULL,\n+\t\t\tconfig->socket_id, 0);\n+\tif (comp_dev->xform_pool == NULL) {\n+\t\tNITROX_LOG(ERR, \"Failed to create xform pool, err %d\\n\",\n+\t\t\t rte_errno);\n+\t\treturn -rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int nitrox_comp_dev_start(struct rte_compressdev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\treturn 0;\n+}\n+\n+static void nitrox_comp_dev_stop(struct rte_compressdev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+}\n+\n+static int nitrox_comp_dev_close(struct rte_compressdev *dev)\n+{\n+\tstruct nitrox_comp_device *comp_dev = dev->data->dev_private;\n+\n+\trte_mempool_free(comp_dev->xform_pool);\n+\tcomp_dev->xform_pool = NULL;\n+\treturn 0;\n+}\n+\n+static void nitrox_comp_stats_get(struct rte_compressdev *dev,\n+\t\t\t\t struct rte_compressdev_stats *stats)\n+{\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(stats);\n+}\n+\n+static void nitrox_comp_stats_reset(struct rte_compressdev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+}\n+\n+static void nitrox_comp_dev_info_get(struct rte_compressdev *dev,\n+\t\t\t\t struct rte_compressdev_info *info)\n+{\n+\tstruct nitrox_comp_device *comp_dev = dev->data->dev_private;\n+\tstruct nitrox_device *ndev = comp_dev->ndev;\n+\n+\tif (!info)\n+\t\treturn;\n+\n+\tinfo->max_nb_queue_pairs = ndev->nr_queues;\n+\tinfo->feature_flags = dev->feature_flags;\n+\tinfo->capabilities = nitrox_comp_pmd_capabilities;\n+}\n+\n+static int nitrox_comp_queue_pair_setup(struct rte_compressdev *dev,\n+\t\t\t\t\tuint16_t qp_id,\n+\t\t\t\t\tuint32_t max_inflight_ops, int socket_id)\n+{\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(qp_id);\n+\tRTE_SET_USED(max_inflight_ops);\n+\tRTE_SET_USED(socket_id);\n+\treturn -1;\n+}\n+\n+static int nitrox_comp_queue_pair_release(struct rte_compressdev *dev,\n+\t\t\t\t\t uint16_t qp_id)\n+{\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(qp_id);\n+\treturn 0;\n+}\n+\n+static int nitrox_comp_private_xform_create(struct rte_compressdev *dev,\n+\t\t\t\t\t const struct rte_comp_xform *xform,\n+\t\t\t\t\t void **private_xform)\n+{\n+\tstruct nitrox_comp_device *comp_dev = dev->data->dev_private;\n+\tstruct nitrox_comp_xform *nxform;\n+\tenum rte_comp_checksum_type chksum_type;\n+\tint ret;\n+\n+\tif (unlikely(comp_dev->xform_pool == NULL)) {\n+\t\tNITROX_LOG(ERR, \"private xform pool not yet created\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rte_mempool_get(comp_dev->xform_pool, private_xform)) {\n+\t\tNITROX_LOG(ERR, \"Failed to get from private xform pool\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tnxform = (struct nitrox_comp_xform *)*private_xform;\n+\tmemset(nxform, 0, sizeof(*nxform));\n+\tif (xform->type == RTE_COMP_COMPRESS) {\n+\t\tenum rte_comp_huffman algo;\n+\t\tint level;\n+\n+\t\tnxform->op = NITROX_COMP_OP_COMPRESS;\n+\t\tif (xform->compress.algo != RTE_COMP_ALGO_DEFLATE) {\n+\t\t\tNITROX_LOG(ERR, \"Only deflate is supported\\n\");\n+\t\t\tret = -ENOTSUP;\n+\t\t\tgoto err_exit;\n+\t\t}\n+\n+\t\talgo = xform->compress.deflate.huffman;\n+\t\tif (algo == RTE_COMP_HUFFMAN_DEFAULT)\n+\t\t\tnxform->algo = NITROX_COMP_ALGO_DEFLATE_DEFAULT;\n+\t\telse if (algo == RTE_COMP_HUFFMAN_FIXED)\n+\t\t\tnxform->algo = NITROX_COMP_ALGO_DEFLATE_FIXEDHUFF;\n+\t\telse if (algo == RTE_COMP_HUFFMAN_DYNAMIC)\n+\t\t\tnxform->algo = NITROX_COMP_ALGO_DEFLATE_DYNHUFF;\n+\t\telse {\n+\t\t\tNITROX_LOG(ERR, \"Invalid deflate algorithm %d\\n\", algo);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto err_exit;\n+\t\t}\n+\n+\t\tlevel = xform->compress.level;\n+\t\tif (level == RTE_COMP_LEVEL_PMD_DEFAULT) {\n+\t\t\tnxform->level = NITROX_COMP_LEVEL_MEDIUM;\n+\t\t} else if (level >= NITROX_COMP_LEVEL_LOWEST_START &&\n+\t\t\t level <= NITROX_COMP_LEVEL_LOWEST_END) {\n+\t\t\tnxform->level = NITROX_COMP_LEVEL_LOWEST;\n+\t\t} else if (level >= NITROX_COMP_LEVEL_LOWER_START &&\n+\t\t\t level <= NITROX_COMP_LEVEL_LOWER_END) {\n+\t\t\tnxform->level = NITROX_COMP_LEVEL_LOWER;\n+\t\t} else if (level >= NITROX_COMP_LEVEL_MEDIUM_START &&\n+\t\t\t level <= NITROX_COMP_LEVEL_MEDIUM_END) {\n+\t\t\tnxform->level = NITROX_COMP_LEVEL_MEDIUM;\n+\t\t} else if (level >= NITROX_COMP_LEVEL_BEST_START &&\n+\t\t\t level <= NITROX_COMP_LEVEL_BEST_END) {\n+\t\t\tnxform->level = NITROX_COMP_LEVEL_BEST;\n+\t\t} else {\n+\t\t\tNITROX_LOG(ERR, \"Unsupported compression level %d\\n\",\n+\t\t\t\t xform->compress.level);\n+\t\t\tret = -ENOTSUP;\n+\t\t\tgoto err_exit;\n+\t\t}\n+\n+\t\tchksum_type = xform->compress.chksum;\n+\t} else if (xform->type == RTE_COMP_DECOMPRESS) {\n+\t\tnxform->op = NITROX_COMP_OP_DECOMPRESS;\n+\t\tif (xform->decompress.algo != RTE_COMP_ALGO_DEFLATE) {\n+\t\t\tNITROX_LOG(ERR, \"Only deflate is supported\\n\");\n+\t\t\tret = -ENOTSUP;\n+\t\t\tgoto err_exit;\n+\t\t}\n+\n+\t\tnxform->algo = NITROX_COMP_ALGO_DEFLATE_DEFAULT;\n+\t\tnxform->level = NITROX_COMP_LEVEL_BEST;\n+\t\tchksum_type = xform->decompress.chksum;\n+\t} else {\n+\t\tret = -EINVAL;\n+\t\tgoto err_exit;\n+\t}\n+\n+\tif (chksum_type == RTE_COMP_CHECKSUM_NONE)\n+\t\tnxform->chksum_type = NITROX_CHKSUM_TYPE_NONE;\n+\telse if (chksum_type == RTE_COMP_CHECKSUM_CRC32)\n+\t\tnxform->chksum_type = NITROX_CHKSUM_TYPE_CRC32;\n+\telse if (chksum_type == RTE_COMP_CHECKSUM_ADLER32)\n+\t\tnxform->chksum_type = NITROX_CHKSUM_TYPE_ADLER32;\n+\telse {\n+\t\tNITROX_LOG(ERR, \"Unsupported checksum type %d\\n\",\n+\t\t\t chksum_type);\n+\t\tret = -ENOTSUP;\n+\t\tgoto err_exit;\n+\t}\n+\n+\treturn 0;\n+err_exit:\n+\tmemset(nxform, 0, sizeof(*nxform));\n+\trte_mempool_put(comp_dev->xform_pool, nxform);\n+\treturn ret;\n+}\n+\n+static int nitrox_comp_private_xform_free(struct rte_compressdev *dev,\n+\t\t\t\t\t void *private_xform)\n+{\n+\tstruct nitrox_comp_xform *nxform = private_xform;\n+\tstruct rte_mempool *mp = rte_mempool_from_obj(nxform);\n+\n+\tRTE_SET_USED(dev);\n+\tif (unlikely(nxform == NULL))\n+\t\treturn -EINVAL;\n+\n+\tmemset(nxform, 0, sizeof(*nxform));\n+\tmp = rte_mempool_from_obj(nxform);\n+\trte_mempool_put(mp, nxform);\n+\treturn 0;\n+}\n+\n+static uint16_t nitrox_comp_dev_enq_burst(void *qp,\n+\t\t\t\t\t struct rte_comp_op **ops,\n+\t\t\t\t\t uint16_t nb_ops)\n+{\n+\tRTE_SET_USED(qp);\n+\tRTE_SET_USED(ops);\n+\tRTE_SET_USED(nb_ops);\n+\treturn 0;\n+}\n+\n+static uint16_t nitrox_comp_dev_deq_burst(void *qp,\n+\t\t\t\t\t struct rte_comp_op **ops,\n+\t\t\t\t\t uint16_t nb_ops)\n+{\n+\tRTE_SET_USED(qp);\n+\tRTE_SET_USED(ops);\n+\tRTE_SET_USED(nb_ops);\n+\treturn 0;\n+}\n+\n+static struct rte_compressdev_ops nitrox_compressdev_ops = {\n+\t\t.dev_configure\t\t= nitrox_comp_dev_configure,\n+\t\t.dev_start\t\t= nitrox_comp_dev_start,\n+\t\t.dev_stop\t\t= nitrox_comp_dev_stop,\n+\t\t.dev_close\t\t= nitrox_comp_dev_close,\n+\n+\t\t.stats_get\t\t= nitrox_comp_stats_get,\n+\t\t.stats_reset\t\t= nitrox_comp_stats_reset,\n+\n+\t\t.dev_infos_get\t\t= nitrox_comp_dev_info_get,\n+\n+\t\t.queue_pair_setup\t= nitrox_comp_queue_pair_setup,\n+\t\t.queue_pair_release\t= nitrox_comp_queue_pair_release,\n+\n+\t\t.private_xform_create\t= nitrox_comp_private_xform_create,\n+\t\t.private_xform_free\t= nitrox_comp_private_xform_free,\n+\t\t.stream_create\t\t= NULL,\n+\t\t.stream_free\t\t= NULL\n+};\n+\n+int\n+nitrox_comp_pmd_create(struct nitrox_device *ndev)\n+{\n+\tchar name[RTE_COMPRESSDEV_NAME_MAX_LEN];\n+\tstruct rte_compressdev_pmd_init_params init_params = {\n+\t\t\t.name = \"\",\n+\t\t\t.socket_id = ndev->pdev->device.numa_node,\n+\t};\n+\tstruct rte_compressdev *cdev;\n+\n+\trte_pci_device_name(&ndev->pdev->addr, name, sizeof(name));\n+\tsnprintf(name + strlen(name),\n+\t\t RTE_COMPRESSDEV_NAME_MAX_LEN - strlen(name),\n+\t\t \"_n5comp\");\n+\tndev->rte_comp_dev.driver = &nitrox_rte_comp_drv;\n+\tndev->rte_comp_dev.numa_node = ndev->pdev->device.numa_node;\n+\tndev->rte_comp_dev.devargs = NULL;\n+\tcdev = rte_compressdev_pmd_create(name,\n+\t\t\t\t\t &ndev->rte_comp_dev,\n+\t\t\t\t\t sizeof(struct nitrox_comp_device),\n+\t\t\t\t\t &init_params);\n+\tif (!cdev) {\n+\t\tNITROX_LOG(ERR, \"Cryptodev '%s' creation failed\\n\", name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tcdev->dev_ops = &nitrox_compressdev_ops;\n+\tcdev->enqueue_burst = nitrox_comp_dev_enq_burst;\n+\tcdev->dequeue_burst = nitrox_comp_dev_deq_burst;\n+\tcdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;\n+\n+\tndev->comp_dev = cdev->data->dev_private;\n+\tndev->comp_dev->cdev = cdev;\n+\tndev->comp_dev->ndev = ndev;\n+\tndev->comp_dev->xform_pool = NULL;\n+\tNITROX_LOG(DEBUG, \"Created compressdev '%s', dev_id %d\\n\",\n+\t\t cdev->data->name, cdev->data->dev_id);\n+\treturn 0;\n+}\n+\n+int\n+nitrox_comp_pmd_destroy(struct nitrox_device *ndev)\n+{\n+\tint err;\n+\n+\tif (ndev->comp_dev == NULL)\n+\t\treturn 0;\n+\n+\terr = rte_compressdev_pmd_destroy(ndev->comp_dev->cdev);\n+\tif (err)\n+\t\treturn err;\n+\n+\tndev->comp_dev = NULL;\n+\treturn 0;\n+}\ndiff --git a/drivers/compress/nitrox/nitrox_comp.h b/drivers/compress/nitrox/nitrox_comp.h\nnew file mode 100644\nindex 0000000000..90e1931b05\n--- /dev/null\n+++ b/drivers/compress/nitrox/nitrox_comp.h\n@@ -0,0 +1,33 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2024 Marvell.\n+ */\n+\n+#ifndef _NITROX_COMP_H_\n+#define _NITROX_COMP_H_\n+\n+#define COMPRESSDEV_NAME_NITROX_PMD\tcompress_nitrox\n+#define NITROX_DECOMP_CTX_SIZE 2048\n+#define NITROX_CONSTANTS_MAX_SEARCH_DEPTH 31744\n+#define NITROX_COMP_WINDOW_SIZE_MIN 1\n+#define NITROX_COMP_WINDOW_SIZE_MAX 15\n+#define NITROX_COMP_LEVEL_LOWEST_START 1\n+#define NITROX_COMP_LEVEL_LOWEST_END 2\n+#define NITROX_COMP_LEVEL_LOWER_START 3\n+#define NITROX_COMP_LEVEL_LOWER_END 4\n+#define NITROX_COMP_LEVEL_MEDIUM_START 5\n+#define NITROX_COMP_LEVEL_MEDIUM_END 6\n+#define NITROX_COMP_LEVEL_BEST_START 7\n+#define NITROX_COMP_LEVEL_BEST_END 9\n+\n+struct nitrox_comp_device {\n+\tstruct rte_compressdev *cdev;\n+\tstruct nitrox_device *ndev;\n+\tstruct rte_mempool *xform_pool;\n+};\n+\n+struct nitrox_device;\n+\n+int nitrox_comp_pmd_create(struct nitrox_device *ndev);\n+int nitrox_comp_pmd_destroy(struct nitrox_device *ndev);\n+\n+#endif /* _NITROX_COMP_H_ */\ndiff --git a/drivers/compress/nitrox/nitrox_comp_reqmgr.h b/drivers/compress/nitrox/nitrox_comp_reqmgr.h\nnew file mode 100644\nindex 0000000000..14f35a1e5b\n--- /dev/null\n+++ b/drivers/compress/nitrox/nitrox_comp_reqmgr.h\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2024 Marvell.\n+ */\n+\n+#ifndef _NITROX_COMP_REQMGR_H_\n+#define _NITROX_COMP_REQMGR_H_\n+\n+enum nitrox_comp_op {\n+\tNITROX_COMP_OP_DECOMPRESS,\n+\tNITROX_COMP_OP_COMPRESS,\n+};\n+\n+enum nitrox_comp_algo {\n+\tNITROX_COMP_ALGO_DEFLATE_DEFAULT,\n+\tNITROX_COMP_ALGO_DEFLATE_DYNHUFF,\n+\tNITROX_COMP_ALGO_DEFLATE_FIXEDHUFF,\n+\tNITROX_COMP_ALGO_LZS,\n+};\n+\n+enum nitrox_comp_level {\n+\tNITROX_COMP_LEVEL_BEST,\n+\tNITROX_COMP_LEVEL_MEDIUM,\n+\tNITROX_COMP_LEVEL_LOWER,\n+\tNITROX_COMP_LEVEL_LOWEST,\n+};\n+\n+enum nitrox_chksum_type {\n+\tNITROX_CHKSUM_TYPE_CRC32,\n+\tNITROX_CHKSUM_TYPE_ADLER32,\n+\tNITROX_CHKSUM_TYPE_NONE,\n+};\n+\n+struct nitrox_comp_xform {\n+\tenum nitrox_comp_op op;\n+\tenum nitrox_comp_algo algo;\n+\tenum nitrox_comp_level level;\n+\tenum nitrox_chksum_type chksum_type;\n+};\n+\n+#endif /* _NITROX_COMP_REQMGR_H_ */\n", "prefixes": [ "v4", "2/7" ] }