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GET /api/patches/137450/?format=api
{ "id": 137450, "url": "http://patches.dpdk.org/api/patches/137450/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240228170046.176600-10-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240228170046.176600-10-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240228170046.176600-10-dsosnowski@nvidia.com", "date": "2024-02-28T17:00:44", "name": "[09/11] net/mlx5: move rarely used flow fields outside", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a3a739157a655c305d857f3f2be6c81d3194341c", "submitter": { "id": 2386, "url": "http://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240228170046.176600-10-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 31278, "url": "http://patches.dpdk.org/api/series/31278/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31278", "date": "2024-02-28T17:00:35", "name": "net/mlx5: flow insertion performance improvements", "version": 1, "mbox": "http://patches.dpdk.org/series/31278/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137450/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137450/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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b=hrV9dLYpCb1mi5xLq8dGH3iJSXeHLK+W8CutPAleLSz5CdAZoh8PoSnXt4mvD1hMKRTD1Rl9xSLQKlB04Xx9nK4vJlyaa1CiHkodofOlHEZqdqF34LL+hVJM8ASJ/4dnHyn0o8j6w3hgJ5LoThuLuSLDp5AORZlEilNLqy/7JNRfMz+0O21UvdzjiRjKTe3UapAI0GT0/nYlTjzH0JSBXEiXgn+/Y4l8PJeo2kgMDh0QOIwfvHW77/jPc97UBkROVeTPKI+DR7bLwZ0mO/zFaovM0tlV+vTCuU51Ooe/b4D1qC0x8dMAoSuRcUOyYgbFylvpAIlA7FMhYhYCBo6lBg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, Raslan Darawsheh <rasland@nvidia.com>, Bing Zhao\n <bingz@nvidia.com>", "Subject": "[PATCH 09/11] net/mlx5: move rarely used flow fields outside", "Date": "Wed, 28 Feb 2024 18:00:44 +0100", "Message-ID": "<20240228170046.176600-10-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240228170046.176600-1-dsosnowski@nvidia.com>", "References": "<20240228170046.176600-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A103:EE_|MN2PR12MB4095:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f5be1a28-7a39-4b35-e2ca-08dc387efa0a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", 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SFS:(13230031)(36860700004)(82310400014); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Feb 2024 17:01:58.9788 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f5be1a28-7a39-4b35-e2ca-08dc387efa0a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A103.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4095", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Some of the flow fields are either not always required\nor are used very rarely, e.g.:\n\n- AGE action reference,\n- direct METER/METER_MARK action reference,\n- matcher selector for resizable tables.\n\nThis patch moves these fields to rte_flow_hw_aux struct in order to\nreduce the overall size of the flow struct, reducing the total size\nof working set for most common use cases.\nThis results in reduction of the frequency of cache invalidation\nduring async flow operations processing.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 61 +++++++++++-----\n drivers/net/mlx5/mlx5_flow_hw.c | 121 ++++++++++++++++++++++++--------\n 2 files changed, 138 insertions(+), 44 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 2e3e7d0533..1c67d8dd35 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1271,31 +1271,60 @@ enum {\n #pragma GCC diagnostic ignored \"-Wpedantic\"\n #endif\n \n-/* HWS flow struct. */\n+/** HWS flow struct. */\n struct rte_flow_hw {\n-\tuint32_t idx; /* Flow index from indexed pool. */\n-\tuint32_t res_idx; /* Resource index from indexed pool. */\n-\tuint32_t fate_type; /* Fate action type. */\n+\t/** The table flow allcated from. */\n+\tstruct rte_flow_template_table *table;\n+\t/** Application's private data passed to enqueued flow operation. */\n+\tvoid *user_data;\n+\t/** Flow index from indexed pool. */\n+\tuint32_t idx;\n+\t/** Resource index from indexed pool. */\n+\tuint32_t res_idx;\n+\t/** HWS flow rule index passed to mlx5dr. */\n+\tuint32_t rule_idx;\n+\t/** Fate action type. */\n+\tuint32_t fate_type;\n+\t/** Ongoing flow operation type. */\n+\tuint8_t operation_type;\n+\t/** Index of pattern template this flow is based on. */\n+\tuint8_t mt_idx;\n+\n+\t/** COUNT action index. */\n+\tcnt_id_t cnt_id;\n \tunion {\n-\t\t/* Jump action. */\n+\t\t/** Jump action. */\n \t\tstruct mlx5_hw_jump_action *jump;\n-\t\tstruct mlx5_hrxq *hrxq; /* TIR action. */\n+\t\t/** TIR action. */\n+\t\tstruct mlx5_hrxq *hrxq;\n \t};\n-\tstruct rte_flow_template_table *table; /* The table flow allcated from. */\n-\tuint8_t mt_idx;\n-\tuint8_t matcher_selector:1;\n+\n+\t/**\n+\t * Padding for alignment to 56 bytes.\n+\t * Since mlx5dr rule is 72 bytes, whole flow is contained within 128 B (2 cache lines).\n+\t * This space is reserved for future additions to flow struct.\n+\t */\n+\tuint8_t padding[10];\n+\t/** HWS layer data struct. */\n+\tuint8_t rule[];\n+} __rte_packed;\n+\n+/** Auxiliary data fields that are updatable. */\n+struct rte_flow_hw_aux_fields {\n+\t/** AGE action index. */\n \tuint32_t age_idx;\n-\tcnt_id_t cnt_id;\n+\t/** Direct meter (METER or METER_MARK) action index. */\n \tuint32_t mtr_id;\n-\tuint32_t rule_idx;\n-\tuint8_t operation_type; /**< Ongoing flow operation type. */\n-\tvoid *user_data; /**< Application's private data passed to enqueued flow operation. */\n-\tuint8_t padding[1]; /**< Padding for proper alignment of mlx5dr rule struct. */\n-\tuint8_t rule[]; /* HWS layer data struct. */\n-} __rte_packed;\n+};\n \n /** Auxiliary data stored per flow which is not required to be stored in main flow structure. */\n struct rte_flow_hw_aux {\n+\t/** Auxiliary fields associated with the original flow. */\n+\tstruct rte_flow_hw_aux_fields orig;\n+\t/** Auxiliary fields associated with the updated flow. */\n+\tstruct rte_flow_hw_aux_fields upd;\n+\t/** Index of resizable matcher associated with this flow. */\n+\tuint8_t matcher_selector;\n \t/** Placeholder flow struct used during flow rule update operation. */\n \tstruct rte_flow_hw upd_flow;\n };\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 4d39e7bd45..3252f76e64 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -139,6 +139,50 @@ mlx5_flow_hw_aux(uint16_t port_id, struct rte_flow_hw *flow)\n \t}\n }\n \n+static __rte_always_inline void\n+mlx5_flow_hw_aux_set_age_idx(struct rte_flow_hw *flow,\n+\t\t\t struct rte_flow_hw_aux *aux,\n+\t\t\t uint32_t age_idx)\n+{\n+\t/*\n+\t * Only when creating a flow rule, the type will be set explicitly.\n+\t * Or else, it should be none in the rule update case.\n+\t */\n+\tif (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))\n+\t\taux->upd.age_idx = age_idx;\n+\telse\n+\t\taux->orig.age_idx = age_idx;\n+}\n+\n+static __rte_always_inline uint32_t\n+mlx5_flow_hw_aux_get_age_idx(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)\n+{\n+\tif (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))\n+\t\treturn aux->upd.age_idx;\n+\telse\n+\t\treturn aux->orig.age_idx;\n+}\n+\n+static __rte_always_inline void\n+mlx5_flow_hw_aux_set_mtr_id(struct rte_flow_hw *flow,\n+\t\t\t struct rte_flow_hw_aux *aux,\n+\t\t\t uint32_t mtr_id)\n+{\n+\tif (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))\n+\t\taux->upd.mtr_id = mtr_id;\n+\telse\n+\t\taux->orig.mtr_id = mtr_id;\n+}\n+\n+static __rte_always_inline uint32_t __rte_unused\n+mlx5_flow_hw_aux_get_mtr_id(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux)\n+{\n+\tif (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE))\n+\t\treturn aux->upd.mtr_id;\n+\telse\n+\t\treturn aux->orig.mtr_id;\n+}\n+\n static int\n mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_template_table *tbl,\n@@ -2753,6 +2797,7 @@ flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,\n \tstruct mlx5_aso_mtr *aso_mtr;\n \tstruct mlx5_age_info *age_info;\n \tstruct mlx5_hws_age_param *param;\n+\tstruct rte_flow_hw_aux *aux;\n \tuint32_t act_idx = (uint32_t)(uintptr_t)action->conf;\n \tuint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;\n \tuint32_t idx = act_idx &\n@@ -2790,11 +2835,12 @@ flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,\n \t\tflow->cnt_id = act_idx;\n \t\tbreak;\n \tcase MLX5_INDIRECT_ACTION_TYPE_AGE:\n+\t\taux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n \t\t/*\n \t\t * Save the index with the indirect type, to recognize\n \t\t * it in flow destroy.\n \t\t */\n-\t\tflow->age_idx = act_idx;\n+\t\tmlx5_flow_hw_aux_set_age_idx(flow, aux, act_idx);\n \t\tif (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)\n \t\t\t/*\n \t\t\t * The mutual update for idirect AGE & COUNT will be\n@@ -3020,14 +3066,16 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \tconst struct rte_flow_action_meter *meter = NULL;\n \tconst struct rte_flow_action_age *age = NULL;\n \tstruct rte_flow_attr attr = {\n-\t\t\t.ingress = 1,\n+\t\t.ingress = 1,\n \t};\n \tuint32_t ft_flag;\n-\tsize_t encap_len = 0;\n \tint ret;\n+\tsize_t encap_len = 0;\n \tuint32_t age_idx = 0;\n+\tuint32_t mtr_idx = 0;\n \tstruct mlx5_aso_mtr *aso_mtr;\n \tstruct mlx5_multi_pattern_segment *mp_segment = NULL;\n+\tstruct rte_flow_hw_aux *aux;\n \n \tattr.group = table->grp->group_id;\n \tft_flag = mlx5_hw_act_flag[!!table->grp->group_id][table->type];\n@@ -3207,6 +3255,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\treturn -1;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_AGE:\n+\t\t\taux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n \t\t\tage = action->conf;\n \t\t\t/*\n \t\t\t * First, create the AGE parameter, then create its\n@@ -3220,7 +3269,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\t\t\t\t error);\n \t\t\tif (age_idx == 0)\n \t\t\t\treturn -rte_errno;\n-\t\t\tflow->age_idx = age_idx;\n+\t\t\tmlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);\n \t\t\tif (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)\n \t\t\t\t/*\n \t\t\t\t * When AGE uses indirect counter, no need to\n@@ -3281,9 +3330,11 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t */\n \t\t\tret = flow_hw_meter_mark_compile(dev,\n \t\t\t\tact_data->action_dst, action,\n-\t\t\t\trule_acts, &flow->mtr_id, MLX5_HW_INV_QUEUE, error);\n+\t\t\t\trule_acts, &mtr_idx, MLX5_HW_INV_QUEUE, error);\n \t\t\tif (ret != 0)\n \t\t\t\treturn ret;\n+\t\t\taux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n+\t\t\tmlx5_flow_hw_aux_set_mtr_id(flow, aux, mtr_idx);\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n@@ -3291,9 +3342,10 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t}\n \tif (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) {\n \t\tif (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE) {\n-\t\t\tage_idx = flow->age_idx & MLX5_HWS_AGE_IDX_MASK;\n-\t\t\tif (mlx5_hws_cnt_age_get(priv->hws_cpool,\n-\t\t\t\t\t\t flow->cnt_id) != age_idx)\n+\t\t\taux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n+\t\t\tage_idx = mlx5_flow_hw_aux_get_age_idx(flow, aux) &\n+\t\t\t\t MLX5_HWS_AGE_IDX_MASK;\n+\t\t\tif (mlx5_hws_cnt_age_get(priv->hws_cpool, flow->cnt_id) != age_idx)\n \t\t\t\t/*\n \t\t\t\t * This is first use of this indirect counter\n \t\t\t\t * for this indirect AGE, need to increase the\n@@ -3305,8 +3357,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t * Update this indirect counter the indirect/direct AGE in which\n \t\t * using it.\n \t\t */\n-\t\tmlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id,\n-\t\t\t\t age_idx);\n+\t\tmlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, age_idx);\n \t}\n \tif (hw_acts->encap_decap && !hw_acts->encap_decap->shared) {\n \t\tint ix = mlx5_multi_pattern_reformat_to_index(hw_acts->encap_decap->action_type);\n@@ -3499,6 +3550,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t\t\t\t\t &rule_attr,\n \t\t\t\t\t (struct mlx5dr_rule *)flow->rule);\n \t} else {\n+\t\tstruct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n \t\tuint32_t selector;\n \n \t\tflow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE;\n@@ -3510,7 +3562,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t\t\t\t\t &rule_attr,\n \t\t\t\t\t (struct mlx5dr_rule *)flow->rule);\n \t\trte_rwlock_read_unlock(&table->matcher_replace_rwlk);\n-\t\tflow->matcher_selector = selector;\n+\t\taux->matcher_selector = selector;\n \t}\n \tif (likely(!ret)) {\n \t\tflow_hw_q_inc_flow_ops(priv, queue);\n@@ -3632,6 +3684,7 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,\n \t\t\t\t\t rule_acts, &rule_attr,\n \t\t\t\t\t (struct mlx5dr_rule *)flow->rule);\n \t} else {\n+\t\tstruct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n \t\tuint32_t selector;\n \n \t\tflow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE;\n@@ -3642,6 +3695,7 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,\n \t\t\t\t\t rule_acts, &rule_attr,\n \t\t\t\t\t (struct mlx5dr_rule *)flow->rule);\n \t\trte_rwlock_read_unlock(&table->matcher_replace_rwlk);\n+\t\taux->matcher_selector = selector;\n \t}\n \tif (likely(!ret)) {\n \t\tflow_hw_q_inc_flow_ops(priv, queue);\n@@ -3729,6 +3783,8 @@ flow_hw_async_flow_update(struct rte_eth_dev *dev,\n \t} else {\n \t\tnf->res_idx = of->res_idx;\n \t}\n+\t/* Indicate the construction function to set the proper fields. */\n+\tnf->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;\n \t/*\n \t * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices\n \t * for rule insertion hints.\n@@ -3846,15 +3902,17 @@ flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,\n \t\t\t struct rte_flow_hw *flow,\n \t\t\t struct rte_flow_error *error)\n {\n+\tstruct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(priv->dev_data->port_id, flow);\n \tuint32_t *cnt_queue;\n+\tuint32_t age_idx = aux->orig.age_idx;\n \n \tif (mlx5_hws_cnt_is_shared(priv->hws_cpool, flow->cnt_id)) {\n-\t\tif (flow->age_idx && !mlx5_hws_age_is_indirect(flow->age_idx)) {\n+\t\tif (age_idx && !mlx5_hws_age_is_indirect(age_idx)) {\n \t\t\t/* Remove this AGE parameter from indirect counter. */\n \t\t\tmlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, 0);\n \t\t\t/* Release the AGE parameter. */\n-\t\t\tmlx5_hws_age_action_destroy(priv, flow->age_idx, error);\n-\t\t\tflow->age_idx = 0;\n+\t\t\tmlx5_hws_age_action_destroy(priv, age_idx, error);\n+\t\t\tmlx5_flow_hw_aux_set_age_idx(flow, aux, 0);\n \t\t}\n \t\treturn;\n \t}\n@@ -3863,16 +3921,16 @@ flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,\n \t/* Put the counter first to reduce the race risk in BG thread. */\n \tmlx5_hws_cnt_pool_put(priv->hws_cpool, cnt_queue, &flow->cnt_id);\n \tflow->cnt_id = 0;\n-\tif (flow->age_idx) {\n-\t\tif (mlx5_hws_age_is_indirect(flow->age_idx)) {\n-\t\t\tuint32_t idx = flow->age_idx & MLX5_HWS_AGE_IDX_MASK;\n+\tif (age_idx) {\n+\t\tif (mlx5_hws_age_is_indirect(age_idx)) {\n+\t\t\tuint32_t idx = age_idx & MLX5_HWS_AGE_IDX_MASK;\n \n \t\t\tmlx5_hws_age_nb_cnt_decrease(priv, idx);\n \t\t} else {\n \t\t\t/* Release the AGE parameter. */\n-\t\t\tmlx5_hws_age_action_destroy(priv, flow->age_idx, error);\n+\t\t\tmlx5_hws_age_action_destroy(priv, age_idx, error);\n \t\t}\n-\t\tflow->age_idx = 0;\n+\t\tmlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);\n \t}\n }\n \n@@ -4002,6 +4060,7 @@ hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_mtr_pool *pool = priv->hws_mpool;\n \tstruct rte_flow_template_table *table = flow->table;\n+\tstruct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n \t/* Release the original resource index in case of update. */\n \tuint32_t res_idx = flow->res_idx;\n \n@@ -4012,9 +4071,9 @@ hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,\n \tif (mlx5_hws_cnt_id_valid(flow->cnt_id))\n \t\tflow_hw_age_count_release(priv, queue,\n \t\t\t\t\t flow, error);\n-\tif (flow->mtr_id) {\n-\t\tmlx5_ipool_free(pool->idx_pool,\tflow->mtr_id);\n-\t\tflow->mtr_id = 0;\n+\tif (aux->orig.mtr_id) {\n+\t\tmlx5_ipool_free(pool->idx_pool,\taux->orig.mtr_id);\n+\t\taux->orig.mtr_id = 0;\n \t}\n \tif (flow->operation_type != MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE) {\n \t\tif (table->resource)\n@@ -4025,6 +4084,8 @@ hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,\n \t\tstruct rte_flow_hw *upd_flow = &aux->upd_flow;\n \n \t\trte_memcpy(flow, upd_flow, offsetof(struct rte_flow_hw, rule));\n+\t\taux->orig = aux->upd;\n+\t\tflow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;\n \t\tif (table->resource)\n \t\t\tmlx5_ipool_free(table->resource, res_idx);\n \t}\n@@ -4037,7 +4098,8 @@ hw_cmpl_resizable_tbl(struct rte_eth_dev *dev,\n \t\t struct rte_flow_error *error)\n {\n \tstruct rte_flow_template_table *table = flow->table;\n-\tuint32_t selector = flow->matcher_selector;\n+\tstruct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n+\tuint32_t selector = aux->matcher_selector;\n \tuint32_t other_selector = (selector + 1) & 1;\n \n \tswitch (flow->operation_type) {\n@@ -4060,7 +4122,7 @@ hw_cmpl_resizable_tbl(struct rte_eth_dev *dev,\n \t\t\trte_atomic_fetch_add_explicit\n \t\t\t\t(&table->matcher_info[other_selector].refcnt, 1,\n \t\t\t\t rte_memory_order_relaxed);\n-\t\t\tflow->matcher_selector = other_selector;\n+\t\t\taux->matcher_selector = other_selector;\n \t\t}\n \t\tbreak;\n \tdefault:\n@@ -11206,6 +11268,7 @@ flow_hw_query(struct rte_eth_dev *dev, struct rte_flow *flow,\n {\n \tint ret = -EINVAL;\n \tstruct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;\n+\tstruct rte_flow_hw_aux *aux;\n \n \tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n \t\tswitch (actions->type) {\n@@ -11216,8 +11279,9 @@ flow_hw_query(struct rte_eth_dev *dev, struct rte_flow *flow,\n \t\t\t\t\t\t error);\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_AGE:\n-\t\t\tret = flow_hw_query_age(dev, hw_flow->age_idx, data,\n-\t\t\t\t\t\terror);\n+\t\t\taux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);\n+\t\t\tret = flow_hw_query_age(dev, mlx5_flow_hw_aux_get_age_idx(hw_flow, aux),\n+\t\t\t\t\t\tdata, error);\n \t\t\tbreak;\n \t\tdefault:\n \t\t\treturn rte_flow_error_set(error, ENOTSUP,\n@@ -12497,8 +12561,9 @@ flow_hw_update_resized(struct rte_eth_dev *dev, uint32_t queue,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct rte_flow_hw *hw_flow = (struct rte_flow_hw *)flow;\n \tstruct rte_flow_template_table *table = hw_flow->table;\n+\tstruct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);\n \tuint32_t table_selector = table->matcher_selector;\n-\tuint32_t rule_selector = hw_flow->matcher_selector;\n+\tuint32_t rule_selector = aux->matcher_selector;\n \tuint32_t other_selector;\n \tstruct mlx5dr_matcher *other_matcher;\n \tstruct mlx5dr_rule_attr rule_attr = {\n@@ -12511,7 +12576,7 @@ flow_hw_update_resized(struct rte_eth_dev *dev, uint32_t queue,\n \t * the one that was used BEFORE table resize.\n \t * Since the function is called AFTER table resize,\n \t * `table->matcher_selector` always points to the new matcher and\n-\t * `hw_flow->matcher_selector` points to a matcher used to create the flow.\n+\t * `aux->matcher_selector` points to a matcher used to create the flow.\n \t */\n \tother_selector = rule_selector == table_selector ?\n \t\t\t (rule_selector + 1) & 1 : rule_selector;\n", "prefixes": [ "09/11" ] }