Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/137447/?format=api
{ "id": 137447, "url": "http://patches.dpdk.org/api/patches/137447/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240228170046.176600-6-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240228170046.176600-6-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240228170046.176600-6-dsosnowski@nvidia.com", "date": "2024-02-28T17:00:40", "name": "[05/11] net/mlx5: remove action params from job", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2735bbc350aee1fd6a425b3362206c14a1003c22", "submitter": { "id": 2386, "url": "http://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240228170046.176600-6-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 31278, "url": "http://patches.dpdk.org/api/series/31278/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31278", "date": "2024-02-28T17:00:35", "name": "net/mlx5: flow insertion performance improvements", "version": 1, "mbox": "http://patches.dpdk.org/series/31278/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137447/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137447/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AB05F43C2C;\n\tWed, 28 Feb 2024 18:02:45 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9F28742FA3;\n\tWed, 28 Feb 2024 18:01:55 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2077.outbound.protection.outlook.com [40.107.243.77])\n by mails.dpdk.org (Postfix) with ESMTP id 4410B427E8\n for <dev@dpdk.org>; Wed, 28 Feb 2024 18:01:51 +0100 (CET)", "from MN2PR07CA0014.namprd07.prod.outlook.com (2603:10b6:208:1a0::24)\n by SA0PR12MB4590.namprd12.prod.outlook.com (2603:10b6:806:93::11)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.39; Wed, 28 Feb\n 2024 17:01:47 +0000", "from BL02EPF0001A106.namprd05.prod.outlook.com\n (2603:10b6:208:1a0:cafe::69) by MN2PR07CA0014.outlook.office365.com\n (2603:10b6:208:1a0::24) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.50 via Frontend\n Transport; Wed, 28 Feb 2024 17:01:47 +0000", "from mail.nvidia.com (216.228.117.160) by\n BL02EPF0001A106.mail.protection.outlook.com (10.167.241.139) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7292.25 via Frontend Transport; Wed, 28 Feb 2024 17:01:47 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 28 Feb\n 2024 09:01:15 -0800", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 28 Feb\n 2024 09:01:13 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=FgL1hQM9HiEjqYOhbs1/mWGF5lkOTyly4sZF0BEe3vNYyiztmk9eUN/ZuO/2PZ9kCxAOhhuKsT8y1i4U6FtMiw3ib2Ul62nYTiM/T6Fe3CQqDuzLZsU0kcE/CiaM/WdSkFfsbEFEeh/+j2GSskNdUTj6bipSoax+Q6DmSuELN69VSI55rPYy/p39SM25u2lpKbBn8958MP69FjNjYLuyJp0HrtcpnPY4SH7e4euxCH7rloAeHvUhESuWa+QX8E1UF/YzVl3g18z8k3XlnCWCBxMULFVBIICt9LrlkBRhiN8EMZsksuvdEjeoEQXMuozLgi98XVjsuCViXCRI3bNp0Q==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=4sO+NNyqov3mwLS1xQmBuK/L79gR7ObwfTe9N6l5mVE=;\n b=hT4BeFBN/zoHGqUgads2ESlMZfOVY494oneda13Z8db84XnI2tuZUCwQgDQ+OOQlSHSLECHUTwBfTNxnderqydXdTzd8FInwW066cwJWXjfB5SNhZqecVAFEHzNEH0YDALJIf9e+jhgHFsnNsn+1HRfjZEySOLYS06R4ydOLDUOKzQ3DBJyYe9sBFbzISL08HNWV0QY1BHV3BH4pOKbRI9VwQi4/RGhUl4bX4JJDMXXM5SAgk5OI05ePo1hijZ4WFqHrT9gyITV4Ypc0LO63aRSdUmI4Px+nYiKnbXb5HPRRw2VarY3dJjq+cH66Z1SASkc6mu430ugs5d/RBkB79w==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=4sO+NNyqov3mwLS1xQmBuK/L79gR7ObwfTe9N6l5mVE=;\n b=S4AiPoUAywApY6hvb4QzoC++Dh0s7QRHNImfMbHP2mzeN/B/JU7xBcMQa/59fAIXdvL1bVG1a4AIgaaxSm0NEj/pEXGozoVvjEbe4VS0Kjt+Bu1+2WbozeWl641++dziBLmSnE4emAQpJLHb8+EuzxS/70jEI7+NffNuhz0vAyRlHRxo1vHjiRemv20AhdHimsvnl1pZtpymdIZJ9YPsEkjgfBeVIw4JBLt4lWLmicsdTiA+7gWKM4btUSFTps/vlUtGrd85ZHthxxiM+0ZVOczvc7EkFgv0OUXaC9IbANyFJmGJ/E/75MQQGVd2n5ry3jCnbRnPPeoMDT/m5WaOYQ==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, Raslan Darawsheh <rasland@nvidia.com>, Bing Zhao\n <bingz@nvidia.com>", "Subject": "[PATCH 05/11] net/mlx5: remove action params from job", "Date": "Wed, 28 Feb 2024 18:00:40 +0100", "Message-ID": "<20240228170046.176600-6-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240228170046.176600-1-dsosnowski@nvidia.com>", "References": "<20240228170046.176600-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A106:EE_|SA0PR12MB4590:EE_", "X-MS-Office365-Filtering-Correlation-Id": "8e716a0c-a8cd-46ad-867d-08dc387ef316", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n It6oRMNjSXmGxl0rCxU7SMWdg2wy4jt2dVsP+TkbOWe0NZ+ire/Hn110pg3nTA4xn6Lmu6HM5jgqEd2VXC+k6d9MGki9s0FoyUzKCRuZmcV2GDYcLZDcRbNupZY0Ha+IEDmEuFsG1ahNw/MlYlt7VnnGWiUvkMkpCL0e2Wf65yUNO2InabxFrfWzlLCByed1VpiiK2g05JAA0KAzaHhOrxz6ThZUbLFjgl8zERkNWB15evsFzo+fqn9I1imvv3kmaTkohe/bahtPIyhefF3plqK+a1Oyei2chYJffhbDYvEBDku7KPH7hztMbiT0nxaOi93FqjenAp1jALj8BDJMEXxLaQLUYTInJ8r84+GN9fNtvvsvPuN1ddOiMwfN7fHAOJdwAscL+yoLxJZDOPNHMedxOizJkPYmyTt7IKa6ssV1+CJlxjtN+ek0M89Il05r/tM8zeahu3xO+er0y/V6QFMJb2GOiMTI6zpFDlgYx3EKrrJ97vao4sUKwFa5LzbLUH18WxIL2mnPJM4QSLG8s0vWZ8iG7qEjGp5QhNlH6UXSNuzZban9erkOe6qucMsAMOv23Pp9ZDhDOUyFd3h39THUOka98Ct89MAVpAKYNtoD2orw76VBy1dLt9p4TQ8jpPfaJu7w9bLWi3hEHnVA2zC4BPYQoRnPVaQvB66Ei6qcgdzLLlwqas94dYAOeOCGOtar+/fQuQYbEx+WPiMnFD88FgABylVEVy5hIwcMFsYQMYL6Kb1EePr/ByWVpLAA", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(82310400014)(36860700004); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Feb 2024 17:01:47.2329 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8e716a0c-a8cd-46ad-867d-08dc387ef316", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A106.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA0PR12MB4590", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "mlx5_hw_q_job struct held references to buffers which contained:\n\n- modify header commands array,\n- encap/decap data buffer,\n- IPv6 routing data buffer.\n\nThese buffers were passed as parameters to HWS layer during rule\ncreation. They were needed only during the call to HWS layer\nwhen flow operation is enqueues (i.e. mlx5dr_rule_create()).\nAfter operation is enqueued, data stored there can be safely discarded\nand it is not required to store it during the whole lifecycle of a job.\n\nThis patch removes references to these buffers from mlx5_hw_q_job\nand removes relevant allocations to reduce job memory footprint.\nBuffers stored per job are replaced with stack allocated ones,\ncontained in mlx5_flow_hw_action_params struct.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 3 -\n drivers/net/mlx5/mlx5_flow.h | 10 +++\n drivers/net/mlx5/mlx5_flow_hw.c | 120 ++++++++++++++------------------\n 3 files changed, 63 insertions(+), 70 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex bb1853e797..bd0846d6bf 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -401,9 +401,6 @@ struct mlx5_hw_q_job {\n \t\tconst void *action; /* Indirect action attached to the job. */\n \t};\n \tvoid *user_data; /* Job user data. */\n-\tuint8_t *encap_data; /* Encap data. */\n-\tuint8_t *push_data; /* IPv6 routing push data. */\n-\tstruct mlx5_modification_cmd *mhdr_cmd;\n \tstruct rte_flow_item *items;\n \tunion {\n \t\tstruct {\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 11135645ef..df1c913017 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1294,6 +1294,16 @@ typedef int\n \n #define MLX5_MHDR_MAX_CMD ((MLX5_MAX_MODIFY_NUM) * 2 + 1)\n \n+/** Container for flow action data constructed during flow rule creation. */\n+struct mlx5_flow_hw_action_params {\n+\t/** Array of constructed modify header commands. */\n+\tstruct mlx5_modification_cmd mhdr_cmd[MLX5_MHDR_MAX_CMD];\n+\t/** Constructed encap/decap data buffer. */\n+\tuint8_t encap_data[MLX5_ENCAP_MAX_LEN];\n+\t/** Constructed IPv6 routing data buffer. */\n+\tuint8_t ipv6_push_data[MLX5_PUSH_MAX_LEN];\n+};\n+\n /* rte flow action translate to DR action struct. */\n struct mlx5_action_construct_data {\n \tLIST_ENTRY(mlx5_action_construct_data) next;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex fcf493c771..7160477c83 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -158,7 +158,7 @@ static int flow_hw_translate_group(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_flow_error *error);\n static __rte_always_inline int\n flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,\n-\t\t\t struct mlx5_hw_q_job *job,\n+\t\t\t struct mlx5_modification_cmd *mhdr_cmd,\n \t\t\t struct mlx5_action_construct_data *act_data,\n \t\t\t const struct mlx5_hw_actions *hw_acts,\n \t\t\t const struct rte_flow_action *action);\n@@ -2799,7 +2799,7 @@ flow_hw_mhdr_cmd_is_nop(const struct mlx5_modification_cmd *cmd)\n * 0 on success, negative value otherwise and rte_errno is set.\n */\n static __rte_always_inline int\n-flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,\n+flow_hw_modify_field_construct(struct mlx5_modification_cmd *mhdr_cmd,\n \t\t\t struct mlx5_action_construct_data *act_data,\n \t\t\t const struct mlx5_hw_actions *hw_acts,\n \t\t\t const struct rte_flow_action *action)\n@@ -2858,7 +2858,7 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,\n \n \t\tif (i >= act_data->modify_header.mhdr_cmds_end)\n \t\t\treturn -1;\n-\t\tif (flow_hw_mhdr_cmd_is_nop(&job->mhdr_cmd[i])) {\n+\t\tif (flow_hw_mhdr_cmd_is_nop(&mhdr_cmd[i])) {\n \t\t\t++i;\n \t\t\tcontinue;\n \t\t}\n@@ -2878,7 +2878,7 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,\n \t\t mhdr_action->dst.field == RTE_FLOW_FIELD_IPV6_DSCP)\n \t\t\tdata <<= MLX5_IPV6_HDR_DSCP_SHIFT;\n \t\tdata = (data & mask) >> off_b;\n-\t\tjob->mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);\n+\t\tmhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);\n \t\t++field;\n \t} while (field->size);\n \treturn 0;\n@@ -2892,8 +2892,10 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,\n *\n * @param[in] dev\n * Pointer to the rte_eth_dev structure.\n- * @param[in] job\n- * Pointer to job descriptor.\n+ * @param[in] flow\n+ * Pointer to flow structure.\n+ * @param[in] ap\n+ * Pointer to container for temporarily constructed actions' parameters.\n * @param[in] hw_acts\n * Pointer to translated actions from template.\n * @param[in] it_idx\n@@ -2910,7 +2912,8 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,\n */\n static __rte_always_inline int\n flow_hw_actions_construct(struct rte_eth_dev *dev,\n-\t\t\t struct mlx5_hw_q_job *job,\n+\t\t\t struct rte_flow_hw *flow,\n+\t\t\t struct mlx5_flow_hw_action_params *ap,\n \t\t\t const struct mlx5_hw_action_template *hw_at,\n \t\t\t const uint8_t it_idx,\n \t\t\t const struct rte_flow_action actions[],\n@@ -2920,7 +2923,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_mtr_pool *pool = priv->hws_mpool;\n-\tstruct rte_flow_template_table *table = job->flow->table;\n+\tstruct rte_flow_template_table *table = flow->table;\n \tstruct mlx5_action_construct_data *act_data;\n \tconst struct rte_flow_actions_template *at = hw_at->action_template;\n \tconst struct mlx5_hw_actions *hw_acts = &hw_at->acts;\n@@ -2931,8 +2934,6 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \tconst struct rte_flow_action_ethdev *port_action = NULL;\n \tconst struct rte_flow_action_meter *meter = NULL;\n \tconst struct rte_flow_action_age *age = NULL;\n-\tuint8_t *buf = job->encap_data;\n-\tuint8_t *push_buf = job->push_data;\n \tstruct rte_flow_attr attr = {\n \t\t\t.ingress = 1,\n \t};\n@@ -2957,17 +2958,17 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \tif (hw_acts->mhdr && hw_acts->mhdr->mhdr_cmds_num > 0 && !hw_acts->mhdr->shared) {\n \t\tuint16_t pos = hw_acts->mhdr->pos;\n \n-\t\tmp_segment = mlx5_multi_pattern_segment_find(table, job->flow->res_idx);\n+\t\tmp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);\n \t\tif (!mp_segment || !mp_segment->mhdr_action)\n \t\t\treturn -1;\n \t\trule_acts[pos].action = mp_segment->mhdr_action;\n \t\t/* offset is relative to DR action */\n \t\trule_acts[pos].modify_header.offset =\n-\t\t\t\t\tjob->flow->res_idx - mp_segment->head_index;\n+\t\t\t\t\tflow->res_idx - mp_segment->head_index;\n \t\trule_acts[pos].modify_header.data =\n-\t\t\t\t\t(uint8_t *)job->mhdr_cmd;\n-\t\trte_memcpy(job->mhdr_cmd, hw_acts->mhdr->mhdr_cmds,\n-\t\t\t sizeof(*job->mhdr_cmd) * hw_acts->mhdr->mhdr_cmds_num);\n+\t\t\t\t\t(uint8_t *)ap->mhdr_cmd;\n+\t\trte_memcpy(ap->mhdr_cmd, hw_acts->mhdr->mhdr_cmds,\n+\t\t\t sizeof(*ap->mhdr_cmd) * hw_acts->mhdr->mhdr_cmds_num);\n \t}\n \tLIST_FOREACH(act_data, &hw_acts->act_list, next) {\n \t\tuint32_t jump_group;\n@@ -3000,7 +3001,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ACTION_TYPE_INDIRECT:\n \t\t\tif (flow_hw_shared_action_construct\n \t\t\t\t\t(dev, queue, action, table, it_idx,\n-\t\t\t\t\t at->action_flags, job->flow,\n+\t\t\t\t\t at->action_flags, flow,\n \t\t\t\t\t &rule_acts[act_data->action_dst]))\n \t\t\t\treturn -1;\n \t\t\tbreak;\n@@ -3025,8 +3026,8 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\treturn -1;\n \t\t\trule_acts[act_data->action_dst].action =\n \t\t\t(!!attr.group) ? jump->hws_action : jump->root_action;\n-\t\t\tjob->flow->jump = jump;\n-\t\t\tjob->flow->fate_type = MLX5_FLOW_FATE_JUMP;\n+\t\t\tflow->jump = jump;\n+\t\t\tflow->fate_type = MLX5_FLOW_FATE_JUMP;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RSS:\n \t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n@@ -3036,8 +3037,8 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\tif (!hrxq)\n \t\t\t\treturn -1;\n \t\t\trule_acts[act_data->action_dst].action = hrxq->action;\n-\t\t\tjob->flow->hrxq = hrxq;\n-\t\t\tjob->flow->fate_type = MLX5_FLOW_FATE_QUEUE;\n+\t\t\tflow->hrxq = hrxq;\n+\t\t\tflow->fate_type = MLX5_FLOW_FATE_QUEUE;\n \t\t\tbreak;\n \t\tcase MLX5_RTE_FLOW_ACTION_TYPE_RSS:\n \t\t\titem_flags = table->its[it_idx]->item_flags;\n@@ -3049,38 +3050,37 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:\n \t\t\tenc_item = ((const struct rte_flow_action_vxlan_encap *)\n \t\t\t\t action->conf)->definition;\n-\t\t\tif (flow_dv_convert_encap_data(enc_item, buf, &encap_len, NULL))\n+\t\t\tif (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))\n \t\t\t\treturn -1;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:\n \t\t\tenc_item = ((const struct rte_flow_action_nvgre_encap *)\n \t\t\t\t action->conf)->definition;\n-\t\t\tif (flow_dv_convert_encap_data(enc_item, buf, &encap_len, NULL))\n+\t\t\tif (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL))\n \t\t\t\treturn -1;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n \t\t\traw_encap_data =\n \t\t\t\t(const struct rte_flow_action_raw_encap *)\n \t\t\t\t action->conf;\n-\t\t\trte_memcpy((void *)buf, raw_encap_data->data, act_data->encap.len);\n-\t\t\tMLX5_ASSERT(raw_encap_data->size ==\n-\t\t\t\t act_data->encap.len);\n+\t\t\trte_memcpy(ap->encap_data, raw_encap_data->data, act_data->encap.len);\n+\t\t\tMLX5_ASSERT(raw_encap_data->size == act_data->encap.len);\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_IPV6_EXT_PUSH:\n \t\t\tipv6_push =\n \t\t\t\t(const struct rte_flow_action_ipv6_ext_push *)action->conf;\n-\t\t\trte_memcpy((void *)push_buf, ipv6_push->data,\n+\t\t\trte_memcpy(ap->ipv6_push_data, ipv6_push->data,\n \t\t\t\t act_data->ipv6_ext.len);\n \t\t\tMLX5_ASSERT(ipv6_push->size == act_data->ipv6_ext.len);\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:\n \t\t\tif (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)\n-\t\t\t\tret = flow_hw_set_vlan_vid_construct(dev, job,\n+\t\t\t\tret = flow_hw_set_vlan_vid_construct(dev, ap->mhdr_cmd,\n \t\t\t\t\t\t\t\t act_data,\n \t\t\t\t\t\t\t\t hw_acts,\n \t\t\t\t\t\t\t\t action);\n \t\t\telse\n-\t\t\t\tret = flow_hw_modify_field_construct(job,\n+\t\t\t\tret = flow_hw_modify_field_construct(ap->mhdr_cmd,\n \t\t\t\t\t\t\t\t act_data,\n \t\t\t\t\t\t\t\t hw_acts,\n \t\t\t\t\t\t\t\t action);\n@@ -3116,8 +3116,8 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\trule_acts[act_data->action_dst + 1].action =\n \t\t\t\t\t(!!attr.group) ? jump->hws_action :\n \t\t\t\t\t\t\t jump->root_action;\n-\t\t\tjob->flow->jump = jump;\n-\t\t\tjob->flow->fate_type = MLX5_FLOW_FATE_JUMP;\n+\t\t\tflow->jump = jump;\n+\t\t\tflow->fate_type = MLX5_FLOW_FATE_JUMP;\n \t\t\tif (mlx5_aso_mtr_wait(priv->sh, MLX5_HW_INV_QUEUE, aso_mtr))\n \t\t\t\treturn -1;\n \t\t\tbreak;\n@@ -3131,11 +3131,11 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t */\n \t\t\tage_idx = mlx5_hws_age_action_create(priv, queue, 0,\n \t\t\t\t\t\t\t age,\n-\t\t\t\t\t\t\t job->flow->res_idx,\n+\t\t\t\t\t\t\t flow->res_idx,\n \t\t\t\t\t\t\t error);\n \t\t\tif (age_idx == 0)\n \t\t\t\treturn -rte_errno;\n-\t\t\tjob->flow->age_idx = age_idx;\n+\t\t\tflow->age_idx = age_idx;\n \t\t\tif (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)\n \t\t\t\t/*\n \t\t\t\t * When AGE uses indirect counter, no need to\n@@ -3158,7 +3158,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\t );\n \t\t\tif (ret != 0)\n \t\t\t\treturn ret;\n-\t\t\tjob->flow->cnt_id = cnt_id;\n+\t\t\tflow->cnt_id = cnt_id;\n \t\t\tbreak;\n \t\tcase MLX5_RTE_FLOW_ACTION_TYPE_COUNT:\n \t\t\tret = mlx5_hws_cnt_pool_get_action_offset\n@@ -3169,7 +3169,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\t );\n \t\t\tif (ret != 0)\n \t\t\t\treturn ret;\n-\t\t\tjob->flow->cnt_id = act_data->shared_counter.id;\n+\t\t\tflow->cnt_id = act_data->shared_counter.id;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_CONNTRACK:\n \t\t\tct_idx = MLX5_INDIRECT_ACTION_IDX_GET(action->conf);\n@@ -3196,8 +3196,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t */\n \t\t\tret = flow_hw_meter_mark_compile(dev,\n \t\t\t\tact_data->action_dst, action,\n-\t\t\t\trule_acts, &job->flow->mtr_id,\n-\t\t\t\tMLX5_HW_INV_QUEUE, error);\n+\t\t\t\trule_acts, &flow->mtr_id, MLX5_HW_INV_QUEUE, error);\n \t\t\tif (ret != 0)\n \t\t\t\treturn ret;\n \t\t\tbreak;\n@@ -3207,9 +3206,9 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t}\n \tif (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) {\n \t\tif (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE) {\n-\t\t\tage_idx = job->flow->age_idx & MLX5_HWS_AGE_IDX_MASK;\n+\t\t\tage_idx = flow->age_idx & MLX5_HWS_AGE_IDX_MASK;\n \t\t\tif (mlx5_hws_cnt_age_get(priv->hws_cpool,\n-\t\t\t\t\t\t job->flow->cnt_id) != age_idx)\n+\t\t\t\t\t\t flow->cnt_id) != age_idx)\n \t\t\t\t/*\n \t\t\t\t * This is first use of this indirect counter\n \t\t\t\t * for this indirect AGE, need to increase the\n@@ -3221,7 +3220,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t * Update this indirect counter the indirect/direct AGE in which\n \t\t * using it.\n \t\t */\n-\t\tmlx5_hws_cnt_age_set(priv->hws_cpool, job->flow->cnt_id,\n+\t\tmlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id,\n \t\t\t\t age_idx);\n \t}\n \tif (hw_acts->encap_decap && !hw_acts->encap_decap->shared) {\n@@ -3231,21 +3230,21 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\tif (ix < 0)\n \t\t\treturn -1;\n \t\tif (!mp_segment)\n-\t\t\tmp_segment = mlx5_multi_pattern_segment_find(table, job->flow->res_idx);\n+\t\t\tmp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx);\n \t\tif (!mp_segment || !mp_segment->reformat_action[ix])\n \t\t\treturn -1;\n \t\tra->action = mp_segment->reformat_action[ix];\n \t\t/* reformat offset is relative to selected DR action */\n-\t\tra->reformat.offset = job->flow->res_idx - mp_segment->head_index;\n-\t\tra->reformat.data = buf;\n+\t\tra->reformat.offset = flow->res_idx - mp_segment->head_index;\n+\t\tra->reformat.data = ap->encap_data;\n \t}\n \tif (hw_acts->push_remove && !hw_acts->push_remove->shared) {\n \t\trule_acts[hw_acts->push_remove_pos].ipv6_ext.offset =\n-\t\t\t\tjob->flow->res_idx - 1;\n-\t\trule_acts[hw_acts->push_remove_pos].ipv6_ext.header = push_buf;\n+\t\t\t\tflow->res_idx - 1;\n+\t\trule_acts[hw_acts->push_remove_pos].ipv6_ext.header = ap->ipv6_push_data;\n \t}\n \tif (mlx5_hws_cnt_id_valid(hw_acts->cnt_id))\n-\t\tjob->flow->cnt_id = hw_acts->cnt_id;\n+\t\tflow->cnt_id = hw_acts->cnt_id;\n \treturn 0;\n }\n \n@@ -3345,6 +3344,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t\t.burst = attr->postpone,\n \t};\n \tstruct mlx5dr_rule_action *rule_acts;\n+\tstruct mlx5_flow_hw_action_params ap;\n \tstruct rte_flow_hw *flow = NULL;\n \tstruct mlx5_hw_q_job *job = NULL;\n \tconst struct rte_flow_item *rule_items;\n@@ -3401,7 +3401,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t * No need to copy and contrust a new \"actions\" list based on the\n \t * user's input, in order to save the cost.\n \t */\n-\tif (flow_hw_actions_construct(dev, job,\n+\tif (flow_hw_actions_construct(dev, flow, &ap,\n \t\t\t\t &table->ats[action_template_index],\n \t\t\t\t pattern_template_index, actions,\n \t\t\t\t rule_acts, queue, error)) {\n@@ -3493,6 +3493,7 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,\n \t\t.burst = attr->postpone,\n \t};\n \tstruct mlx5dr_rule_action *rule_acts;\n+\tstruct mlx5_flow_hw_action_params ap;\n \tstruct rte_flow_hw *flow = NULL;\n \tstruct mlx5_hw_q_job *job = NULL;\n \tuint32_t flow_idx = 0;\n@@ -3545,7 +3546,7 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,\n \t * No need to copy and contrust a new \"actions\" list based on the\n \t * user's input, in order to save the cost.\n \t */\n-\tif (flow_hw_actions_construct(dev, job,\n+\tif (flow_hw_actions_construct(dev, flow, &ap,\n \t\t\t\t &table->ats[action_template_index],\n \t\t\t\t 0, actions, rule_acts, queue, error)) {\n \t\trte_errno = EINVAL;\n@@ -3627,6 +3628,7 @@ flow_hw_async_flow_update(struct rte_eth_dev *dev,\n \t\t.burst = attr->postpone,\n \t};\n \tstruct mlx5dr_rule_action *rule_acts;\n+\tstruct mlx5_flow_hw_action_params ap;\n \tstruct rte_flow_hw *of = (struct rte_flow_hw *)flow;\n \tstruct rte_flow_hw *nf;\n \tstruct rte_flow_template_table *table = of->table;\n@@ -3679,7 +3681,7 @@ flow_hw_async_flow_update(struct rte_eth_dev *dev,\n \t * No need to copy and contrust a new \"actions\" list based on the\n \t * user's input, in order to save the cost.\n \t */\n-\tif (flow_hw_actions_construct(dev, job,\n+\tif (flow_hw_actions_construct(dev, nf, &ap,\n \t\t\t\t &table->ats[action_template_index],\n \t\t\t\t nf->mt_idx, actions,\n \t\t\t\t rule_acts, queue, error)) {\n@@ -6611,7 +6613,7 @@ flow_hw_set_vlan_vid(struct rte_eth_dev *dev,\n \n static __rte_always_inline int\n flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,\n-\t\t\t struct mlx5_hw_q_job *job,\n+\t\t\t struct mlx5_modification_cmd *mhdr_cmd,\n \t\t\t struct mlx5_action_construct_data *act_data,\n \t\t\t const struct mlx5_hw_actions *hw_acts,\n \t\t\t const struct rte_flow_action *action)\n@@ -6639,8 +6641,7 @@ flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,\n \t\t.conf = &conf\n \t};\n \n-\treturn flow_hw_modify_field_construct(job, act_data, hw_acts,\n-\t\t\t\t\t &modify_action);\n+\treturn flow_hw_modify_field_construct(mhdr_cmd, act_data, hw_acts, &modify_action);\n }\n \n static int\n@@ -9990,10 +9991,6 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t}\n \t\tmem_size += (sizeof(struct mlx5_hw_q_job *) +\n \t\t\t sizeof(struct mlx5_hw_q_job) +\n-\t\t\t sizeof(uint8_t) * MLX5_ENCAP_MAX_LEN +\n-\t\t\t sizeof(uint8_t) * MLX5_PUSH_MAX_LEN +\n-\t\t\t sizeof(struct mlx5_modification_cmd) *\n-\t\t\t MLX5_MHDR_MAX_CMD +\n \t\t\t sizeof(struct rte_flow_item) *\n \t\t\t MLX5_HW_MAX_ITEMS +\n \t\t\t\tsizeof(struct rte_flow_hw)) *\n@@ -10006,8 +10003,6 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\tgoto err;\n \t}\n \tfor (i = 0; i < nb_q_updated; i++) {\n-\t\tuint8_t *encap = NULL, *push = NULL;\n-\t\tstruct mlx5_modification_cmd *mhdr_cmd = NULL;\n \t\tstruct rte_flow_item *items = NULL;\n \t\tstruct rte_flow_hw *upd_flow = NULL;\n \n@@ -10021,20 +10016,11 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\t\t&job[_queue_attr[i - 1]->size - 1].upd_flow[1];\n \t\tjob = (struct mlx5_hw_q_job *)\n \t\t &priv->hw_q[i].job[_queue_attr[i]->size];\n-\t\tmhdr_cmd = (struct mlx5_modification_cmd *)\n-\t\t\t &job[_queue_attr[i]->size];\n-\t\tencap = (uint8_t *)\n-\t\t\t &mhdr_cmd[_queue_attr[i]->size * MLX5_MHDR_MAX_CMD];\n-\t\tpush = (uint8_t *)\n-\t\t\t &encap[_queue_attr[i]->size * MLX5_ENCAP_MAX_LEN];\n \t\titems = (struct rte_flow_item *)\n-\t\t\t &push[_queue_attr[i]->size * MLX5_PUSH_MAX_LEN];\n+\t\t\t &job[_queue_attr[i]->size];\n \t\tupd_flow = (struct rte_flow_hw *)\n \t\t\t&items[_queue_attr[i]->size * MLX5_HW_MAX_ITEMS];\n \t\tfor (j = 0; j < _queue_attr[i]->size; j++) {\n-\t\t\tjob[j].mhdr_cmd = &mhdr_cmd[j * MLX5_MHDR_MAX_CMD];\n-\t\t\tjob[j].encap_data = &encap[j * MLX5_ENCAP_MAX_LEN];\n-\t\t\tjob[j].push_data = &push[j * MLX5_PUSH_MAX_LEN];\n \t\t\tjob[j].items = &items[j * MLX5_HW_MAX_ITEMS];\n \t\t\tjob[j].upd_flow = &upd_flow[j];\n \t\t\tpriv->hw_q[i].job[j] = &job[j];\n", "prefixes": [ "05/11" ] }