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GET /api/patches/137372/?format=api
{ "id": 137372, "url": "http://patches.dpdk.org/api/patches/137372/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240227183555.3932711-3-amitprakashs@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240227183555.3932711-3-amitprakashs@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240227183555.3932711-3-amitprakashs@marvell.com", "date": "2024-02-27T18:35:53", "name": "[v10,2/4] app/dma-perf: add PCI device support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8bb66901040b1fb77413ea45cc52033ee8fcb7f6", "submitter": { "id": 2699, "url": "http://patches.dpdk.org/api/people/2699/?format=api", "name": "Amit Prakash Shukla", "email": "amitprakashs@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240227183555.3932711-3-amitprakashs@marvell.com/mbox/", "series": [ { "id": 31255, "url": "http://patches.dpdk.org/api/series/31255/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31255", "date": "2024-02-27T18:35:51", "name": "PCI Dev and SG copy support", "version": 10, "mbox": "http://patches.dpdk.org/series/31255/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137372/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/137372/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3B0D443C06;\n\tTue, 27 Feb 2024 20:08:54 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C4D3740279;\n\tTue, 27 Feb 2024 20:08:53 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id BDD4340150\n for <dev@dpdk.org>; Tue, 27 Feb 2024 20:08:51 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 41RFh1TC005683; Tue, 27 Feb 2024 11:08:51 -0800", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3whjm693t2-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 27 Feb 2024 11:08:50 -0800 (PST)", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Tue, 27 Feb\n 2024 11:08:49 -0800", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id\n 15.0.1497.48; Tue, 27 Feb 2024 11:08:49 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend\n Transport; Tue, 27 Feb 2024 11:08:49 -0800", "from cavium-OptiPlex-5090-BM14.. (unknown [10.28.36.157])\n by maili.marvell.com (Postfix) with ESMTP id 65F1E3F7095;\n Tue, 27 Feb 2024 10:38:14 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=m8eqxVaz/wm7al2DrY2rg3IzDuOZWgOgGYblqwZNfJI=; b=jxy\n Dz0DJ5j/IOIW5gmhYaJh2axxAH58DeQ0n31xusA6915VsqUf1UYl/gs7PCeLe00p\n rWXFA5IqwvPIXaPUQsufDxxooQYeP7j87x2u5H7aBlhD0Oz/uUATR0BLnQGseGBW\n nTCpA7OwmwvqD0ouExzollhbyex4fK3NIqCWCFQhJQumiij6Fow1QvqdvTf30W5J\n kFTIMTB9v5TWHro5+7B0prceyndb2g+8cC20mVyLdhEx8zl5GF6rDLpqkIQSeOBw\n IUWlDmAd1OYpdajLU7TgOHCBfQeN8glJ6CLyQ3YGvUwiLkSeL79Z8N46vNnEcpjX\n hhUdXjcBhHTe09Y7Xgw==", "From": "Amit Prakash Shukla <amitprakashs@marvell.com>", "To": "Cheng Jiang <honest.jiang@foxmail.com>, Chengwen Feng\n <fengchengwen@huawei.com>", "CC": "<dev@dpdk.org>, <jerinj@marvell.com>, <anoobj@marvell.com>, Kevin Laatz\n <kevin.laatz@intel.com>, Bruce Richardson <bruce.richardson@intel.com>,\n \"Pavan Nikhilesh\" <pbhagavatula@marvell.com>, Gowrishankar Muthukrishnan\n <gmuthukrishn@marvell.com>, Amit Prakash Shukla <amitprakashs@marvell.com>", "Subject": "[PATCH v10 2/4] app/dma-perf: add PCI device support", "Date": "Wed, 28 Feb 2024 00:05:53 +0530", "Message-ID": "<20240227183555.3932711-3-amitprakashs@marvell.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240227183555.3932711-1-amitprakashs@marvell.com>", "References": "<20240227160031.3931694-1-amitprakashs@marvell.com>\n <20240227183555.3932711-1-amitprakashs@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "u-iRx1TlnyfWsn4jcOKYIkGavzoY8b0j", "X-Proofpoint-GUID": "u-iRx1TlnyfWsn4jcOKYIkGavzoY8b0j", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-02-27_06,2024-02-27_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support to test performance for \"device to memory\" and\n\"memory to device\" data transfer.\n\nSigned-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>\nAcked-by: Anoob Joseph <anoobj@marvell.com>\nAcked-by: Chengwen Feng <fengchengwen@huawei.com>\n---\nv10:\n- PCI config parsing using kvargs.\n\n app/test-dma-perf/benchmark.c | 117 ++++++++++++++++++++++++++++++----\n app/test-dma-perf/config.ini | 33 ++++++++++\n app/test-dma-perf/main.c | 77 ++++++++++++++++++++++\n app/test-dma-perf/main.h | 7 ++\n 4 files changed, 222 insertions(+), 12 deletions(-)", "diff": "diff --git a/app/test-dma-perf/benchmark.c b/app/test-dma-perf/benchmark.c\nindex 9b1f58c78c..4370d71134 100644\n--- a/app/test-dma-perf/benchmark.c\n+++ b/app/test-dma-perf/benchmark.c\n@@ -127,17 +127,54 @@ cache_flush_buf(__rte_unused struct rte_mbuf **array,\n #endif\n }\n \n+static int\n+vchan_data_populate(uint32_t dev_id, struct rte_dma_vchan_conf *qconf,\n+\t\t struct test_configure *cfg)\n+{\n+\tstruct rte_dma_info info;\n+\n+\tqconf->direction = cfg->transfer_dir;\n+\n+\trte_dma_info_get(dev_id, &info);\n+\tif (!(RTE_BIT64(qconf->direction) & info.dev_capa))\n+\t\treturn -1;\n+\n+\tqconf->nb_desc = cfg->ring_size.cur;\n+\n+\tswitch (qconf->direction) {\n+\tcase RTE_DMA_DIR_MEM_TO_DEV:\n+\t\tqconf->dst_port.pcie.vfen = 1;\n+\t\tqconf->dst_port.port_type = RTE_DMA_PORT_PCIE;\n+\t\tqconf->dst_port.pcie.coreid = cfg->vchan_dev.port.pcie.coreid;\n+\t\tqconf->dst_port.pcie.vfid = cfg->vchan_dev.port.pcie.vfid;\n+\t\tqconf->dst_port.pcie.pfid = cfg->vchan_dev.port.pcie.pfid;\n+\t\tbreak;\n+\tcase RTE_DMA_DIR_DEV_TO_MEM:\n+\t\tqconf->src_port.pcie.vfen = 1;\n+\t\tqconf->src_port.port_type = RTE_DMA_PORT_PCIE;\n+\t\tqconf->src_port.pcie.coreid = cfg->vchan_dev.port.pcie.coreid;\n+\t\tqconf->src_port.pcie.vfid = cfg->vchan_dev.port.pcie.vfid;\n+\t\tqconf->src_port.pcie.pfid = cfg->vchan_dev.port.pcie.pfid;\n+\t\tbreak;\n+\tcase RTE_DMA_DIR_MEM_TO_MEM:\n+\tcase RTE_DMA_DIR_DEV_TO_DEV:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* Configuration of device. */\n static void\n-configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size)\n+configure_dmadev_queue(uint32_t dev_id, struct test_configure *cfg)\n {\n \tuint16_t vchan = 0;\n \tstruct rte_dma_info info;\n \tstruct rte_dma_conf dev_config = { .nb_vchans = 1 };\n-\tstruct rte_dma_vchan_conf qconf = {\n-\t\t.direction = RTE_DMA_DIR_MEM_TO_MEM,\n-\t\t.nb_desc = ring_size\n-\t};\n+\tstruct rte_dma_vchan_conf qconf = { 0 };\n+\n+\tif (vchan_data_populate(dev_id, &qconf, cfg) != 0)\n+\t\trte_exit(EXIT_FAILURE, \"Error with vchan data populate.\\n\");\n \n \tif (rte_dma_configure(dev_id, &dev_config) != 0)\n \t\trte_exit(EXIT_FAILURE, \"Error with dma configure.\\n\");\n@@ -159,7 +196,6 @@ configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size)\n static int\n config_dmadevs(struct test_configure *cfg)\n {\n-\tuint32_t ring_size = cfg->ring_size.cur;\n \tstruct lcore_dma_map_t *ldm = &cfg->lcore_dma_map;\n \tuint32_t nb_workers = ldm->cnt;\n \tuint32_t i;\n@@ -176,7 +212,7 @@ config_dmadevs(struct test_configure *cfg)\n \t\t}\n \n \t\tldm->dma_ids[i] = dev_id;\n-\t\tconfigure_dmadev_queue(dev_id, ring_size);\n+\t\tconfigure_dmadev_queue(dev_id, cfg);\n \t\t++nb_dmadevs;\n \t}\n \n@@ -302,13 +338,23 @@ do_cpu_mem_copy(void *p)\n \treturn 0;\n }\n \n+static void\n+dummy_free_ext_buf(void *addr, void *opaque)\n+{\n+\tRTE_SET_USED(addr);\n+\tRTE_SET_USED(opaque);\n+}\n+\n static int\n setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n \t\t\tstruct rte_mbuf ***dsts)\n {\n-\tunsigned int buf_size = cfg->buf_size.cur;\n+\tstatic struct rte_mbuf_ext_shared_info *ext_buf_info;\n+\tunsigned int cur_buf_size = cfg->buf_size.cur;\n+\tunsigned int buf_size = cur_buf_size + RTE_PKTMBUF_HEADROOM;\n \tunsigned int nr_sockets;\n \tuint32_t nr_buf = cfg->nr_buf;\n+\tuint32_t i;\n \n \tnr_sockets = rte_socket_count();\n \tif (cfg->src_numa_node >= nr_sockets ||\n@@ -321,7 +367,7 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n \t\t\tnr_buf,\n \t\t\t0,\n \t\t\t0,\n-\t\t\tbuf_size + RTE_PKTMBUF_HEADROOM,\n+\t\t\tbuf_size,\n \t\t\tcfg->src_numa_node);\n \tif (src_pool == NULL) {\n \t\tPRINT_ERR(\"Error with source mempool creation.\\n\");\n@@ -332,7 +378,7 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n \t\t\tnr_buf,\n \t\t\t0,\n \t\t\t0,\n-\t\t\tbuf_size + RTE_PKTMBUF_HEADROOM,\n+\t\t\tbuf_size,\n \t\t\tcfg->dst_numa_node);\n \tif (dst_pool == NULL) {\n \t\tPRINT_ERR(\"Error with destination mempool creation.\\n\");\n@@ -361,16 +407,49 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n \t\treturn -1;\n \t}\n \n+\tif (cfg->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM ||\n+\t cfg->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV) {\n+\t\text_buf_info = rte_malloc(NULL, sizeof(struct rte_mbuf_ext_shared_info), 0);\n+\t\tif (ext_buf_info == NULL) {\n+\t\t\tprintf(\"Error: ext_buf_info malloc failed.\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tif (cfg->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM) {\n+\t\text_buf_info->free_cb = dummy_free_ext_buf;\n+\t\text_buf_info->fcb_opaque = NULL;\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+\t\t\t/* Using mbuf structure to hold remote iova address. */\n+\t\t\trte_pktmbuf_attach_extbuf((*srcs)[i], (void *)(cfg->vchan_dev.raddr +\n+\t\t\t\t\t\t (i * buf_size)), (rte_iova_t)(cfg->vchan_dev.raddr +\n+\t\t\t\t\t\t (i * buf_size)), 0, ext_buf_info);\n+\t\t\trte_mbuf_ext_refcnt_update(ext_buf_info, 1);\n+\t\t}\n+\t}\n+\n+\tif (cfg->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV) {\n+\t\text_buf_info->free_cb = dummy_free_ext_buf;\n+\t\text_buf_info->fcb_opaque = NULL;\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+\t\t\t/* Using mbuf structure to hold remote iova address. */\n+\t\t\trte_pktmbuf_attach_extbuf((*dsts)[i], (void *)(cfg->vchan_dev.raddr +\n+\t\t\t\t\t\t (i * buf_size)), (rte_iova_t)(cfg->vchan_dev.raddr +\n+\t\t\t\t\t\t (i * buf_size)), 0, ext_buf_info);\n+\t\t\trte_mbuf_ext_refcnt_update(ext_buf_info, 1);\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \n void\n mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n {\n-\tuint16_t i;\n+\tuint32_t i;\n \tuint32_t offset;\n \tunsigned int lcore_id = 0;\n-\tstruct rte_mbuf **srcs = NULL, **dsts = NULL;\n+\tstruct rte_mbuf **srcs = NULL, **dsts = NULL, **m = NULL;\n \tstruct lcore_dma_map_t *ldm = &cfg->lcore_dma_map;\n \tunsigned int buf_size = cfg->buf_size.cur;\n \tuint16_t kick_batch = cfg->kick_batch.cur;\n@@ -476,6 +555,20 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \t\t\tavg_cycles_total / nb_workers, bandwidth_total, mops_total);\n \n out:\n+\n+\tif (cfg->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM)\n+\t\tm = srcs;\n+\telse if (cfg->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV)\n+\t\tm = dsts;\n+\n+\tif (m) {\n+\t\tfor (i = 0; i < nr_buf; i++)\n+\t\t\trte_pktmbuf_detach_extbuf(m[i]);\n+\n+\t\tif (m[0]->shinfo && rte_mbuf_ext_refcnt_read(m[0]->shinfo) == 0)\n+\t\t\trte_free(m[0]->shinfo);\n+\t}\n+\n \t/* free mbufs used in the test */\n \tif (srcs != NULL)\n \t\trte_pktmbuf_free_bulk(srcs, nr_buf);\ndiff --git a/app/test-dma-perf/config.ini b/app/test-dma-perf/config.ini\nindex 4d59234b2a..9c8221025e 100644\n--- a/app/test-dma-perf/config.ini\n+++ b/app/test-dma-perf/config.ini\n@@ -38,6 +38,23 @@\n \n ; \"skip\" To skip a test-case set skip to 1.\n \n+; Parameters to be configured for data transfers from \"mem to dev\" and \"dev to mem\":\n+; ==================================================================================\n+; \"direction\" denotes the direction of data transfer. It can take 3 values:\n+; mem2mem - mem to mem transfer\n+; mem2dev - mem to dev transfer\n+; dev2mem - dev to mem transfer\n+; If not specified the default value is mem2mem transfer.\n+\n+; \"vchan_dev comma separated bus related config parameter for mem2dev and dev2mem dma transfer. Ex:\"\n+; vchan_dev=raddr=0x400000,coreid=1,pfid=2,vfid=3\n+; \"raddr\" remote iova address for mem2dev and dev2mem transfer.\n+; \"coreid\" denotes PCIe core index.\n+; \"pfid\" denotes PF-id to be used for data transfer\n+; \"vfid\" denotes VF-id of PF-id to be used for data transfer.\n+\n+; =========== End of \"mem2dev\" and \"dev2mem\" config parameters. ==============\n+\n [case1]\n type=DMA_MEM_COPY\n mem_size=10\n@@ -52,6 +69,22 @@ lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3\n eal_args=--in-memory --file-prefix=test\n \n [case2]\n+skip=1\n+type=DMA_MEM_COPY\n+direction=dev2mem\n+vchan_dev=raddr=0x200000000,coreid=1,pfid=2,vfid=3\n+mem_size=10\n+buf_size=64,4096,2,MUL\n+dma_ring_size=1024\n+kick_batch=32\n+src_numa_node=0\n+dst_numa_node=0\n+cache_flush=0\n+test_seconds=2\n+lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3\n+eal_args=--in-memory --file-prefix=test\n+\n+[case3]\n type=CPU_MEM_COPY\n mem_size=10\n buf_size=64,8192,2,MUL\ndiff --git a/app/test-dma-perf/main.c b/app/test-dma-perf/main.c\nindex e9e40e72e7..051f76a6f9 100644\n--- a/app/test-dma-perf/main.c\n+++ b/app/test-dma-perf/main.c\n@@ -16,6 +16,8 @@\n #include <rte_cfgfile.h>\n #include <rte_string_fns.h>\n #include <rte_lcore.h>\n+#include <rte_dmadev.h>\n+#include <rte_kvargs.h>\n \n #include \"main.h\"\n \n@@ -325,6 +327,28 @@ parse_entry(const char *value, struct test_configure_entry *entry)\n \treturn args_nr;\n }\n \n+static int populate_pcie_config(const char *key, const char *value, void *test)\n+{\n+\tstruct test_configure *test_case = (struct test_configure *)test;\n+\tchar *endptr;\n+\tint ret = 0;\n+\n+\tif (strcmp(key, \"raddr\") == 0)\n+\t\ttest_case->vchan_dev.raddr = strtoull(value, &endptr, 16);\n+\telse if (strcmp(key, \"coreid\") == 0)\n+\t\ttest_case->vchan_dev.port.pcie.coreid = (uint8_t)atoi(value);\n+\telse if (strcmp(key, \"vfid\") == 0)\n+\t\ttest_case->vchan_dev.port.pcie.vfid = (uint16_t)atoi(value);\n+\telse if (strcmp(key, \"pfid\") == 0)\n+\t\ttest_case->vchan_dev.port.pcie.pfid = (uint16_t)atoi(value);\n+\telse {\n+\t\tprintf(\"Invalid config param: %s\\n\", key);\n+\t\tret = -1;\n+\t}\n+\n+\treturn ret;\n+}\n+\n static uint16_t\n load_configs(const char *path)\n {\n@@ -333,9 +357,12 @@ load_configs(const char *path)\n \tstruct test_configure *test_case;\n \tchar section_name[CFG_NAME_LEN];\n \tconst char *case_type;\n+\tconst char *transfer_dir;\n \tconst char *lcore_dma;\n \tconst char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str;\n \tconst char *skip;\n+\tstruct rte_kvargs *kvlist;\n+\tconst char *vchan_dev;\n \tint args_nr, nb_vp;\n \tbool is_dma;\n \n@@ -373,6 +400,22 @@ load_configs(const char *path)\n \t\tif (strcmp(case_type, DMA_MEM_COPY) == 0) {\n \t\t\ttest_case->test_type = TEST_TYPE_DMA_MEM_COPY;\n \t\t\ttest_case->test_type_str = DMA_MEM_COPY;\n+\n+\t\t\ttransfer_dir = rte_cfgfile_get_entry(cfgfile, section_name, \"direction\");\n+\t\t\tif (transfer_dir == NULL) {\n+\t\t\t\tprintf(\"Transfer direction not configured.\"\n+\t\t\t\t\t\" Defaulting it to MEM to MEM transfer.\\n\");\n+\t\t\t\ttest_case->transfer_dir = RTE_DMA_DIR_MEM_TO_MEM;\n+\t\t\t} else {\n+\t\t\t\tif (strcmp(transfer_dir, \"mem2dev\") == 0)\n+\t\t\t\t\ttest_case->transfer_dir = RTE_DMA_DIR_MEM_TO_DEV;\n+\t\t\t\telse if (strcmp(transfer_dir, \"dev2mem\") == 0)\n+\t\t\t\t\ttest_case->transfer_dir = RTE_DMA_DIR_DEV_TO_MEM;\n+\t\t\t\telse {\n+\t\t\t\t\tprintf(\"Defaulting the test to MEM to MEM transfer\\n\");\n+\t\t\t\t\ttest_case->transfer_dir = RTE_DMA_DIR_MEM_TO_MEM;\n+\t\t\t\t}\n+\t\t\t}\n \t\t\tis_dma = true;\n \t\t} else if (strcmp(case_type, CPU_MEM_COPY) == 0) {\n \t\t\ttest_case->test_type = TEST_TYPE_CPU_MEM_COPY;\n@@ -384,6 +427,40 @@ load_configs(const char *path)\n \t\t\tcontinue;\n \t\t}\n \n+\t\tif (test_case->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV ||\n+\t\t\ttest_case->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM) {\n+\t\t\tvchan_dev = rte_cfgfile_get_entry(cfgfile, section_name, \"vchan_dev\");\n+\t\t\tif (vchan_dev == NULL) {\n+\t\t\t\tprintf(\"Transfer direction mem2dev and dev2mem\"\n+\t\t\t\t \" vhcan_dev shall be configured.\\n\");\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tkvlist = rte_kvargs_parse(vchan_dev, NULL);\n+\t\t\tif (kvlist == NULL) {\n+\t\t\t\tprintf(\"rte_kvargs_parse() error\");\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tif (rte_kvargs_process(kvlist, NULL, populate_pcie_config,\n+\t\t\t\t\t (void *)test_case) < 0) {\n+\t\t\t\tprintf(\"rte_kvargs_process() error\\n\");\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tif (!test_case->vchan_dev.raddr) {\n+\t\t\t\tprintf(\"For mem2dev and dev2mem configure raddr\\n\");\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\trte_kvargs_free(kvlist);\n+\t\t}\n+\n \t\ttest_case->src_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n \t\t\t\t\t\t\t\tsection_name, \"src_numa_node\"));\n \t\ttest_case->dst_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile,\ndiff --git a/app/test-dma-perf/main.h b/app/test-dma-perf/main.h\nindex 32670151af..745c24b7fe 100644\n--- a/app/test-dma-perf/main.h\n+++ b/app/test-dma-perf/main.h\n@@ -38,10 +38,16 @@ struct lcore_dma_map_t {\n \tuint16_t cnt;\n };\n \n+struct test_vchan_dev_config {\n+\tstruct rte_dma_port_param port;\n+\tuintptr_t raddr;\n+};\n+\n struct test_configure {\n \tbool is_valid;\n \tbool is_skip;\n \tuint8_t test_type;\n+\tuint8_t transfer_dir;\n \tconst char *test_type_str;\n \tuint16_t src_numa_node;\n \tuint16_t dst_numa_node;\n@@ -57,6 +63,7 @@ struct test_configure {\n \tuint16_t test_secs;\n \tconst char *eal_args;\n \tuint8_t scenario_id;\n+\tstruct test_vchan_dev_config vchan_dev;\n };\n \n void mem_copy_benchmark(struct test_configure *cfg, bool is_dma);\n", "prefixes": [ "v10", "2/4" ] }