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GET /api/patches/137371/?format=api
{ "id": 137371, "url": "http://patches.dpdk.org/api/patches/137371/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240227185631.3932799-1-amitprakashs@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240227185631.3932799-1-amitprakashs@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240227185631.3932799-1-amitprakashs@marvell.com", "date": "2024-02-27T18:56:30", "name": "[v10,4/4] app/dma-perf: add SG copy support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "34da213c7fa2505e81c2245d782cd93773f17fc7", "submitter": { "id": 2699, "url": "http://patches.dpdk.org/api/people/2699/?format=api", "name": "Amit Prakash Shukla", "email": "amitprakashs@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240227185631.3932799-1-amitprakashs@marvell.com/mbox/", "series": [ { "id": 31257, "url": "http://patches.dpdk.org/api/series/31257/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31257", "date": "2024-02-27T18:56:30", "name": null, "version": 10, "mbox": "http://patches.dpdk.org/series/31257/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137371/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/137371/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 720C543C06;\n\tTue, 27 Feb 2024 19:56:57 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5F64D40279;\n\tTue, 27 Feb 2024 19:56:57 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 3B90C40150\n for <dev@dpdk.org>; Tue, 27 Feb 2024 19:56:55 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 41RFh1RZ005683; Tue, 27 Feb 2024 10:56:54 -0800", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3whjm6925g-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 27 Feb 2024 10:56:54 -0800 (PST)", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Tue, 27 Feb\n 2024 10:56:52 -0800", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id\n 15.0.1497.48; Tue, 27 Feb 2024 10:56:52 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend\n Transport; Tue, 27 Feb 2024 10:56:52 -0800", "from cavium-OptiPlex-5090-BM14.. (unknown [10.28.36.157])\n by maili.marvell.com (Postfix) with ESMTP id 1FF093F713F;\n Tue, 27 Feb 2024 10:56:48 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=NRLNI0og2zd4hYRNBDjFXI7b4bOfDl5uYmK52yU5waA=; b=XP1\n 2bsDQje9u9nvqePxm621/3W8Q3C9XKNldaPIvPjOMHKhGJSZLiuhZD3P9ZQBtXYs\n gCu6xewo6NMVePzGSao+vnxfCl2NyduwKtr45dFDHtUZO2LXVgG+CNqQKbmfV4IT\n o6Eru4DHNbpPJ8yXovEOFFTeDCBfaREmug2iWR4ddEeKY1tdtiWvUI9HOQ9JULyf\n 2nRopeK9gaiE2xBhcwGHB863qqykH6OH0xXRTz4N6YkSVdWZ2+AmyLZUuFDQXOOF\n ZgPZguVVdwRa87ZuxkEJvduFvSC4hou+H4Y+C7QHzC88snlqVot4xw/50kStkvnn\n QBvvpdHLeXRngLxqWAw==", "From": "Amit Prakash Shukla <amitprakashs@marvell.com>", "To": "Cheng Jiang <honest.jiang@foxmail.com>, Chengwen Feng\n <fengchengwen@huawei.com>", "CC": "<dev@dpdk.org>, <jerinj@marvell.com>, <anoobj@marvell.com>, Kevin Laatz\n <kevin.laatz@intel.com>, Bruce Richardson <bruce.richardson@intel.com>,\n \"Pavan Nikhilesh\" <pbhagavatula@marvell.com>, Gowrishankar Muthukrishnan\n <gmuthukrishn@marvell.com>", "Subject": "[PATCH v10 4/4] app/dma-perf: add SG copy support", "Date": "Wed, 28 Feb 2024 00:26:30 +0530", "Message-ID": "<20240227185631.3932799-1-amitprakashs@marvell.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240227160031.3931694-1-amitprakashs@marvell.com>", "References": "<20240227160031.3931694-1-amitprakashs@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "cdmXBV9dDtTXLwd9cjGXg8xvX00JXpMl", "X-Proofpoint-GUID": "cdmXBV9dDtTXLwd9cjGXg8xvX00JXpMl", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-02-27_06,2024-02-27_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\n\nAdd SG copy support.\n\nSigned-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\nAcked-by: Anoob Joseph <anoobj@marvell.com>\nAcked-by: Chengwen Feng <fengchengwen@huawei.com>\n---\nv10:\n- SG config variables renamed.\n\n app/test-dma-perf/benchmark.c | 278 +++++++++++++++++++++++++++++-----\n app/test-dma-perf/config.ini | 25 ++-\n app/test-dma-perf/main.c | 34 ++++-\n app/test-dma-perf/main.h | 5 +-\n 4 files changed, 300 insertions(+), 42 deletions(-)", "diff": "diff --git a/app/test-dma-perf/benchmark.c b/app/test-dma-perf/benchmark.c\nindex 0047e2f4b8..25ed6fa6d0 100644\n--- a/app/test-dma-perf/benchmark.c\n+++ b/app/test-dma-perf/benchmark.c\n@@ -46,6 +46,10 @@ struct lcore_params {\n \tuint16_t test_secs;\n \tstruct rte_mbuf **srcs;\n \tstruct rte_mbuf **dsts;\n+\tstruct rte_dma_sge *src_sges;\n+\tstruct rte_dma_sge *dst_sges;\n+\tuint8_t src_ptrs;\n+\tuint8_t dst_ptrs;\n \tvolatile struct worker_info worker_info;\n };\n \n@@ -86,21 +90,31 @@ calc_result(uint32_t buf_size, uint32_t nr_buf, uint16_t nb_workers, uint16_t te\n }\n \n static void\n-output_result(uint8_t scenario_id, uint32_t lcore_id, char *dma_name, uint16_t ring_size,\n-\t\t\tuint16_t kick_batch, uint64_t ave_cycle, uint32_t buf_size, uint32_t nr_buf,\n-\t\t\tfloat memory, float bandwidth, float mops, bool is_dma)\n+output_result(struct test_configure *cfg, struct lcore_params *para,\n+\t\t\tuint16_t kick_batch, uint64_t ave_cycle, uint32_t buf_size,\n+\t\t\tuint32_t nr_buf, float memory, float bandwidth, float mops)\n {\n-\tif (is_dma)\n-\t\tprintf(\"lcore %u, DMA %s, DMA Ring Size: %u, Kick Batch Size: %u.\\n\",\n-\t\t\t\tlcore_id, dma_name, ring_size, kick_batch);\n-\telse\n+\tuint16_t ring_size = cfg->ring_size.cur;\n+\tuint8_t scenario_id = cfg->scenario_id;\n+\tuint32_t lcore_id = para->lcore_id;\n+\tchar *dma_name = para->dma_name;\n+\n+\tif (cfg->is_dma) {\n+\t\tprintf(\"lcore %u, DMA %s, DMA Ring Size: %u, Kick Batch Size: %u\", lcore_id,\n+\t\t dma_name, ring_size, kick_batch);\n+\t\tif (cfg->is_sg)\n+\t\t\tprintf(\" DMA src ptrs: %u, dst ptrs: %u\",\n+\t\t\t para->src_ptrs, para->dst_ptrs);\n+\t\tprintf(\".\\n\");\n+\t} else {\n \t\tprintf(\"lcore %u\\n\", lcore_id);\n+\t}\n \n \tprintf(\"Average Cycles/op: %\" PRIu64 \", Buffer Size: %u B, Buffer Number: %u, Memory: %.2lf MB, Frequency: %.3lf Ghz.\\n\",\n \t\t\tave_cycle, buf_size, nr_buf, memory, rte_get_timer_hz()/1000000000.0);\n \tprintf(\"Average Bandwidth: %.3lf Gbps, MOps: %.3lf\\n\", bandwidth, mops);\n \n-\tif (is_dma)\n+\tif (cfg->is_dma)\n \t\tsnprintf(output_str[lcore_id], MAX_OUTPUT_STR_LEN, CSV_LINE_DMA_FMT,\n \t\t\tscenario_id, lcore_id, dma_name, ring_size, kick_batch, buf_size,\n \t\t\tnr_buf, memory, ave_cycle, bandwidth, mops);\n@@ -167,7 +181,7 @@ vchan_data_populate(uint32_t dev_id, struct rte_dma_vchan_conf *qconf,\n \n /* Configuration of device. */\n static void\n-configure_dmadev_queue(uint32_t dev_id, struct test_configure *cfg)\n+configure_dmadev_queue(uint32_t dev_id, struct test_configure *cfg, uint8_t ptrs_max)\n {\n \tuint16_t vchan = 0;\n \tstruct rte_dma_info info;\n@@ -190,6 +204,10 @@ configure_dmadev_queue(uint32_t dev_id, struct test_configure *cfg)\n \t\trte_exit(EXIT_FAILURE, \"Error, no configured queues reported on device id. %u\\n\",\n \t\t\t\tdev_id);\n \n+\tif (info.max_sges < ptrs_max)\n+\t\trte_exit(EXIT_FAILURE, \"Error, DMA ptrs more than supported by device id %u.\\n\",\n+\t\t\t\tdev_id);\n+\n \tif (rte_dma_start(dev_id) != 0)\n \t\trte_exit(EXIT_FAILURE, \"Error with dma start.\\n\");\n }\n@@ -202,8 +220,12 @@ config_dmadevs(struct test_configure *cfg)\n \tuint32_t i;\n \tint dev_id;\n \tuint16_t nb_dmadevs = 0;\n+\tuint8_t ptrs_max = 0;\n \tchar *dma_name;\n \n+\tif (cfg->is_sg)\n+\t\tptrs_max = RTE_MAX(cfg->src_ptrs, cfg->dst_ptrs);\n+\n \tfor (i = 0; i < ldm->cnt; i++) {\n \t\tdma_name = ldm->dma_names[i];\n \t\tdev_id = rte_dma_get_dev_id_by_name(dma_name);\n@@ -213,7 +235,7 @@ config_dmadevs(struct test_configure *cfg)\n \t\t}\n \n \t\tldm->dma_ids[i] = dev_id;\n-\t\tconfigure_dmadev_queue(dev_id, cfg);\n+\t\tconfigure_dmadev_queue(dev_id, cfg, ptrs_max);\n \t\t++nb_dmadevs;\n \t}\n \n@@ -253,7 +275,7 @@ do_dma_submit_and_poll(uint16_t dev_id, uint64_t *async_cnt,\n }\n \n static inline int\n-do_dma_mem_copy(void *p)\n+do_dma_plain_mem_copy(void *p)\n {\n \tstruct lcore_params *para = (struct lcore_params *)p;\n \tvolatile struct worker_info *worker_info = &(para->worker_info);\n@@ -306,6 +328,65 @@ do_dma_mem_copy(void *p)\n \treturn 0;\n }\n \n+static inline int\n+do_dma_sg_mem_copy(void *p)\n+{\n+\tstruct lcore_params *para = (struct lcore_params *)p;\n+\tvolatile struct worker_info *worker_info = &(para->worker_info);\n+\tstruct rte_dma_sge *src_sges = para->src_sges;\n+\tstruct rte_dma_sge *dst_sges = para->dst_sges;\n+\tconst uint16_t kick_batch = para->kick_batch;\n+\tconst uint8_t src_ptrs = para->src_ptrs;\n+\tconst uint8_t dst_ptrs = para->dst_ptrs;\n+\tconst uint16_t dev_id = para->dev_id;\n+\tuint32_t nr_buf = para->nr_buf;\n+\tuint64_t async_cnt = 0;\n+\tuint32_t poll_cnt = 0;\n+\tuint16_t nr_cpl;\n+\tuint32_t i, j;\n+\tint ret;\n+\n+\tnr_buf /= RTE_MAX(src_ptrs, dst_ptrs);\n+\tworker_info->stop_flag = false;\n+\tworker_info->ready_flag = true;\n+\n+\twhile (!worker_info->start_flag)\n+\t\t;\n+\n+\twhile (1) {\n+\t\tj = 0;\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+dma_copy:\n+\t\t\tret = rte_dma_copy_sg(dev_id, 0,\n+\t\t\t\t&src_sges[i * src_ptrs], &dst_sges[j * dst_ptrs],\n+\t\t\t\tsrc_ptrs, dst_ptrs, 0);\n+\t\t\tif (unlikely(ret < 0)) {\n+\t\t\t\tif (ret == -ENOSPC) {\n+\t\t\t\t\tdo_dma_submit_and_poll(dev_id, &async_cnt, worker_info);\n+\t\t\t\t\tgoto dma_copy;\n+\t\t\t\t} else\n+\t\t\t\t\terror_exit(dev_id);\n+\t\t\t}\n+\t\t\tasync_cnt++;\n+\t\t\tj++;\n+\n+\t\t\tif ((async_cnt % kick_batch) == 0)\n+\t\t\t\tdo_dma_submit_and_poll(dev_id, &async_cnt, worker_info);\n+\t\t}\n+\n+\t\tif (worker_info->stop_flag)\n+\t\t\tbreak;\n+\t}\n+\n+\trte_dma_submit(dev_id, 0);\n+\twhile ((async_cnt > 0) && (poll_cnt++ < POLL_MAX)) {\n+\t\tnr_cpl = rte_dma_completed(dev_id, 0, MAX_DMA_CPL_NB, NULL, NULL);\n+\t\tasync_cnt -= nr_cpl;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static inline int\n do_cpu_mem_copy(void *p)\n {\n@@ -347,8 +428,9 @@ dummy_free_ext_buf(void *addr, void *opaque)\n }\n \n static int\n-setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n-\t\t\tstruct rte_mbuf ***dsts)\n+setup_memory_env(struct test_configure *cfg,\n+\t\t\t struct rte_mbuf ***srcs, struct rte_mbuf ***dsts,\n+\t\t\t struct rte_dma_sge **src_sges, struct rte_dma_sge **dst_sges)\n {\n \tstatic struct rte_mbuf_ext_shared_info *ext_buf_info;\n \tunsigned int cur_buf_size = cfg->buf_size.cur;\n@@ -409,8 +491,8 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n \t}\n \n \tfor (i = 0; i < nr_buf; i++) {\n-\t\tmemset(rte_pktmbuf_mtod((*srcs)[i], void *), rte_rand(), buf_size);\n-\t\tmemset(rte_pktmbuf_mtod((*dsts)[i], void *), 0, buf_size);\n+\t\tmemset(rte_pktmbuf_mtod((*srcs)[i], void *), rte_rand(), cur_buf_size);\n+\t\tmemset(rte_pktmbuf_mtod((*dsts)[i], void *), 0, cur_buf_size);\n \t}\n \n \tif (cfg->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM ||\n@@ -446,20 +528,56 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n \t\t}\n \t}\n \n+\tif (cfg->is_sg) {\n+\t\tuint8_t src_ptrs = cfg->src_ptrs;\n+\t\tuint8_t dst_ptrs = cfg->dst_ptrs;\n+\t\tuint32_t sglen_src, sglen_dst;\n+\n+\t\t*src_sges = rte_zmalloc(NULL, nr_buf * sizeof(struct rte_dma_sge),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\t\tif (*src_sges == NULL) {\n+\t\t\tprintf(\"Error: src_sges array malloc failed.\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\t*dst_sges = rte_zmalloc(NULL, nr_buf * sizeof(struct rte_dma_sge),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\t\tif (*dst_sges == NULL) {\n+\t\t\tprintf(\"Error: dst_sges array malloc failed.\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tsglen_src = cur_buf_size / src_ptrs;\n+\t\tsglen_dst = cur_buf_size / dst_ptrs;\n+\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+\t\t\t(*src_sges)[i].addr = rte_pktmbuf_iova((*srcs)[i]);\n+\t\t\t(*src_sges)[i].length = sglen_src;\n+\t\t\tif (!((i+1) % src_ptrs))\n+\t\t\t\t(*src_sges)[i].length += (cur_buf_size % src_ptrs);\n+\n+\t\t\t(*dst_sges)[i].addr = rte_pktmbuf_iova((*dsts)[i]);\n+\t\t\t(*dst_sges)[i].length = sglen_dst;\n+\t\t\tif (!((i+1) % dst_ptrs))\n+\t\t\t\t(*dst_sges)[i].length += (cur_buf_size % dst_ptrs);\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \n int\n-mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n+mem_copy_benchmark(struct test_configure *cfg)\n {\n-\tuint32_t i;\n+\tuint32_t i, j;\n \tuint32_t offset;\n \tunsigned int lcore_id = 0;\n \tstruct rte_mbuf **srcs = NULL, **dsts = NULL, **m = NULL;\n+\tstruct rte_dma_sge *src_sges = NULL, *dst_sges = NULL;\n \tstruct lcore_dma_map_t *ldm = &cfg->lcore_dma_map;\n+\tconst uint32_t mcore_id = rte_get_main_lcore();\n \tunsigned int buf_size = cfg->buf_size.cur;\n \tuint16_t kick_batch = cfg->kick_batch.cur;\n-\tuint32_t nr_buf = cfg->nr_buf = (cfg->mem_size.cur * 1024 * 1024) / (cfg->buf_size.cur * 2);\n \tuint16_t nb_workers = ldm->cnt;\n \tuint16_t test_secs = cfg->test_secs;\n \tfloat memory = 0;\n@@ -467,12 +585,32 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \tuint32_t avg_cycles_total;\n \tfloat mops, mops_total;\n \tfloat bandwidth, bandwidth_total;\n+\tuint32_t nr_sgsrc = 0, nr_sgdst = 0;\n+\tuint32_t nr_buf;\n \tint ret = 0;\n \n-\tif (setup_memory_env(cfg, &srcs, &dsts) < 0)\n+\t/* Align number of buffers according to workers count */\n+\tnr_buf = (cfg->mem_size.cur * 1024 * 1024) / (cfg->buf_size.cur * 2);\n+\tnr_buf -= (nr_buf % nb_workers);\n+\tif (cfg->is_sg) {\n+\t\tnr_buf /= nb_workers;\n+\t\tnr_buf -= nr_buf % (cfg->src_ptrs * cfg->dst_ptrs);\n+\t\tnr_buf *= nb_workers;\n+\n+\t\tif (cfg->dst_ptrs > cfg->src_ptrs) {\n+\t\t\tnr_sgsrc = (nr_buf / cfg->dst_ptrs * cfg->src_ptrs);\n+\t\t\tnr_sgdst = nr_buf;\n+\t\t} else {\n+\t\t\tnr_sgsrc = nr_buf;\n+\t\t\tnr_sgdst = (nr_buf / cfg->src_ptrs * cfg->dst_ptrs);\n+\t\t}\n+\t}\n+\n+\tcfg->nr_buf = nr_buf;\n+\tif (setup_memory_env(cfg, &srcs, &dsts, &src_sges, &dst_sges) < 0)\n \t\tgoto out;\n \n-\tif (is_dma)\n+\tif (cfg->is_dma)\n \t\tif (config_dmadevs(cfg) < 0)\n \t\t\tgoto out;\n \n@@ -486,13 +624,23 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \n \tfor (i = 0; i < nb_workers; i++) {\n \t\tlcore_id = ldm->lcores[i];\n+\t\tif (lcore_id == mcore_id) {\n+\t\t\tprintf(\"lcore parameters can not use main core id %d\\n\", mcore_id);\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tif (rte_eal_lcore_role(lcore_id) == ROLE_OFF) {\n+\t\t\tprintf(\"lcore parameters can not use offline core id %d\\n\", lcore_id);\n+\t\t\tgoto out;\n+\t\t}\n+\n \t\toffset = nr_buf / nb_workers * i;\n \t\tlcores[i] = rte_malloc(NULL, sizeof(struct lcore_params), 0);\n \t\tif (lcores[i] == NULL) {\n \t\t\tprintf(\"lcore parameters malloc failure for lcore %d\\n\", lcore_id);\n \t\t\tbreak;\n \t\t}\n-\t\tif (is_dma) {\n+\t\tif (cfg->is_dma) {\n \t\t\tlcores[i]->dma_name = ldm->dma_names[i];\n \t\t\tlcores[i]->dev_id = ldm->dma_ids[i];\n \t\t\tlcores[i]->kick_batch = kick_batch;\n@@ -506,10 +654,23 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \t\tlcores[i]->scenario_id = cfg->scenario_id;\n \t\tlcores[i]->lcore_id = lcore_id;\n \n-\t\tif (is_dma)\n-\t\t\trte_eal_remote_launch(do_dma_mem_copy, (void *)(lcores[i]), lcore_id);\n-\t\telse\n+\t\tif (cfg->is_sg) {\n+\t\t\tlcores[i]->src_ptrs = cfg->src_ptrs;\n+\t\t\tlcores[i]->dst_ptrs = cfg->dst_ptrs;\n+\t\t\tlcores[i]->src_sges = src_sges + (nr_sgsrc / nb_workers * i);\n+\t\t\tlcores[i]->dst_sges = dst_sges + (nr_sgdst / nb_workers * i);\n+\t\t}\n+\n+\t\tif (cfg->is_dma) {\n+\t\t\tif (!cfg->is_sg)\n+\t\t\t\trte_eal_remote_launch(do_dma_plain_mem_copy, (void *)(lcores[i]),\n+\t\t\t\t\tlcore_id);\n+\t\t\telse\n+\t\t\t\trte_eal_remote_launch(do_dma_sg_mem_copy, (void *)(lcores[i]),\n+\t\t\t\t\tlcore_id);\n+\t\t} else {\n \t\t\trte_eal_remote_launch(do_cpu_mem_copy, (void *)(lcores[i]), lcore_id);\n+\t\t}\n \t}\n \n \twhile (1) {\n@@ -541,13 +702,53 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \n \trte_eal_mp_wait_lcore();\n \n-\tfor (i = 0; i < (nr_buf / nb_workers) * nb_workers; i++) {\n-\t\tif (memcmp(rte_pktmbuf_mtod(srcs[i], void *),\n-\t\t\t rte_pktmbuf_mtod(dsts[i], void *),\n-\t\t\t cfg->buf_size.cur) != 0) {\n-\t\t\tprintf(\"Copy validation fails for buffer number %d\\n\", i);\n-\t\t\tret = -1;\n-\t\t\tgoto out;\n+\tif (!cfg->is_sg && cfg->transfer_dir == RTE_DMA_DIR_MEM_TO_MEM) {\n+\t\tfor (i = 0; i < (nr_buf / nb_workers) * nb_workers; i++) {\n+\t\t\tif (memcmp(rte_pktmbuf_mtod(srcs[i], void *),\n+\t\t\t\t\trte_pktmbuf_mtod(dsts[i], void *),\n+\t\t\t\t\tcfg->buf_size.cur) != 0) {\n+\t\t\t\tprintf(\"Copy validation fails for buffer number %d\\n\", i);\n+\t\t\t\tret = -1;\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t}\n+\t} else if (cfg->is_sg && cfg->transfer_dir == RTE_DMA_DIR_MEM_TO_MEM) {\n+\t\tsize_t src_remsz = buf_size % cfg->src_ptrs;\n+\t\tsize_t dst_remsz = buf_size % cfg->dst_ptrs;\n+\t\tsize_t src_sz = buf_size / cfg->src_ptrs;\n+\t\tsize_t dst_sz = buf_size / cfg->dst_ptrs;\n+\t\tuint8_t src[buf_size], dst[buf_size];\n+\t\tuint8_t *sbuf, *dbuf, *ptr;\n+\n+\t\tfor (i = 0; i < (nr_buf / RTE_MAX(cfg->src_ptrs, cfg->dst_ptrs)); i++) {\n+\t\t\tsbuf = src;\n+\t\t\tdbuf = dst;\n+\t\t\tptr = NULL;\n+\n+\t\t\tfor (j = 0; j < cfg->src_ptrs; j++) {\n+\t\t\t\tptr = rte_pktmbuf_mtod(srcs[i * cfg->src_ptrs + j], uint8_t *);\n+\t\t\t\tmemcpy(sbuf, ptr, src_sz);\n+\t\t\t\tsbuf += src_sz;\n+\t\t\t}\n+\n+\t\t\tif (src_remsz)\n+\t\t\t\tmemcpy(sbuf, ptr + src_sz, src_remsz);\n+\n+\t\t\tfor (j = 0; j < cfg->dst_ptrs; j++) {\n+\t\t\t\tptr = rte_pktmbuf_mtod(dsts[i * cfg->dst_ptrs + j], uint8_t *);\n+\t\t\t\tmemcpy(dbuf, ptr, dst_sz);\n+\t\t\t\tdbuf += dst_sz;\n+\t\t\t}\n+\n+\t\t\tif (dst_remsz)\n+\t\t\t\tmemcpy(dbuf, ptr + dst_sz, dst_remsz);\n+\n+\t\t\tif (memcmp(src, dst, buf_size) != 0) {\n+\t\t\t\tprintf(\"SG Copy validation fails for buffer number %d\\n\",\n+\t\t\t\t\ti * cfg->src_ptrs);\n+\t\t\t\tret = -1;\n+\t\t\t\tgoto out;\n+\t\t\t}\n \t\t}\n \t}\n \n@@ -558,10 +759,8 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \t\tcalc_result(buf_size, nr_buf, nb_workers, test_secs,\n \t\t\tlcores[i]->worker_info.test_cpl,\n \t\t\t&memory, &avg_cycles, &bandwidth, &mops);\n-\t\toutput_result(cfg->scenario_id, lcores[i]->lcore_id,\n-\t\t\t\t\tlcores[i]->dma_name, cfg->ring_size.cur, kick_batch,\n-\t\t\t\t\tavg_cycles, buf_size, nr_buf / nb_workers, memory,\n-\t\t\t\t\tbandwidth, mops, is_dma);\n+\t\toutput_result(cfg, lcores[i], kick_batch, avg_cycles, buf_size,\n+\t\t\tnr_buf / nb_workers, memory, bandwidth, mops);\n \t\tmops_total += mops;\n \t\tbandwidth_total += bandwidth;\n \t\tavg_cycles_total += avg_cycles;\n@@ -604,13 +803,20 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \trte_mempool_free(dst_pool);\n \tdst_pool = NULL;\n \n+\t/* free sges for mbufs */\n+\trte_free(src_sges);\n+\tsrc_sges = NULL;\n+\n+\trte_free(dst_sges);\n+\tdst_sges = NULL;\n+\n \t/* free the worker parameters */\n \tfor (i = 0; i < nb_workers; i++) {\n \t\trte_free(lcores[i]);\n \t\tlcores[i] = NULL;\n \t}\n \n-\tif (is_dma) {\n+\tif (cfg->is_dma) {\n \t\tfor (i = 0; i < nb_workers; i++) {\n \t\t\tprintf(\"Stopping dmadev %d\\n\", ldm->dma_ids[i]);\n \t\t\trte_dma_stop(ldm->dma_ids[i]);\ndiff --git a/app/test-dma-perf/config.ini b/app/test-dma-perf/config.ini\nindex 9c8221025e..28f6c9d1db 100644\n--- a/app/test-dma-perf/config.ini\n+++ b/app/test-dma-perf/config.ini\n@@ -38,6 +38,14 @@\n \n ; \"skip\" To skip a test-case set skip to 1.\n \n+; Parameters to be configured for SG copy:\n+; ========================================\n+; \"dma_src_sge\" denotes number of source segments.\n+; \"dma_dst_sge\" denotes number of destination segments.\n+;\n+; For SG copy, both the parameters need to be configured and they are valid only\n+; when type is DMA_MEM_COPY.\n+;\n ; Parameters to be configured for data transfers from \"mem to dev\" and \"dev to mem\":\n ; ==================================================================================\n ; \"direction\" denotes the direction of data transfer. It can take 3 values:\n@@ -69,6 +77,21 @@ lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3\n eal_args=--in-memory --file-prefix=test\n \n [case2]\n+type=DMA_MEM_COPY\n+mem_size=10\n+buf_size=64,8192,2,MUL\n+dma_ring_size=1024\n+dma_src_sge=4\n+dma_dst_sge=1\n+kick_batch=32\n+src_numa_node=0\n+dst_numa_node=0\n+cache_flush=0\n+test_seconds=2\n+lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3\n+eal_args=--in-memory --file-prefix=test\n+\n+[case3]\n skip=1\n type=DMA_MEM_COPY\n direction=dev2mem\n@@ -84,7 +107,7 @@ test_seconds=2\n lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3\n eal_args=--in-memory --file-prefix=test\n \n-[case3]\n+[case4]\n type=CPU_MEM_COPY\n mem_size=10\n buf_size=64,8192,2,MUL\ndiff --git a/app/test-dma-perf/main.c b/app/test-dma-perf/main.c\nindex df05bcd7df..a27e4c9429 100644\n--- a/app/test-dma-perf/main.c\n+++ b/app/test-dma-perf/main.c\n@@ -108,10 +108,8 @@ run_test_case(struct test_configure *case_cfg)\n \n \tswitch (case_cfg->test_type) {\n \tcase TEST_TYPE_DMA_MEM_COPY:\n-\t\tret = mem_copy_benchmark(case_cfg, true);\n-\t\tbreak;\n \tcase TEST_TYPE_CPU_MEM_COPY:\n-\t\tret = mem_copy_benchmark(case_cfg, false);\n+\t\tret = mem_copy_benchmark(case_cfg);\n \t\tbreak;\n \tdefault:\n \t\tprintf(\"Unknown test type. %s\\n\", case_cfg->test_type_str);\n@@ -365,7 +363,8 @@ load_configs(const char *path)\n \tconst char *case_type;\n \tconst char *transfer_dir;\n \tconst char *lcore_dma;\n-\tconst char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str;\n+\tconst char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str,\n+\t\t*src_ptrs_str, *dst_ptrs_str;\n \tconst char *skip;\n \tstruct rte_kvargs *kvlist;\n \tconst char *vchan_dev;\n@@ -467,6 +466,7 @@ load_configs(const char *path)\n \t\t\trte_kvargs_free(kvlist);\n \t\t}\n \n+\t\ttest_case->is_dma = is_dma;\n \t\ttest_case->src_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n \t\t\t\t\t\t\t\tsection_name, \"src_numa_node\"));\n \t\ttest_case->dst_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n@@ -501,6 +501,32 @@ load_configs(const char *path)\n \t\t\t} else if (args_nr == 4)\n \t\t\t\tnb_vp++;\n \n+\t\t\tsrc_ptrs_str = rte_cfgfile_get_entry(cfgfile, section_name,\n+\t\t\t\t\t\t\t\t\"dma_src_sge\");\n+\t\t\tif (src_ptrs_str != NULL) {\n+\t\t\t\ttest_case->src_ptrs = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n+\t\t\t\t\t\t\t\tsection_name, \"dma_src_sge\"));\n+\t\t\t}\n+\n+\t\t\tdst_ptrs_str = rte_cfgfile_get_entry(cfgfile, section_name,\n+\t\t\t\t\t\t\t\t\"dma_dst_sge\");\n+\t\t\tif (dst_ptrs_str != NULL) {\n+\t\t\t\ttest_case->dst_ptrs = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n+\t\t\t\t\t\t\t\tsection_name, \"dma_dst_sge\"));\n+\t\t\t}\n+\n+\t\t\tif ((src_ptrs_str != NULL && dst_ptrs_str == NULL) ||\n+\t\t\t (src_ptrs_str == NULL && dst_ptrs_str != NULL)) {\n+\t\t\t\tprintf(\"parse dma_src_sge, dma_dst_sge error in case %d.\\n\",\n+\t\t\t\t\ti + 1);\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t} else if (src_ptrs_str != NULL && dst_ptrs_str != NULL) {\n+\t\t\t\ttest_case->is_sg = true;\n+\t\t\t} else {\n+\t\t\t\ttest_case->is_sg = false;\n+\t\t\t}\n+\n \t\t\tkick_batch_str = rte_cfgfile_get_entry(cfgfile, section_name, \"kick_batch\");\n \t\t\targs_nr = parse_entry(kick_batch_str, &test_case->kick_batch);\n \t\t\tif (args_nr < 0) {\ndiff --git a/app/test-dma-perf/main.h b/app/test-dma-perf/main.h\nindex 1123e7524a..baf149b72b 100644\n--- a/app/test-dma-perf/main.h\n+++ b/app/test-dma-perf/main.h\n@@ -53,11 +53,14 @@ struct test_configure {\n \tuint16_t dst_numa_node;\n \tuint16_t opcode;\n \tbool is_dma;\n+\tbool is_sg;\n \tstruct lcore_dma_map_t lcore_dma_map;\n \tstruct test_configure_entry mem_size;\n \tstruct test_configure_entry buf_size;\n \tstruct test_configure_entry ring_size;\n \tstruct test_configure_entry kick_batch;\n+\tuint8_t src_ptrs;\n+\tuint8_t dst_ptrs;\n \tuint8_t cache_flush;\n \tuint32_t nr_buf;\n \tuint16_t test_secs;\n@@ -66,6 +69,6 @@ struct test_configure {\n \tstruct test_vchan_dev_config vchan_dev;\n };\n \n-int mem_copy_benchmark(struct test_configure *cfg, bool is_dma);\n+int mem_copy_benchmark(struct test_configure *cfg);\n \n #endif /* MAIN_H */\n", "prefixes": [ "v10", "4/4" ] }