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GET /api/patches/137354/?format=api
{ "id": 137354, "url": "http://patches.dpdk.org/api/patches/137354/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240227135224.20066-5-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240227135224.20066-5-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240227135224.20066-5-dsosnowski@nvidia.com", "date": "2024-02-27T13:52:24", "name": "[v3,4/4] net/mlx5: remove port from conntrack handle representation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8d00480568b74bf44e3f7df3e925b046d5d2dc06", "submitter": { "id": 2386, "url": "http://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240227135224.20066-5-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 31247, "url": "http://patches.dpdk.org/api/series/31247/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31247", "date": "2024-02-27T13:52:20", "name": "net/mlx5: connection tracking changes", "version": 3, "mbox": "http://patches.dpdk.org/series/31247/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137354/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/137354/checks/", "tags": {}, "related": [], "headers": { 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"Subject": "[PATCH v3 4/4] net/mlx5: remove port from conntrack handle\n representation", "Date": "Tue, 27 Feb 2024 15:52:24 +0200", "Message-ID": "<20240227135224.20066-5-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240227135224.20066-1-dsosnowski@nvidia.com>", "References": "<20240223142320.49470-1-dsosnowski@nvidia.com>\n <20240227135224.20066-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN3PEPF0000B078:EE_|SJ0PR12MB5469:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b3075190-4d49-4848-5471-08dc379b6ea8", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", 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SFS:(13230031)(82310400014)(36860700004); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Feb 2024 13:53:09.3564 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b3075190-4d49-4848-5471-08dc379b6ea8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN3PEPF0000B078.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ0PR12MB5469", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch removes the owner port index from integer\nrepresentation of indirect action handle in mlx5 PMD for conntrack\nflow actions.\nThis index is not needed when HW Steering flow engine is enabled,\nbecause either:\n\n- port references its own indirect actions or,\n- port references indirect actions of the host port when sharing\n indirect actions was configured.\n\nIn both cases it is explicitly known which port owns the action.\nPort index, included in action handle, introduced unnecessary\nlimitation and caused undefined behavior issues when application\nused more than supported number of ports.\n\nThis patch removes the port index from indirect conntrack action handle\nrepresentation when HW steering flow engine is used.\nIt does not affect SW Steering flow engine.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 2 +-\n drivers/net/mlx5/mlx5_flow.h | 18 +++++++++++---\n drivers/net/mlx5/mlx5_flow_hw.c | 44 +++++++++++----------------------\n 3 files changed, 29 insertions(+), 35 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex db47d70b70..329b98f68f 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -815,7 +815,7 @@ Limitations\n \n - Cannot co-exist with ASO meter, ASO age action in a single flow rule.\n - Flow rules insertion rate and memory consumption need more optimization.\n- - 16 ports maximum.\n+ - 16 ports maximum (with ``dv_flow_en=1``).\n - 32M connections maximum.\n \n - Multi-thread flow insertion:\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex b4bf96cd64..187f440893 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -80,7 +80,12 @@ enum mlx5_indirect_type {\n #define MLX5_INDIRECT_ACT_CT_OWNER_SHIFT 25\n #define MLX5_INDIRECT_ACT_CT_OWNER_MASK (MLX5_INDIRECT_ACT_CT_MAX_PORT - 1)\n \n-/* 29-31: type, 25-28: owner port, 0-24: index */\n+/*\n+ * When SW steering flow engine is used, the CT action handles are encoded in a following way:\n+ * - bits 31:29 - type\n+ * - bits 28:25 - port index of the action owner\n+ * - bits 24:0 - action index\n+ */\n #define MLX5_INDIRECT_ACT_CT_GEN_IDX(owner, index) \\\n \t((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | \\\n \t (((owner) & MLX5_INDIRECT_ACT_CT_OWNER_MASK) << \\\n@@ -93,9 +98,14 @@ enum mlx5_indirect_type {\n #define MLX5_INDIRECT_ACT_CT_GET_IDX(index) \\\n \t((index) & ((1 << MLX5_INDIRECT_ACT_CT_OWNER_SHIFT) - 1))\n \n-#define MLX5_ACTION_CTX_CT_GET_IDX MLX5_INDIRECT_ACT_CT_GET_IDX\n-#define MLX5_ACTION_CTX_CT_GET_OWNER MLX5_INDIRECT_ACT_CT_GET_OWNER\n-#define MLX5_ACTION_CTX_CT_GEN_IDX MLX5_INDIRECT_ACT_CT_GEN_IDX\n+/*\n+ * When HW steering flow engine is used, the CT action handles are encoded in a following way:\n+ * - bits 31:29 - type\n+ * - bits 28:0 - action index\n+ */\n+#define MLX5_INDIRECT_ACT_HWS_CT_GEN_IDX(index) \\\n+\t((struct rte_flow_action_handle *)(uintptr_t) \\\n+\t ((MLX5_INDIRECT_ACTION_TYPE_CT << MLX5_INDIRECT_ACTION_TYPE_OFFSET) | (index)))\n \n enum mlx5_indirect_list_type {\n \tMLX5_INDIRECT_ACTION_LIST_TYPE_ERR = 0,\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 2550e0604f..e48a927bf0 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -563,7 +563,7 @@ flow_hw_ct_compile(struct rte_eth_dev *dev,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_ct_action *ct;\n \n-\tct = mlx5_ipool_get(priv->hws_ctpool->cts, MLX5_ACTION_CTX_CT_GET_IDX(idx));\n+\tct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);\n \tif (!ct || (!priv->shared_host && mlx5_aso_ct_available(priv->sh, queue, ct)))\n \t\treturn -1;\n \trule_act->action = priv->hws_ctpool->dr_action;\n@@ -2462,8 +2462,7 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_CONNTRACK:\n \t\t\tif (masks->conf) {\n-\t\t\t\tct_idx = MLX5_ACTION_CTX_CT_GET_IDX\n-\t\t\t\t\t ((uint32_t)(uintptr_t)actions->conf);\n+\t\t\t\tct_idx = MLX5_INDIRECT_ACTION_IDX_GET(actions->conf);\n \t\t\t\tif (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE, ct_idx,\n \t\t\t\t\t\t &acts->rule_acts[dr_pos]))\n \t\t\t\t\tgoto err;\n@@ -3180,8 +3179,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\tjob->flow->cnt_id = act_data->shared_counter.id;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_CONNTRACK:\n-\t\t\tct_idx = MLX5_ACTION_CTX_CT_GET_IDX\n-\t\t\t\t ((uint32_t)(uintptr_t)action->conf);\n+\t\t\tct_idx = MLX5_INDIRECT_ACTION_IDX_GET(action->conf);\n \t\t\tif (flow_hw_ct_compile(dev, queue, ct_idx,\n \t\t\t\t\t &rule_acts[act_data->action_dst]))\n \t\t\t\treturn -1;\n@@ -3796,16 +3794,14 @@ flow_hw_pull_legacy_indirect_comp(struct rte_eth_dev *dev, struct mlx5_hw_q_job\n \t\t\taso_mtr = mlx5_ipool_get(priv->hws_mpool->idx_pool, idx);\n \t\t\taso_mtr->state = ASO_METER_READY;\n \t\t} else if (type == MLX5_INDIRECT_ACTION_TYPE_CT) {\n-\t\t\tidx = MLX5_ACTION_CTX_CT_GET_IDX\n-\t\t\t((uint32_t)(uintptr_t)job->action);\n+\t\t\tidx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);\n \t\t\taso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);\n \t\t\taso_ct->state = ASO_CONNTRACK_READY;\n \t\t}\n \t} else if (job->type == MLX5_HW_Q_JOB_TYPE_QUERY) {\n \t\ttype = MLX5_INDIRECT_ACTION_TYPE_GET(job->action);\n \t\tif (type == MLX5_INDIRECT_ACTION_TYPE_CT) {\n-\t\t\tidx = MLX5_ACTION_CTX_CT_GET_IDX\n-\t\t\t((uint32_t)(uintptr_t)job->action);\n+\t\t\tidx = MLX5_INDIRECT_ACTION_IDX_GET(job->action);\n \t\t\taso_ct = mlx5_ipool_get(priv->hws_ctpool->cts, idx);\n \t\t\tmlx5_aso_ct_obj_analyze(job->query.user,\n \t\t\t\t\t\tjob->query.hw);\n@@ -10225,7 +10221,6 @@ flow_hw_conntrack_destroy(struct rte_eth_dev *dev,\n \t\t\t uint32_t idx,\n \t\t\t struct rte_flow_error *error)\n {\n-\tuint32_t ct_idx = MLX5_ACTION_CTX_CT_GET_IDX(idx);\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_ct_pool *pool = priv->hws_ctpool;\n \tstruct mlx5_aso_ct_action *ct;\n@@ -10235,7 +10230,7 @@ flow_hw_conntrack_destroy(struct rte_eth_dev *dev,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n \t\t\t\t\"CT destruction is not allowed to guest port\");\n-\tct = mlx5_ipool_get(pool->cts, ct_idx);\n+\tct = mlx5_ipool_get(pool->cts, idx);\n \tif (!ct) {\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -10244,7 +10239,7 @@ flow_hw_conntrack_destroy(struct rte_eth_dev *dev,\n \t}\n \t__atomic_store_n(&ct->state, ASO_CONNTRACK_FREE,\n \t\t\t\t __ATOMIC_RELAXED);\n-\tmlx5_ipool_free(pool->cts, ct_idx);\n+\tmlx5_ipool_free(pool->cts, idx);\n \treturn 0;\n }\n \n@@ -10257,15 +10252,13 @@ flow_hw_conntrack_query(struct rte_eth_dev *dev, uint32_t queue, uint32_t idx,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_ct_pool *pool = priv->hws_ctpool;\n \tstruct mlx5_aso_ct_action *ct;\n-\tuint32_t ct_idx;\n \n \tif (priv->shared_host)\n \t\treturn rte_flow_error_set(error, ENOTSUP,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n \t\t\t\t\"CT query is not allowed to guest port\");\n-\tct_idx = MLX5_ACTION_CTX_CT_GET_IDX(idx);\n-\tct = mlx5_ipool_get(pool->cts, ct_idx);\n+\tct = mlx5_ipool_get(pool->cts, idx);\n \tif (!ct) {\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -10293,7 +10286,6 @@ flow_hw_conntrack_update(struct rte_eth_dev *dev, uint32_t queue,\n \tstruct mlx5_aso_ct_pool *pool = priv->hws_ctpool;\n \tstruct mlx5_aso_ct_action *ct;\n \tconst struct rte_flow_action_conntrack *new_prf;\n-\tuint32_t ct_idx;\n \tint ret = 0;\n \n \tif (priv->shared_host)\n@@ -10301,8 +10293,7 @@ flow_hw_conntrack_update(struct rte_eth_dev *dev, uint32_t queue,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\tNULL,\n \t\t\t\t\"CT update is not allowed to guest port\");\n-\tct_idx = MLX5_ACTION_CTX_CT_GET_IDX(idx);\n-\tct = mlx5_ipool_get(pool->cts, ct_idx);\n+\tct = mlx5_ipool_get(pool->cts, idx);\n \tif (!ct) {\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n@@ -10363,13 +10354,6 @@ flow_hw_conntrack_create(struct rte_eth_dev *dev, uint32_t queue,\n \t\t\t\t \"CT is not enabled\");\n \t\treturn 0;\n \t}\n-\tif (dev->data->port_id >= MLX5_INDIRECT_ACT_CT_MAX_PORT) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n-\t\t\t\t \"CT supports port indexes up to \"\n-\t\t\t\t RTE_STR(MLX5_ACTION_CTX_CT_MAX_PORT));\n-\t\treturn 0;\n-\t}\n \tct = mlx5_ipool_zmalloc(pool->cts, &ct_idx);\n \tif (!ct) {\n \t\trte_flow_error_set(error, rte_errno,\n@@ -10399,8 +10383,7 @@ flow_hw_conntrack_create(struct rte_eth_dev *dev, uint32_t queue,\n \t\t\treturn 0;\n \t\t}\n \t}\n-\treturn (struct rte_flow_action_handle *)(uintptr_t)\n-\t\tMLX5_ACTION_CTX_CT_GEN_IDX(PORT_ID(priv), ct_idx);\n+\treturn MLX5_INDIRECT_ACT_HWS_CT_GEN_IDX(ct_idx);\n }\n \n /**\n@@ -10741,7 +10724,7 @@ flow_hw_action_handle_update(struct rte_eth_dev *dev, uint32_t queue,\n \tcase MLX5_INDIRECT_ACTION_TYPE_CT:\n \t\tif (ct_conf->state)\n \t\t\taso = true;\n-\t\tret = flow_hw_conntrack_update(dev, queue, update, act_idx,\n+\t\tret = flow_hw_conntrack_update(dev, queue, update, idx,\n \t\t\t\t\t job, push, error);\n \t\tbreak;\n \tcase MLX5_INDIRECT_ACTION_TYPE_METER_MARK:\n@@ -10830,7 +10813,7 @@ flow_hw_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue,\n \t\tmlx5_hws_cnt_shared_put(priv->hws_cpool, &act_idx);\n \t\tbreak;\n \tcase MLX5_INDIRECT_ACTION_TYPE_CT:\n-\t\tret = flow_hw_conntrack_destroy(dev, act_idx, error);\n+\t\tret = flow_hw_conntrack_destroy(dev, idx, error);\n \t\tbreak;\n \tcase MLX5_INDIRECT_ACTION_TYPE_METER_MARK:\n \t\taso_mtr = mlx5_ipool_get(pool->idx_pool, idx);\n@@ -11116,6 +11099,7 @@ flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,\n \tstruct mlx5_hw_q_job *job = NULL;\n \tuint32_t act_idx = (uint32_t)(uintptr_t)handle;\n \tuint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;\n+\tuint32_t idx = MLX5_INDIRECT_ACTION_IDX_GET(handle);\n \tuint32_t age_idx = act_idx & MLX5_HWS_AGE_IDX_MASK;\n \tint ret;\n \tbool push = flow_hw_action_push(attr);\n@@ -11139,7 +11123,7 @@ flow_hw_action_handle_query(struct rte_eth_dev *dev, uint32_t queue,\n \t\taso = true;\n \t\tif (job)\n \t\t\tjob->query.user = data;\n-\t\tret = flow_hw_conntrack_query(dev, queue, act_idx, data,\n+\t\tret = flow_hw_conntrack_query(dev, queue, idx, data,\n \t\t\t\t\t job, push, error);\n \t\tbreak;\n \tcase MLX5_INDIRECT_ACTION_TYPE_QUOTA:\n", "prefixes": [ "v3", "4/4" ] }