Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/13735/?format=api
{ "id": 13735, "url": "http://patches.dpdk.org/api/patches/13735/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1465944971-113413-14-git-send-email-stephen.hurd@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1465944971-113413-14-git-send-email-stephen.hurd@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1465944971-113413-14-git-send-email-stephen.hurd@broadcom.com", "date": "2016-06-14T22:55:47", "name": "[dpdk-dev,v5,14/38] bnxt: add initial Rx code implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "76be05d7158d648a1fce81b6b155af05496bf090", "submitter": { "id": 438, "url": "http://patches.dpdk.org/api/people/438/?format=api", "name": "Stephen Hurd", "email": "stephen.hurd@broadcom.com" }, "delegate": { "id": 10, "url": "http://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1465944971-113413-14-git-send-email-stephen.hurd@broadcom.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/13735/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/13735/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 21C77B44C;\n\tWed, 15 Jun 2016 00:57:56 +0200 (CEST)", "from mail-gw2-out.broadcom.com (mail-gw2-out.broadcom.com\n\t[216.31.210.63]) by dpdk.org (Postfix) with ESMTP id 124A7AD9C\n\tfor <dev@dpdk.org>; Wed, 15 Jun 2016 00:57:14 +0200 (CEST)", "from mail-irv-18.broadcom.com ([10.15.198.37])\n\tby mail-gw2-out.broadcom.com with ESMTP; 14 Jun 2016 16:17:19 -0700", "from mail-irva-12.broadcom.com (mail-irva-12.broadcom.com\n\t[10.11.16.101])\n\tby mail-irv-18.broadcom.com (Postfix) with ESMTP id 2641F82030;\n\tTue, 14 Jun 2016 15:57:10 -0700 (PDT)", "from DPDK-C1.broadcom.com (dhcp-10-13-115-104.irv.broadcom.com\n\t[10.13.115.104])\n\tby mail-irva-12.broadcom.com (Postfix) with ESMTP id 319F8A62A3;\n\tTue, 14 Jun 2016 15:57:02 -0700 (PDT)" ], "X-IronPort-AV": "E=Sophos;i=\"5.26,473,1459839600\"; d=\"scan'208\";a=\"97627313\"", "From": "Stephen Hurd <stephen.hurd@broadcom.com>", "To": "dev@dpdk.org,\n\tajit.khaparde@broadcom.com,\n\tbruce.richardson@intel.com", "Date": "Tue, 14 Jun 2016 15:55:47 -0700", "Message-Id": "<1465944971-113413-14-git-send-email-stephen.hurd@broadcom.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1465944971-113413-1-git-send-email-stephen.hurd@broadcom.com>", "References": "<1465250923-78695-1-git-send-email-stephen.hurd@broadcom.com>\n\t<1465944971-113413-1-git-send-email-stephen.hurd@broadcom.com>", "Subject": "[dpdk-dev] [PATCH v5 14/38] bnxt: add initial Rx code implementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ajit Khaparde <ajit.khaparde@broadcom.com>\n\nThis patch adds initial implementation of rx_pkt_burst() function fo Rx.\nbnxt_recv_pkts() is the top level function for doing Rx.\n\nThis patch also adds code to allocate rings in the ASIC.\n\nFor each Rx queue allocated in the PMD driver, a corresponding ring\nin hardware will be created. Every time a frame is received a Rx ring\nis selected based on the hardware configuration like RSS, MAC or VLAN,\nCOS and such. The hardware uses a completion ring to indicate the\navailability of a packet.\n\nThis patch also brings in functions like bnxt_init_one_rx_ring()\nbnxt_init_rx_ring_struct() which initializes various structures before\na Rx can begin.\n\nbnxt_init_rxbds() initializes the Rx Buffer Descriptors while\nbnxt_alloc_rx_data() allocates a buffer in the host to receive the\nincoming packet.\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nSigned-off-by: Stephen Hurd <stephen.hurd@broadcom.com>\nReviewed-by: David Christensen <david.christensen@broadcom.com>\n\n--\nv4:\nUse rte_mbuf_raw_alloc instead of the now depricated\n__rte_mbuf_raw_alloc and fix issues pointed out by checkpatch.\n\nv5:\nExpand the patch description\nReorder footer\n---\n drivers/net/bnxt/Makefile | 1 +\n drivers/net/bnxt/bnxt_ethdev.c | 3 +-\n drivers/net/bnxt/bnxt_ring.c | 61 ++---\n drivers/net/bnxt/bnxt_rxq.c | 34 ++-\n drivers/net/bnxt/bnxt_rxr.c | 341 ++++++++++++++++++++++++\n drivers/net/bnxt/bnxt_rxr.h | 62 +++++\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 474 +++++++++++++++++++++++++++++++++\n 7 files changed, 936 insertions(+), 40 deletions(-)\n create mode 100644 drivers/net/bnxt/bnxt_rxr.c\n create mode 100644 drivers/net/bnxt/bnxt_rxr.h", "diff": "diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile\nindex 0785681..4d35412 100644\n--- a/drivers/net/bnxt/Makefile\n+++ b/drivers/net/bnxt/Makefile\n@@ -54,6 +54,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_filter.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_hwrm.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_ring.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_rxq.c\n+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_rxr.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_stats.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_txq.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_txr.c\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex 4ace543..6888363 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -42,6 +42,7 @@\n #include \"bnxt.h\"\n #include \"bnxt_hwrm.h\"\n #include \"bnxt_rxq.h\"\n+#include \"bnxt_rxr.h\"\n #include \"bnxt_stats.h\"\n #include \"bnxt_txq.h\"\n #include \"bnxt_txr.h\"\n@@ -269,7 +270,7 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev)\n \t\tgoto error;\n \t}\n \teth_dev->dev_ops = &bnxt_dev_ops;\n-\t/* eth_dev->rx_pkt_burst = &bnxt_recv_pkts; */\n+\teth_dev->rx_pkt_burst = &bnxt_recv_pkts;\n \teth_dev->tx_pkt_burst = &bnxt_xmit_pkts;\n \n \trc = bnxt_alloc_hwrm_resources(bp);\ndiff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c\nindex 2645dda..f547a9e 100644\n--- a/drivers/net/bnxt/bnxt_ring.c\n+++ b/drivers/net/bnxt/bnxt_ring.c\n@@ -36,6 +36,7 @@\n #include \"bnxt.h\"\n #include \"bnxt_cpr.h\"\n #include \"bnxt_ring.h\"\n+#include \"bnxt_rxr.h\"\n #include \"bnxt_txr.h\"\n \n #include \"hsi_struct_def_dpdk.h\"\n@@ -74,8 +75,7 @@ int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,\n {\n \tstruct bnxt_ring *cp_ring = cp_ring_info->cp_ring_struct;\n \tstruct bnxt_ring *tx_ring;\n-\t/* TODO: RX ring */\n-\t/* struct bnxt_ring *rx_ring; */\n+\tstruct bnxt_ring *rx_ring;\n \tstruct rte_pci_device *pdev = bp->pdev;\n \tconst struct rte_memzone *mz = NULL;\n \tchar mz_name[RTE_MEMZONE_NAMESIZE];\n@@ -92,12 +92,9 @@ int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,\n \t\t\t\t\t\ttx_ring_struct->vmem_size) : 0;\n \n \tint rx_vmem_start = tx_vmem_start + tx_vmem_len;\n-\t/* TODO: RX ring */\n-\tint rx_vmem_len = 0;\n-\t/*\n-\t * rx_ring_info ? RTE_CACHE_LINE_ROUNDUP(rx_ring_info->\n-\t * rx_ring_struct->vmem_size) : 0;\n-\t */\n+\tint rx_vmem_len = rx_ring_info ?\n+\t\tRTE_CACHE_LINE_ROUNDUP(rx_ring_info->\n+\t\t\t\t\t\trx_ring_struct->vmem_size) : 0;\n \n \tint cp_ring_start = rx_vmem_start + rx_vmem_len;\n \tint cp_ring_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->ring_size *\n@@ -109,13 +106,9 @@ int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,\n \t\t\t\t sizeof(struct tx_bd_long)) : 0;\n \n \tint rx_ring_start = tx_ring_start + tx_ring_len;\n-\t/* TODO: RX ring */\n-\tint rx_ring_len = 0;\n-\t/*\n-\t * rx_ring_info ?\n-\t * RTE_CACHE_LINE_ROUNDUP(rx_ring_info->rx_ring_struct->ring_size *\n-\t * sizeof(struct rx_prod_pkt_bd)) : 0;\n-\t */\n+\tint rx_ring_len = rx_ring_info ?\n+\t\tRTE_CACHE_LINE_ROUNDUP(rx_ring_info->rx_ring_struct->ring_size *\n+\t\tsizeof(struct rx_prod_pkt_bd)) : 0;\n \n \tint total_alloc_len = rx_ring_start + rx_ring_len;\n \n@@ -153,26 +146,24 @@ int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,\n \t\t}\n \t}\n \n-/*\n- *\tif (rx_ring_info) {\n- *\t\trx_ring = &rx_ring_info->rx_ring_struct;\n- *\n- *\t\trx_ring->bd = ((char *)mz->addr + rx_ring_start);\n- *\t\trx_ring_info->rx_desc_ring =\n- *\t\t (struct rx_prod_pkt_bd *)rx_ring->bd;\n- *\t\trx_ring->bd_dma = mz->phys_addr + rx_ring_start;\n- *\t\trx_ring_info->rx_desc_mapping = rx_ring->bd_dma;\n- *\n- *\t\tif (!rx_ring->bd)\n- *\t\t\treturn -ENOMEM;\n- *\t\tif (rx_ring->vmem_size) {\n- *\t\t\trx_ring->vmem =\n- *\t\t\t (void **)((char *)mz->addr + rx_vmem_start);\n- *\t\t\trx_ring_info->rx_buf_ring =\n- *\t\t\t (struct bnxt_sw_rx_bd *)rx_ring->vmem;\n- *\t\t}\n- *\t}\n- */\n+\tif (rx_ring_info) {\n+\t\trx_ring = rx_ring_info->rx_ring_struct;\n+\n+\t\trx_ring->bd = ((char *)mz->addr + rx_ring_start);\n+\t\trx_ring_info->rx_desc_ring =\n+\t\t (struct rx_prod_pkt_bd *)rx_ring->bd;\n+\t\trx_ring->bd_dma = mz->phys_addr + rx_ring_start;\n+\t\trx_ring_info->rx_desc_mapping = rx_ring->bd_dma;\n+\n+\t\tif (!rx_ring->bd)\n+\t\t\treturn -ENOMEM;\n+\t\tif (rx_ring->vmem_size) {\n+\t\t\trx_ring->vmem =\n+\t\t\t (void **)((char *)mz->addr + rx_vmem_start);\n+\t\t\trx_ring_info->rx_buf_ring =\n+\t\t\t (struct bnxt_sw_rx_bd *)rx_ring->vmem;\n+\t\t}\n+\t}\n \n \tcp_ring->bd = ((char *)mz->addr + cp_ring_start);\n \tcp_ring->bd_dma = mz->phys_addr + cp_ring_start;\ndiff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c\nindex 19c0e3f..eeda631 100644\n--- a/drivers/net/bnxt/bnxt_rxq.c\n+++ b/drivers/net/bnxt/bnxt_rxq.c\n@@ -41,6 +41,7 @@\n #include \"bnxt_hwrm.h\"\n #include \"bnxt_ring.h\"\n #include \"bnxt_rxq.h\"\n+#include \"bnxt_rxr.h\"\n #include \"bnxt_vnic.h\"\n #include \"hsi_struct_def_dpdk.h\"\n \n@@ -216,7 +217,20 @@ err_out:\n \n static void bnxt_rx_queue_release_mbufs(struct bnxt_rx_queue *rxq __rte_unused)\n {\n-\t/* TODO: Requires interaction with TX ring */\n+\tstruct bnxt_sw_rx_bd *sw_ring;\n+\tuint16_t i;\n+\n+\tif (rxq) {\n+\t\tsw_ring = rxq->rx_ring->rx_buf_ring;\n+\t\tif (sw_ring) {\n+\t\t\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n+\t\t\t\tif (sw_ring[i].mbuf) {\n+\t\t\t\t\trte_pktmbuf_free_seg(sw_ring[i].mbuf);\n+\t\t\t\t\tsw_ring[i].mbuf = NULL;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n }\n \n void bnxt_free_rx_mbufs(struct bnxt *bp)\n@@ -237,7 +251,13 @@ void bnxt_rx_queue_release_op(void *rx_queue)\n \tif (rxq) {\n \t\tbnxt_rx_queue_release_mbufs(rxq);\n \n-\t\t/* TODO: Free ring and stats here */\n+\t\t/* Free RX ring hardware descriptors */\n+\t\tbnxt_free_ring(rxq->rx_ring->rx_ring_struct);\n+\n+\t\t/* Free RX completion ring hardware descriptors */\n+\t\tbnxt_free_ring(rxq->cp_ring->cp_ring_struct);\n+\n+\t\tbnxt_free_rxq_stats(rxq);\n \n \t\trte_free(rxq);\n \t}\n@@ -274,7 +294,7 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,\n \trxq->nb_rx_desc = nb_desc;\n \trxq->rx_free_thresh = rx_conf->rx_free_thresh;\n \n-\t/* TODO: Initialize ring structure */\n+\tbnxt_init_rx_ring_struct(rxq);\n \n \trxq->queue_id = queue_idx;\n \trxq->port_id = eth_dev->data->port_id;\n@@ -282,7 +302,13 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,\n \t\t\t\t0 : ETHER_CRC_LEN);\n \n \teth_dev->data->rx_queues[queue_idx] = rxq;\n-\t/* TODO: Allocate RX ring hardware descriptors */\n+\t/* Allocate RX ring hardware descriptors */\n+\tif (bnxt_alloc_rings(bp, queue_idx, NULL, rxq->rx_ring, rxq->cp_ring,\n+\t\t\t\"rxr\")) {\n+\t\tRTE_LOG(ERR, PMD, \"ring_dma_zone_reserve for rx_ring failed!\");\n+\t\tbnxt_rx_queue_release_op(rxq);\n+\t\treturn -ENOMEM;\n+\t}\n \n \treturn 0;\n }\ndiff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c\nnew file mode 100644\nindex 0000000..b02395b\n--- /dev/null\n+++ b/drivers/net/bnxt/bnxt_rxr.c\n@@ -0,0 +1,341 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) Broadcom Limited.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Broadcom Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <inttypes.h>\n+#include <stdbool.h>\n+\n+#include <rte_byteorder.h>\n+#include <rte_malloc.h>\n+#include <rte_memory.h>\n+\n+#include \"bnxt.h\"\n+#include \"bnxt_cpr.h\"\n+#include \"bnxt_ring.h\"\n+#include \"bnxt_rxr.h\"\n+#include \"bnxt_rxq.h\"\n+#include \"hsi_struct_def_dpdk.h\"\n+\n+/*\n+ * RX Ring handling\n+ */\n+\n+static inline struct rte_mbuf *__bnxt_alloc_rx_data(struct rte_mempool *mb)\n+{\n+\tstruct rte_mbuf *data;\n+\n+\tdata = rte_mbuf_raw_alloc(mb);\n+\n+\treturn data;\n+}\n+\n+static inline int bnxt_alloc_rx_data(struct bnxt_rx_queue *rxq,\n+\t\t\t\t struct bnxt_rx_ring_info *rxr,\n+\t\t\t\t uint16_t prod)\n+{\n+\tstruct rx_prod_pkt_bd *rxbd = &rxr->rx_desc_ring[prod];\n+\tstruct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];\n+\tstruct rte_mbuf *data;\n+\n+\tdata = __bnxt_alloc_rx_data(rxq->mb_pool);\n+\tif (!data)\n+\t\treturn -ENOMEM;\n+\n+\trx_buf->mbuf = data;\n+\n+\trxbd->addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR(rx_buf->mbuf));\n+\n+\treturn 0;\n+}\n+\n+static void bnxt_reuse_rx_mbuf(struct bnxt_rx_ring_info *rxr, uint16_t cons,\n+\t\t\t struct rte_mbuf *mbuf)\n+{\n+\tuint16_t prod = rxr->rx_prod;\n+\tstruct bnxt_sw_rx_bd *prod_rx_buf;\n+\tstruct rx_prod_pkt_bd *prod_bd, *cons_bd;\n+\n+\tprod_rx_buf = &rxr->rx_buf_ring[prod];\n+\n+\tprod_rx_buf->mbuf = mbuf;\n+\n+\tprod_bd = &rxr->rx_desc_ring[prod];\n+\tcons_bd = &rxr->rx_desc_ring[cons];\n+\n+\tprod_bd->addr = cons_bd->addr;\n+}\n+\n+static uint16_t bnxt_rx_pkt(struct rte_mbuf **rx_pkt,\n+\t\t\t struct bnxt_rx_queue *rxq, uint32_t *raw_cons)\n+{\n+\tstruct bnxt_cp_ring_info *cpr = rxq->cp_ring;\n+\tstruct bnxt_rx_ring_info *rxr = rxq->rx_ring;\n+\tstruct rx_pkt_cmpl *rxcmp;\n+\tstruct rx_pkt_cmpl_hi *rxcmp1;\n+\tuint32_t tmp_raw_cons = *raw_cons;\n+\tuint16_t cons, prod, cp_cons =\n+\t RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);\n+\tstruct bnxt_sw_rx_bd *rx_buf;\n+\tstruct rte_mbuf *mbuf;\n+\tint rc = 0;\n+\n+\trxcmp = (struct rx_pkt_cmpl *)\n+\t &cpr->cp_desc_ring[cp_cons];\n+\n+\ttmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);\n+\tcp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);\n+\trxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cp_cons];\n+\n+\tif (!CMP_VALID(rxcmp1, tmp_raw_cons, cpr->cp_ring_struct))\n+\t\treturn -EBUSY;\n+\n+\tprod = rxr->rx_prod;\n+\n+\t/* EW - GRO deferred to phase 3 */\n+\tcons = rxcmp->opaque;\n+\trx_buf = &rxr->rx_buf_ring[cons];\n+\tmbuf = rx_buf->mbuf;\n+\trte_prefetch0(mbuf);\n+\n+\tmbuf->nb_segs = 1;\n+\tmbuf->next = NULL;\n+\tmbuf->pkt_len = rxcmp->len;\n+\tmbuf->data_len = mbuf->pkt_len;\n+\tmbuf->port = rxq->port_id;\n+\tmbuf->ol_flags = 0;\n+\tif (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) {\n+\t\tmbuf->hash.rss = rxcmp->rss_hash;\n+\t\tmbuf->ol_flags |= PKT_RX_RSS_HASH;\n+\t} else {\n+\t\tmbuf->hash.fdir.id = rxcmp1->cfa_code;\n+\t\tmbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;\n+\t}\n+\tif (rxcmp1->flags2 & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {\n+\t\tmbuf->vlan_tci = rxcmp1->metadata &\n+\t\t\t(RX_PKT_CMPL_METADATA_VID_MASK |\n+\t\t\tRX_PKT_CMPL_METADATA_DE |\n+\t\t\tRX_PKT_CMPL_METADATA_PRI_MASK);\n+\t\tmbuf->ol_flags |= PKT_RX_VLAN_PKT;\n+\t}\n+\n+\trx_buf->mbuf = NULL;\n+\tif (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {\n+\t\t/* Re-install the mbuf back to the rx ring */\n+\t\tbnxt_reuse_rx_mbuf(rxr, cons, mbuf);\n+\n+\t\trc = -EIO;\n+\t\tgoto next_rx;\n+\t}\n+\t/*\n+\t * TODO: Redesign this....\n+\t * If the allocation fails, the packet does not get received.\n+\t * Simply returning this will result in slowly falling behind\n+\t * on the producer ring buffers.\n+\t * Instead, \"filling up\" the producer just before ringing the\n+\t * doorbell could be a better solution since it will let the\n+\t * producer ring starve until memory is available again pushing\n+\t * the drops into hardware and getting them out of the driver\n+\t * allowing recovery to a full producer ring.\n+\t *\n+\t * This could also help with cache usage by preventing per-packet\n+\t * calls in favour of a tight loop with the same function being called\n+\t * in it.\n+\t */\n+\tif (bnxt_alloc_rx_data(rxq, rxr, prod)) {\n+\t\tRTE_LOG(ERR, PMD, \"mbuf alloc failed with prod=0x%x\\n\", prod);\n+\t\trc = -ENOMEM;\n+\t\tgoto next_rx;\n+\t}\n+\n+\t/*\n+\t * All MBUFs are allocated with the same size under DPDK,\n+\t * no optimization for rx_copy_thresh\n+\t */\n+\n+\t/* AGG buf operation is deferred */\n+\n+\t/* EW - VLAN reception. Must compare against the ol_flags */\n+\n+\t*rx_pkt = mbuf;\n+next_rx:\n+\trxr->rx_prod = RING_NEXT(rxr->rx_ring_struct, prod);\n+\n+\t*raw_cons = tmp_raw_cons;\n+\n+\treturn rc;\n+}\n+\n+uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\tstruct bnxt_rx_queue *rxq = rx_queue;\n+\tstruct bnxt_cp_ring_info *cpr = rxq->cp_ring;\n+\tstruct bnxt_rx_ring_info *rxr = rxq->rx_ring;\n+\tuint32_t raw_cons = cpr->cp_raw_cons;\n+\tuint32_t cons;\n+\tint nb_rx_pkts = 0;\n+\tbool rx_event = false;\n+\tstruct rx_pkt_cmpl *rxcmp;\n+\n+\t/* Handle RX burst request */\n+\twhile (1) {\n+\t\tint rc;\n+\n+\t\tcons = RING_CMP(cpr->cp_ring_struct, raw_cons);\n+\t\trte_prefetch0(&cpr->cp_desc_ring[cons]);\n+\t\trxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];\n+\n+\t\tif (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))\n+\t\t\tbreak;\n+\n+\t\t/* TODO: Avoid magic numbers... */\n+\t\tif ((CMP_TYPE(rxcmp) & 0x30) == 0x10) {\n+\t\t\trc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);\n+\t\t\tif (likely(!rc))\n+\t\t\t\tnb_rx_pkts++;\n+\t\t\telse if (rc == -EBUSY)\t/* partial completion */\n+\t\t\t\tbreak;\n+\t\t\trx_event = true;\n+\t\t}\n+\t\traw_cons = NEXT_RAW_CMP(raw_cons);\n+\t\tif (nb_rx_pkts == nb_pkts)\n+\t\t\tbreak;\n+\t}\n+\tif (raw_cons == cpr->cp_raw_cons) {\n+\t\t/*\n+\t\t * For PMD, there is no need to keep on pushing to REARM\n+\t\t * the doorbell if there are no new completions\n+\t\t */\n+\t\treturn nb_rx_pkts;\n+\t}\n+\tcpr->cp_raw_cons = raw_cons;\n+\n+\tB_CP_DIS_DB(cpr, cpr->cp_raw_cons);\n+\tif (rx_event)\n+\t\tB_RX_DB(rxr->rx_doorbell, rxr->rx_prod);\n+\treturn nb_rx_pkts;\n+}\n+\n+void bnxt_free_rx_rings(struct bnxt *bp)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < (int)bp->rx_nr_rings; i++) {\n+\t\tstruct bnxt_rx_queue *rxq = bp->rx_queues[i];\n+\n+\t\tif (!rxq)\n+\t\t\tcontinue;\n+\n+\t\t/* TODO: free() rxq->rx_ring and rxq->rx_ring->rx_ring_struct */\n+\t\tbnxt_free_ring(rxq->rx_ring->rx_ring_struct);\n+\t\t/* TODO: free() rxq->cp_ring and rxq->cp_ring->cp_ring_struct */\n+\t\tbnxt_free_ring(rxq->cp_ring->cp_ring_struct);\n+\n+\t\trte_free(rxq);\n+\t\tbp->rx_queues[i] = NULL;\n+\t}\n+}\n+\n+void bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq)\n+{\n+\tstruct bnxt *bp = rxq->bp;\n+\tstruct bnxt_cp_ring_info *cpr;\n+\tstruct bnxt_rx_ring_info *rxr;\n+\tstruct bnxt_ring *ring;\n+\n+\trxq->rx_buf_use_size = bp->eth_dev->data->mtu +\n+\t\t\t ETHER_HDR_LEN + ETHER_CRC_LEN +\n+\t\t\t (2 * VLAN_TAG_SIZE);\n+\trxq->rx_buf_size = rxq->rx_buf_use_size + sizeof(struct rte_mbuf);\n+\n+\trxr = rxq->rx_ring;\n+\tring = rxr->rx_ring_struct;\n+\tring->ring_size = rte_align32pow2(rxq->nb_rx_desc);\n+\tring->ring_mask = ring->ring_size - 1;\n+\tring->bd = (void *)rxr->rx_desc_ring;\n+\tring->bd_dma = rxr->rx_desc_mapping;\n+\tring->vmem_size = ring->ring_size * sizeof(struct bnxt_sw_rx_bd);\n+\tring->vmem = (void **)&rxr->rx_buf_ring;\n+\n+\tcpr = rxq->cp_ring;\n+\tring = cpr->cp_ring_struct;\n+\tring->ring_size = rxr->rx_ring_struct->ring_size * 2;\n+\tring->ring_mask = ring->ring_size - 1;\n+\tring->bd = (void *)cpr->cp_desc_ring;\n+\tring->bd_dma = cpr->cp_desc_mapping;\n+\tring->vmem_size = 0;\n+\tring->vmem = NULL;\n+}\n+\n+static void bnxt_init_rxbds(struct bnxt_ring *ring, uint32_t type,\n+\t\t\t uint16_t len)\n+{\n+\tuint32_t j;\n+\tstruct rx_prod_pkt_bd *rx_bd_ring = (struct rx_prod_pkt_bd *)ring->bd;\n+\n+\tif (!rx_bd_ring)\n+\t\treturn;\n+\tfor (j = 0; j < ring->ring_size; j++) {\n+\t\trx_bd_ring[j].flags_type = type;\n+\t\trx_bd_ring[j].len = len;\n+\t\trx_bd_ring[j].opaque = j;\n+\t}\n+}\n+\n+int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq)\n+{\n+\tstruct bnxt_rx_ring_info *rxr;\n+\tstruct bnxt_ring *ring;\n+\tuint32_t prod, type;\n+\tunsigned int i;\n+\n+\ttype = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT | RX_PROD_PKT_BD_FLAGS_EOP_PAD;\n+\n+\t/* TODO: These need to be allocated */\n+\trxr = rxq->rx_ring;\n+\tring = rxr->rx_ring_struct;\n+\tbnxt_init_rxbds(ring, type, rxq->rx_buf_use_size);\n+\n+\tprod = rxr->rx_prod;\n+\tfor (i = 0; i < ring->ring_size; i++) {\n+\t\tif (bnxt_alloc_rx_data(rxq, rxr, prod) != 0) {\n+\t\t\tRTE_LOG(WARNING, PMD,\n+\t\t\t\t\"init'ed rx ring %d with %d/%d mbufs only\\n\",\n+\t\t\t\trxq->queue_id, i, ring->ring_size);\n+\t\t\tbreak;\n+\t\t}\n+\t\trxr->rx_prod = prod;\n+\t\tprod = RING_NEXT(rxr->rx_ring_struct, prod);\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h\nnew file mode 100644\nindex 0000000..95c61a0\n--- /dev/null\n+++ b/drivers/net/bnxt/bnxt_rxr.h\n@@ -0,0 +1,62 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) Broadcom Limited.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Broadcom Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _BNXT_RXR_H_\n+#define _BNXT_RXR_H_\n+\n+#define B_RX_DB(db, prod)\t\t\t\t\t\t\\\n+\t\t(*(uint32_t *)db = (DB_KEY_RX | prod))\n+\n+struct bnxt_sw_rx_bd {\n+\tstruct rte_mbuf\t\t*mbuf; /* data associated with RX descriptor */\n+};\n+\n+struct bnxt_rx_ring_info {\n+\tuint16_t\t\trx_prod;\n+\tvoid\t\t\t*rx_doorbell;\n+\n+\tstruct rx_prod_pkt_bd\t*rx_desc_ring;\n+\tstruct bnxt_sw_rx_bd\t*rx_buf_ring; /* sw ring */\n+\n+\tphys_addr_t\t\trx_desc_mapping;\n+\n+\tstruct bnxt_ring\t*rx_ring_struct;\n+};\n+\n+uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t nb_pkts);\n+void bnxt_free_rx_rings(struct bnxt *bp);\n+void bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq);\n+int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);\n+\n+#endif\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 1543f20..8b30787 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -446,6 +446,79 @@ struct tx_bd_long_hi {\n \tuint32_t cfa_meta;\n } __attribute__((packed));\n \n+/* RX Producer Packet BD (16 bytes) */\n+struct rx_prod_pkt_bd {\n+\t/* This value identifies the type of buffer descriptor. */\n+\t#define RX_PROD_PKT_BD_TYPE_MASK\t\tUINT32_C(0x3f)\n+\t#define RX_PROD_PKT_BD_TYPE_SFT\t\t\t0\n+\t\t/*\n+\t\t * Indicates that this BD is 16B long and is an RX Producer (ie.\n+\t\t * empty) buffer descriptor.\n+\t\t */\n+\t#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT\t\t(UINT32_C(0x4) << 0)\n+\t/*\n+\t * If set to 1, the packet will be placed at the address plus 2B. The 2\n+\t * Bytes of padding will be written as zero.\n+\t */\n+\t/*\n+\t * This is intended to be used when the host buffer is cache-line\n+\t * aligned to produce packets that are easy to parse in host memory\n+\t * while still allowing writes to be cache line aligned.\n+\t */\n+\t#define RX_PROD_PKT_BD_FLAGS_SOP_PAD\t\tUINT32_C(0x40)\n+\t/*\n+\t * If set to 1, the packet write will be padded out to the nearest\n+\t * cache-line with zero value padding.\n+\t */\n+\t/*\n+\t * If receive buffers start/end on cache-line boundaries, this feature\n+\t * will ensure that all data writes on the PCI bus start/end on cache\n+\t * line boundaries.\n+\t */\n+\t#define RX_PROD_PKT_BD_FLAGS_EOP_PAD\t\tUINT32_C(0x80)\n+\t/*\n+\t * This value is the number of additional buffers in the ring that\n+\t * describe the buffer space to be consumed for the this packet. If the\n+\t * value is zero, then the packet must fit within the space described by\n+\t * this BD. If this value is 1 or more, it indicates how many additional\n+\t * \"buffer\" BDs are in the ring immediately following this BD to be used\n+\t * for the same network packet. Even if the packet to be placed does not\n+\t * need all the additional buffers, they will be consumed anyway.\n+\t */\n+\t#define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK\tUINT32_C(0x300)\n+\t#define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT\t8\n+\t#define RX_PROD_PKT_BD_FLAGS_MASK\t\tUINT32_C(0xffc0)\n+\t#define RX_PROD_PKT_BD_FLAGS_SFT\t\t6\n+\tuint16_t flags_type;\n+\n+\t/*\n+\t * This is the length in Bytes of the host physical buffer where data\n+\t * for the packet may be placed in host memory.\n+\t */\n+\t/*\n+\t * While this is a Byte resolution value, it is often advantageous to\n+\t * ensure that the buffers provided end on a host cache line.\n+\t */\n+\tuint16_t len;\n+\n+\t/*\n+\t * The opaque data field is pass through to the completion and can be\n+\t * used for any data that the driver wants to associate with this\n+\t * receive buffer set.\n+\t */\n+\tuint32_t opaque;\n+\n+\t/*\n+\t * This is the host physical address where data for the packet may by\n+\t * placed in host memory.\n+\t */\n+\t/*\n+\t * While this is a Byte resolution value, it is often advantageous to\n+\t * ensure that the buffers provide start on a host cache line.\n+\t */\n+\tuint64_t addr;\n+} __attribute__((packed));\n+\n /* Completion Ring Structures */\n /* Note: This structure is used by the HWRM to communicate HWRM Error. */\n /* Base Completion Record (16 bytes) */\n@@ -611,6 +684,407 @@ struct tx_cmpl {\n \tuint32_t unused_2;\n } __attribute__((packed)) tx_cmpl_t, *ptx_cmpl_t;\n \n+/* RX Packet Completion Record (32 bytes split to 2 16-byte struct) */\n+struct rx_pkt_cmpl {\n+\t/*\n+\t * This field indicates the exact type of the completion. By convention,\n+\t * the LSB identifies the length of the record in 16B units. Even values\n+\t * indicate 16B records. Odd values indicate 32B records.\n+\t */\n+\t#define RX_PKT_CMPL_TYPE_MASK\t\t\tUINT32_C(0x3f)\n+\t#define RX_PKT_CMPL_TYPE_SFT\t\t\t0\n+\t\t/*\n+\t\t * RX L2 completion: Completion of and L2 RX packet.\n+\t\t * Length = 32B\n+\t\t */\n+\t#define RX_PKT_CMPL_TYPE_RX_L2\t\t\t(UINT32_C(0x11) << 0)\n+\t/*\n+\t * When this bit is '1', it indicates a packet that has an error of some\n+\t * type. Type of error is indicated in error_flags.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS_ERROR\t\t\tUINT32_C(0x40)\n+\t/* This field indicates how the packet was placed in the buffer. */\n+\t#define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK\tUINT32_C(0x380)\n+\t#define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT\t\t7\n+\t\t/* Normal: Packet was placed using normal algorithm. */\n+\t#define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL\t(UINT32_C(0x0) << 7)\n+\t\t/* Jumbo: Packet was placed using jumbo algorithm. */\n+\t#define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO\t(UINT32_C(0x1) << 7)\n+\t\t/*\n+\t\t * Header/Data Separation: Packet was placed using Header/Data\n+\t\t * separation algorithm. The separation location is indicated by\n+\t\t * the itype field.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS\t\t(UINT32_C(0x2) << 7)\n+\t#define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \\\n+\t\t\t\t\t\tRX_PKT_CMPL_FLAGS_PLACEMENT_HDS\n+\t/* This bit is '1' if the RSS field in this completion is valid. */\n+\t#define RX_PKT_CMPL_FLAGS_RSS_VALID\t\tUINT32_C(0x400)\n+\t/*\n+\t * This value indicates what the inner packet determined for the packet\n+\t * was.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_MASK\t\tUINT32_C(0xf000)\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_SFT\t\t12\n+\t\t/* Not Known: Indicates that the packet type was not known. */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN\t(UINT32_C(0x0) << 12)\n+\t\t/*\n+\t\t * IP Packet: Indicates that the packet was an IP packet, but\n+\t\t * further classification was not possible.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_IP\t\t(UINT32_C(0x1) << 12)\n+\t\t/*\n+\t\t * TCP Packet: Indicates that the packet was IP and TCP. This\n+\t\t * indicates that the payload_offset field is valid.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_TCP\t\t(UINT32_C(0x2) << 12)\n+\t\t/*\n+\t\t * UDP Packet: Indicates that the packet was IP and UDP. This\n+\t\t * indicates that the payload_offset field is valid.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_UDP\t\t(UINT32_C(0x3) << 12)\n+\t\t/*\n+\t\t * FCoE Packet: Indicates that the packet was recognized as a\n+\t\t * FCoE. This also indicates that the payload_offset field is\n+\t\t * valid.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_FCOE\t\t(UINT32_C(0x4) << 12)\n+\t\t/*\n+\t\t * RoCE Packet: Indicates that the packet was recognized as a\n+\t\t * RoCE. This also indicates that the payload_offset field is\n+\t\t * valid.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_ROCE\t\t(UINT32_C(0x5) << 12)\n+\t\t/*\n+\t\t * ICMP Packet: Indicates that the packet was recognized as\n+\t\t * ICMP. This indicates that the payload_offset field is valid.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_ICMP\t\t(UINT32_C(0x7) << 12)\n+\t\t/*\n+\t\t * PtP packet wo/timestamp: Indicates that the packet was\n+\t\t * recognized as a PtP packet.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \\\n+\t\t\t\t\t\t\t(UINT32_C(0x8) << 12)\n+\t\t/*\n+\t\t * PtP packet w/timestamp: Indicates that the packet was\n+\t\t * recognized as a PtP packet and that a timestamp was taken for\n+\t\t * the packet.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP\t(UINT32_C(0x9) << 12)\n+\t#define RX_PKT_CMPL_FLAGS_ITYPE_LAST \\\n+\t\t\t\t\tRX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP\n+\t#define RX_PKT_CMPL_FLAGS_MASK\t\t\tUINT32_C(0xffc0)\n+\t#define RX_PKT_CMPL_FLAGS_SFT\t\t\t6\n+\tuint16_t flags_type;\n+\n+\t/*\n+\t * This is the length of the data for the packet stored in the buffer(s)\n+\t * identified by the opaque value. This includes the packet BD and any\n+\t * associated buffer BDs. This does not include the the length of any\n+\t * data places in aggregation BDs.\n+\t */\n+\tuint16_t len;\n+\n+\t/*\n+\t * This is a copy of the opaque field from the RX BD this completion\n+\t * corresponds to.\n+\t */\n+\tuint32_t opaque;\n+\n+\t/*\n+\t * This value is written by the NIC such that it will be different for\n+\t * each pass through the completion queue. The even passes will write 1.\n+\t * The odd passes will write 0.\n+\t */\n+\t#define RX_PKT_CMPL_V1\t\t\t\tUINT32_C(0x1)\n+\t/*\n+\t * This value is the number of aggregation buffers that follow this\n+\t * entry in the completion ring that are a part of this packet. If the\n+\t * value is zero, then the packet is completely contained in the buffer\n+\t * space provided for the packet in the RX ring.\n+\t */\n+\t#define RX_PKT_CMPL_AGG_BUFS_MASK\t\tUINT32_C(0x3e)\n+\t#define RX_PKT_CMPL_AGG_BUFS_SFT\t\t1\n+\tuint8_t agg_bufs_v1;\n+\n+\t/*\n+\t * This is the RSS hash type for the packet. The value is packed\n+\t * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.\n+\t */\n+\tuint8_t rss_hash_type;\n+\n+\t/*\n+\t * This value indicates the offset from the beginning of the packet\n+\t * where the inner payload starts. This value is valid for TCP, UDP,\n+\t * FCoE, and RoCE packets.\n+\t */\n+\tuint8_t payload_offset;\n+\n+\tuint8_t unused_1;\n+\n+\t/*\n+\t * This value is the RSS hash value calculated for the packet based on\n+\t * the mode bits and key value in the VNIC.\n+\t */\n+\tuint32_t rss_hash;\n+} __attribute__((packed));\n+\n+/* last 16 bytes of RX Packet Completion Record */\n+struct rx_pkt_cmpl_hi {\n+\t/*\n+\t * This indicates that the ip checksum was calculated for the inner\n+\t * packet and that the ip_cs_error field indicates if there was an\n+\t * error.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_IP_CS_CALC\t\tUINT32_C(0x1)\n+\t/*\n+\t * This indicates that the TCP, UDP or ICMP checksum was calculated for\n+\t * the inner packet and that the l4_cs_error field indicates if there\n+\t * was an error.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_L4_CS_CALC\t\tUINT32_C(0x2)\n+\t/*\n+\t * This indicates that the ip checksum was calculated for the tunnel\n+\t * header and that the t_ip_cs_error field indicates if there was an\n+\t * error.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC\t\tUINT32_C(0x4)\n+\t/*\n+\t * This indicates that the UDP checksum was calculated for the tunnel\n+\t * packet and that the t_l4_cs_error field indicates if there was an\n+\t * error.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC\t\tUINT32_C(0x8)\n+\t/* This value indicates what format the metadata field is. */\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK\tUINT32_C(0xf0)\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT\t4\n+\t\t/* No metadata informtaion. Value is zero. */\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE\t(UINT32_C(0x0) << 4)\n+\t\t/*\n+\t\t * The metadata field contains the VLAN tag and TPID value. -\n+\t\t * metadata[11:0] contains the vlan VID value. - metadata[12]\n+\t\t * contains the vlan DE value. - metadata[15:13] contains the\n+\t\t * vlan PRI value. - metadata[31:16] contains the vlan TPID\n+\t\t * value.\n+\t\t */\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN\t(UINT32_C(0x1) << 4)\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \\\n+\t\t\t\t\tRX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN\n+\t/*\n+\t * This field indicates the IP type for the inner-most IP header. A\n+\t * value of '0' indicates IPv4. A value of '1' indicates IPv6. This\n+\t * value is only valid if itype indicates a packet with an IP header.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_IP_TYPE\t\tUINT32_C(0x100)\n+\tuint32_t flags2;\n+\n+\t/*\n+\t * This is data from the CFA block as indicated by the meta_format\n+\t * field.\n+\t */\n+\t/* When meta_format=1, this value is the VLAN VID. */\n+\t#define RX_PKT_CMPL_METADATA_VID_MASK\t\tUINT32_C(0xfff)\n+\t#define RX_PKT_CMPL_METADATA_VID_SFT\t\t0\n+\t/* When meta_format=1, this value is the VLAN DE. */\n+\t#define RX_PKT_CMPL_METADATA_DE\t\t\tUINT32_C(0x1000)\n+\t/* When meta_format=1, this value is the VLAN PRI. */\n+\t#define RX_PKT_CMPL_METADATA_PRI_MASK\t\tUINT32_C(0xe000)\n+\t#define RX_PKT_CMPL_METADATA_PRI_SFT\t\t13\n+\t/* When meta_format=1, this value is the VLAN TPID. */\n+\t#define RX_PKT_CMPL_METADATA_TPID_MASK\t\tUINT32_C(0xffff0000)\n+\t#define RX_PKT_CMPL_METADATA_TPID_SFT\t\t16\n+\tuint32_t metadata;\n+\n+\t/*\n+\t * This value is written by the NIC such that it will be different for\n+\t * each pass through the completion queue. The even passes will write 1.\n+\t * The odd passes will write 0.\n+\t */\n+\t#define RX_PKT_CMPL_V2\t\t\t\tUINT32_C(0x1)\n+\t/*\n+\t * This error indicates that there was some sort of problem with the BDs\n+\t * for the packet that was found after part of the packet was already\n+\t * placed. The packet should be treated as invalid.\n+\t */\n+\t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK\tUINT32_C(0xe)\n+\t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT\t1\n+\t\t/* No buffer error */\n+\t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \\\n+\t\t\t\t\t\t\t(UINT32_C(0x0) << 1)\n+\t\t/*\n+\t\t * Did Not Fit: Packet did not fit into packet buffer provided.\n+\t\t * For regular placement, this means the packet did not fit in\n+\t\t * the buffer provided. For HDS and jumbo placement, this means\n+\t\t * that the packet could not be placed into 7 physical buffers\n+\t\t * or less.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \\\n+\t\t\t\t\t\t\t(UINT32_C(0x1) << 1)\n+\t\t/*\n+\t\t * Not On Chip: All BDs needed for the packet were not on-chip\n+\t\t * when the packet arrived.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \\\n+\t\t\t\t\t\t\t(UINT32_C(0x2) << 1)\n+\t\t/* Bad Format: BDs were not formatted correctly. */\n+\t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \\\n+\t\t\t\t\t\t\t(UINT32_C(0x3) << 1)\n+\t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \\\n+\t\t\t\tRX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT\n+\t/* This indicates that there was an error in the IP header checksum. */\n+\t#define RX_PKT_CMPL_ERRORS_IP_CS_ERROR\t\tUINT32_C(0x10)\n+\t/*\n+\t * This indicates that there was an error in the TCP, UDP or ICMP\n+\t * checksum.\n+\t */\n+\t#define RX_PKT_CMPL_ERRORS_L4_CS_ERROR\t\tUINT32_C(0x20)\n+\t/*\n+\t * This indicates that there was an error in the tunnel IP header\n+\t * checksum.\n+\t */\n+\t#define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR\tUINT32_C(0x40)\n+\t/* This indicates that there was an error in the tunnel UDP checksum. */\n+\t#define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR\tUINT32_C(0x80)\n+\t/*\n+\t * This indicates that there was a CRC error on either an FCoE or RoCE\n+\t * packet. The itype indicates the packet type.\n+\t */\n+\t#define RX_PKT_CMPL_ERRORS_CRC_ERROR\t\tUINT32_C(0x100)\n+\t/*\n+\t * This indicates that there was an error in the tunnel portion of the\n+\t * packet when this field is non-zero.\n+\t */\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK\tUINT32_C(0xe00)\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT\t9\n+\t\t/*\n+\t\t * No additional error occurred on the tunnel portion of the\n+\t\t * packet of the packet does not have a tunnel.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR\t(UINT32_C(0x0) << 9)\n+\t\t/*\n+\t\t * Indicates that IP header version does not match expectation\n+\t\t * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \\\n+\t\t\t\t\t\t\t(UINT32_C(0x1) << 9)\n+\t\t/*\n+\t\t * Indicates that header length is out of range in the tunnel\n+\t\t * header. Valid for IPv4.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \\\n+\t\t\t\t\t\t\t(UINT32_C(0x2) << 9)\n+\t\t/*\n+\t\t * Indicates that the physical packet is shorter than that\n+\t\t * claimed by the PPPoE header length for a tunnel PPPoE packet.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \\\n+\t\t\t\t\t\t\t(UINT32_C(0x3) << 9)\n+\t\t/*\n+\t\t * Indicates that physical packet is shorter than that claimed\n+\t\t * by the tunnel l3 header length. Valid for IPv4, or IPv6\n+\t\t * tunnel packet packets.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \\\n+\t\t\t\t\t\t\t(UINT32_C(0x4) << 9)\n+\t\t/*\n+\t\t * Indicates that the physical packet is shorter than that\n+\t\t * claimed by the tunnel UDP header length for a tunnel UDP\n+\t\t * packet that is not fragmented.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \\\n+\t\t\t\t\t\t\t(UINT32_C(0x5) << 9)\n+\t\t/*\n+\t\t * indicates that the IPv4 TTL or IPv6 hop limit check have\n+\t\t * failed (e.g. TTL = 0) in the tunnel header. Valid for IPv4,\n+\t\t * and IPv6.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \\\n+\t\t\t\t\t\t\t(UINT32_C(0x6) << 9)\n+\t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \\\n+\t\t\t\tRX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL\n+\t/*\n+\t * This indicates that there was an error in the inner portion of the\n+\t * packet when this field is non-zero.\n+\t */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK\tUINT32_C(0xf000)\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT\t12\n+\t\t/*\n+\t\t * No additional error occurred on the tunnel portion of the\n+\t\t * packet of the packet does not have a tunnel.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR\t(UINT32_C(0x0) << 12)\n+\t\t/*\n+\t\t * Indicates that IP header version does not match expectation\n+\t\t * from L2 Ethertype for IPv4 and IPv6 or that option other than\n+\t\t * VFT was parsed on FCoE packet.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \\\n+\t\t\t\t\t\t\t(UINT32_C(0x1) << 12)\n+\t\t/*\n+\t\t * indicates that header length is out of range. Valid for IPv4\n+\t\t * and RoCE\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \\\n+\t\t\t\t\t\t\t(UINT32_C(0x2) << 12)\n+\t\t/*\n+\t\t * indicates that the IPv4 TTL or IPv6 hop limit check have\n+\t\t * failed (e.g. TTL = 0). Valid for IPv4, and IPv6\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL\t(UINT32_C(0x3) << 12)\n+\t\t/*\n+\t\t * Indicates that physical packet is shorter than that claimed\n+\t\t * by the l3 header length. Valid for IPv4, IPv6 packet or RoCE\n+\t\t * packets.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \\\n+\t\t\t\t\t\t\t(UINT32_C(0x4) << 12)\n+\t\t/*\n+\t\t * Indicates that the physical packet is shorter than that\n+\t\t * claimed by the UDP header length for a UDP packet that is not\n+\t\t * fragmented.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \\\n+\t\t\t\t\t\t\t(UINT32_C(0x5) << 12)\n+\t\t/*\n+\t\t * Indicates that TCP header length > IP payload. Valid for TCP\n+\t\t * packets only.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \\\n+\t\t\t\t\t\t\t(UINT32_C(0x6) << 12)\n+\t\t/* Indicates that TCP header length < 5. Valid for TCP. */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \\\n+\t\t\t\t\t\t\t(UINT32_C(0x7) << 12)\n+\t\t/*\n+\t\t * Indicates that TCP option headers result in a TCP header size\n+\t\t * that does not match data offset in TCP header. Valid for TCP.\n+\t\t */\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \\\n+\t\t\t\t\t\t\t(UINT32_C(0x8) << 12)\n+\t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \\\n+\t\t\t\tRX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN\n+\t#define RX_PKT_CMPL_ERRORS_MASK\t\t\tUINT32_C(0xfffe)\n+\t#define RX_PKT_CMPL_ERRORS_SFT\t\t\t1\n+\tuint16_t errors_v2;\n+\n+\t/*\n+\t * This field identifies the CFA action rule that was used for this\n+\t * packet.\n+\t */\n+\tuint16_t cfa_code;\n+\n+\t/*\n+\t * This value holds the reordering sequence number for the packet. If\n+\t * the reordering sequence is not valid, then this value is zero. The\n+\t * reordering domain for the packet is in the bottom 8 to 10b of the\n+\t * rss_hash value. The bottom 20b of this value contain the ordering\n+\t * domain value for the packet.\n+\t */\n+\t#define RX_PKT_CMPL_REORDER_MASK\t\tUINT32_C(0xffffff)\n+\t#define RX_PKT_CMPL_REORDER_SFT\t\t\t0\n+\tuint32_t reorder;\n+} __attribute__((packed));\n+\n /* HWRM Forwarded Request (16 bytes) */\n struct hwrm_fwd_req_cmpl {\n \t/* Length of forwarded request in bytes. */\n", "prefixes": [ "dpdk-dev", "v5", "14/38" ] }