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GET /api/patches/137303/?format=api
{ "id": 137303, "url": "http://patches.dpdk.org/api/patches/137303/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1709012499-12813-12-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1709012499-12813-12-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1709012499-12813-12-git-send-email-roretzla@linux.microsoft.com", "date": "2024-02-27T05:41:27", "name": "[v6,11/23] net/ice: use mbuf descriptor accessors", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "74c3286052815d9e24ef4214f357d0761f9164dc", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1709012499-12813-12-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31232, "url": "http://patches.dpdk.org/api/series/31232/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31232", "date": "2024-02-27T05:41:17", "name": "stop and remove RTE_MARKER typedefs", "version": 6, "mbox": "http://patches.dpdk.org/series/31232/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137303/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137303/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EC74643C03;\n\tTue, 27 Feb 2024 06:43:04 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A344442EAB;\n\tTue, 27 Feb 2024 06:42:23 +0100 (CET)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id A49E642E28\n for <dev@dpdk.org>; Tue, 27 Feb 2024 06:41:42 +0100 (CET)", "by linux.microsoft.com (Postfix, from userid 1086)\n id 4F70720B74CB; Mon, 26 Feb 2024 21:41:40 -0800 (PST)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 4F70720B74CB", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1709012501;\n bh=QXUSjsa1O426MmBxQKznXdqfLwRtkEq0lm/TN3DZ2MA=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=L2/Ejl00jHZVG/6Xkj0eKa0TadF/PWa2jZi6vibWDZNnm+EeAGrxEJH5CWEY0nmhR\n vdOy6E85AFIOl2FvhPM+tgaajP0BpfLTdzS05OBWAklF+Kwj4vNWFGct70wDvVyrqX\n Nz7uAJIAxk2XNjOExna5wJPWqPJmVM6QW95jWRDs=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "Ajit Khaparde <ajit.khaparde@broadcom.com>,\n Andrew Boyer <andrew.boyer@amd.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>,\n David Christensen <drc@linux.vnet.ibm.com>,\n Hyong Youb Kim <hyonkim@cisco.com>, Jerin Jacob <jerinj@marvell.com>,\n Jie Hai <haijie1@huawei.com>, Jingjing Wu <jingjing.wu@intel.com>,\n John Daley <johndale@cisco.com>, Kevin Laatz <kevin.laatz@intel.com>,\n Kiran Kumar K <kirankumark@marvell.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Satha Rao <skoteshwar@marvell.com>,\n Somnath Kotur <somnath.kotur@broadcom.com>,\n Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Yisen Zhuang <yisen.zhuang@huawei.com>,\n Yuying Zhang <Yuying.Zhang@intel.com>, mb@smartsharesystems.com,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v6 11/23] net/ice: use mbuf descriptor accessors", "Date": "Mon, 26 Feb 2024 21:41:27 -0800", "Message-Id": "<1709012499-12813-12-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1709012499-12813-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1706657173-26166-1-git-send-email-roretzla@linux.microsoft.com>\n <1709012499-12813-1-git-send-email-roretzla@linux.microsoft.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "RTE_MARKER typedefs are a GCC extension unsupported by MSVC. Use\nnew rte_mbuf_rearm_data and rte_mbuf_rx_descriptor_fields1 accessors\nthat provide a compatible type pointer without using the marker fields.\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\n---\n drivers/net/ice/ice_rxtx_vec_avx2.c | 36 +++++++---------------------\n drivers/net/ice/ice_rxtx_vec_avx512.c | 37 +++++++----------------------\n drivers/net/ice/ice_rxtx_vec_common.h | 4 +---\n drivers/net/ice/ice_rxtx_vec_sse.c | 44 +++++++----------------------------\n 4 files changed, 25 insertions(+), 96 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_rxtx_vec_avx2.c b/drivers/net/ice/ice_rxtx_vec_avx2.c\nindex 6f6d790..853f99b 100644\n--- a/drivers/net/ice/ice_rxtx_vec_avx2.c\n+++ b/drivers/net/ice/ice_rxtx_vec_avx2.c\n@@ -114,19 +114,6 @@\n \t\t\t 0xFF, 0xFF,\t/* pkt_type set as unknown */\n \t\t\t 0xFF, 0xFF\t/*pkt_type set as unknown */\n \t\t\t);\n-\t/**\n-\t * compile-time check the above crc and shuffle layout is correct.\n-\t * NOTE: the first field (lowest address) is given last in set_epi\n-\t * calls above.\n-\t */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n \n \t/* Status/Error flag masks */\n \t/**\n@@ -570,13 +557,6 @@\n \t\t * add in the previously computed rx_descriptor fields to\n \t\t * make a single 256-bit write per mbuf\n \t\t */\n-\t\t/* check the structure matches expectations */\n-\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n-\t\t\t\t offsetof(struct rte_mbuf, rearm_data) + 8);\n-\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n-\t\t\t\t RTE_ALIGN(offsetof(struct rte_mbuf,\n-\t\t\t\t\t\t rearm_data),\n-\t\t\t\t\t 16));\n \t\t/* build up data and do writes */\n \t\t__m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,\n \t\t\trearm6, rearm7;\n@@ -596,13 +576,13 @@\n \t\trearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);\n \t\trearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);\n \t\t/* write to mbuf */\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 6]),\n \t\t\t\t rearm6);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 4]),\n \t\t\t\t rearm4);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 2]),\n \t\t\t\t rearm2);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 0]),\n \t\t\t\t rearm0);\n \n \t\t/* repeat for the odd mbufs */\n@@ -625,13 +605,13 @@\n \t\trearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);\n \t\trearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);\n \t\t/* again write to mbufs */\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 7]),\n \t\t\t\t rearm7);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 5]),\n \t\t\t\t rearm5);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 3]),\n \t\t\t\t rearm3);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 1]),\n \t\t\t\t rearm1);\n \n \t\t/* extract and record EOP bit */\ndiff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c b/drivers/net/ice/ice_rxtx_vec_avx512.c\nindex 04148e8..6d04bf7 100644\n--- a/drivers/net/ice/ice_rxtx_vec_avx512.c\n+++ b/drivers/net/ice/ice_rxtx_vec_avx512.c\n@@ -100,20 +100,6 @@\n \t\t\t 0xFFFFFFFF\n \t\t\t);\n \n-\t/**\n-\t * compile-time check the above crc and shuffle layout is correct.\n-\t * NOTE: the first field (lowest address) is given last in set_epi\n-\t * calls above.\n-\t */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n-\n \t/* following code block is for Rx Checksum Offload */\n \t/* Status/Error flag masks */\n \t/**\n@@ -568,13 +554,6 @@\n \t\t * add in the previously computed rx_descriptor fields to\n \t\t * make a single 256-bit write per mbuf\n \t\t */\n-\t\t/* check the structure matches expectations */\n-\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n-\t\t\t\t offsetof(struct rte_mbuf, rearm_data) + 8);\n-\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n-\t\t\t\t RTE_ALIGN(offsetof(struct rte_mbuf,\n-\t\t\t\t\t\t rearm_data),\n-\t\t\t\t\t 16));\n \t\t/* build up data and do writes */\n \t\t__m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,\n \t\t\trearm6, rearm7;\n@@ -597,13 +576,13 @@\n \t\trearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);\n \n \t\t/* write to mbuf */\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 6]),\n \t\t\t\t rearm6);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 4]),\n \t\t\t\t rearm4);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 2]),\n \t\t\t\t rearm2);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 0]),\n \t\t\t\t rearm0);\n \n \t\t/* repeat for the odd mbufs */\n@@ -627,13 +606,13 @@\n \t\trearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);\n \t\trearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);\n \t\t/* again write to mbufs */\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 7]),\n \t\t\t\t rearm7);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 5]),\n \t\t\t\t rearm5);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 3]),\n \t\t\t\t rearm3);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 1]),\n \t\t\t\t rearm1);\n \n \t\t/* extract and record EOP bit */\ndiff --git a/drivers/net/ice/ice_rxtx_vec_common.h b/drivers/net/ice/ice_rxtx_vec_common.h\nindex 4b73465..c284d2d 100644\n--- a/drivers/net/ice/ice_rxtx_vec_common.h\n+++ b/drivers/net/ice/ice_rxtx_vec_common.h\n@@ -232,7 +232,6 @@\n static inline int\n ice_rxq_vec_setup_default(struct ice_rx_queue *rxq)\n {\n-\tuintptr_t p;\n \tstruct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */\n \n \tmb_def.nb_segs = 1;\n@@ -242,8 +241,7 @@\n \n \t/* prevent compiler reordering: rearm_data covers previous fields */\n \trte_compiler_barrier();\n-\tp = (uintptr_t)&mb_def.rearm_data;\n-\trxq->mbuf_initializer = *(uint64_t *)p;\n+\trxq->mbuf_initializer = *rte_mbuf_rearm_data(&mb_def);\n \treturn 0;\n }\n \ndiff --git a/drivers/net/ice/ice_rxtx_vec_sse.c b/drivers/net/ice/ice_rxtx_vec_sse.c\nindex 9a1b7e3..ed9928b 100644\n--- a/drivers/net/ice/ice_rxtx_vec_sse.c\n+++ b/drivers/net/ice/ice_rxtx_vec_sse.c\n@@ -267,14 +267,10 @@\n \trearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(flags, 4), 0x30);\n \n \t/* write the rearm data and the olflags in one write */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n-\t\t\t offsetof(struct rte_mbuf, rearm_data) + 8);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n-\t\t\t RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));\n-\t_mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);\n-\t_mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);\n-\t_mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);\n-\t_mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);\n+\t_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[0]), rearm0);\n+\t_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[1]), rearm1);\n+\t_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[2]), rearm2);\n+\t_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[3]), rearm3);\n }\n \n static inline void\n@@ -342,16 +338,6 @@\n \t\t\t\t\t\t 0x04, 0x0C,\n \t\t\t\t\t\t 0x00, 0x08);\n \n-\t/**\n-\t * compile-time check the above crc_adjust layout is correct.\n-\t * NOTE: the first field (lowest address) is given last in set_epi16\n-\t * call above.\n-\t */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n-\t\t\t offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n-\t\t\t offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n-\n \t/* 4 packets DD mask */\n \tconst __m128i dd_check = _mm_set_epi64x(0x0000000100000001LL,\n \t\t\t\t\t\t0x0000000100000001LL);\n@@ -382,20 +368,6 @@\n \t rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))\n \t\treturn 0;\n \n-\t/**\n-\t * Compile-time verify the shuffle mask\n-\t * NOTE: some field positions already verified above, but duplicated\n-\t * here for completeness in case of future modifications.\n-\t */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n-\t\t\t offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n-\t\t\t offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n-\t\t\t offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n-\t\t\t offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n-\n \t/* Cache is empty -> need to scan the buffer rings, but first move\n \t * the next 'n' mbufs into the cache\n \t */\n@@ -542,10 +514,10 @@\n \n \t\t/* D.3 copy final 3,4 data to rx_pkts */\n \t\t_mm_storeu_si128\n-\t\t\t((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,\n+\t\t\t(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 3]),\n \t\t\t pkt_mb3);\n \t\t_mm_storeu_si128\n-\t\t\t((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,\n+\t\t\t(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 2]),\n \t\t\t pkt_mb2);\n \n \t\t/* C* extract and record EOP bit */\n@@ -569,9 +541,9 @@\n \n \t\t/* D.3 copy final 1,2 data to rx_pkts */\n \t\t_mm_storeu_si128\n-\t\t\t((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,\n+\t\t\t(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 1]),\n \t\t\t pkt_mb1);\n-\t\t_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,\n+\t\t_mm_storeu_si128(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos]),\n \t\t\t\t pkt_mb0);\n \t\tice_rx_desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);\n \t\t/* C.4 calc available number of desc */\n", "prefixes": [ "v6", "11/23" ] }