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GET /api/patches/137300/?format=api
{ "id": 137300, "url": "http://patches.dpdk.org/api/patches/137300/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1709012499-12813-10-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1709012499-12813-10-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1709012499-12813-10-git-send-email-roretzla@linux.microsoft.com", "date": "2024-02-27T05:41:25", "name": "[v6,09/23] net/i40e: use mbuf descriptor accessors", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bc6915eba0619086179a5493e024efa8e9f833dd", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1709012499-12813-10-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31232, "url": "http://patches.dpdk.org/api/series/31232/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31232", "date": "2024-02-27T05:41:17", "name": "stop and remove RTE_MARKER typedefs", "version": 6, "mbox": "http://patches.dpdk.org/series/31232/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137300/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137300/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 64EC443C03;\n\tTue, 27 Feb 2024 06:42:45 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8C95842E87;\n\tTue, 27 Feb 2024 06:42:19 +0100 (CET)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id 91E3E402A7\n for <dev@dpdk.org>; Tue, 27 Feb 2024 06:41:42 +0100 (CET)", "by linux.microsoft.com (Postfix, from userid 1086)\n id 322E320B74C9; Mon, 26 Feb 2024 21:41:40 -0800 (PST)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 322E320B74C9", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1709012501;\n bh=KVp3GaPTlA6IhRX2/cqo/lCeuFijymdaCpdHvBKfDFs=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=XedJP2uPq9TLkqjdCpGPJjkq4wO58DS6brQkSmKqg0cAke/qSypXd88NaFEsdnM76\n onX1YKbBEJ/oExXh5KbNqzletGpHOYI6mHJv25aZNef+ALDnG0cbcwAVwPa7OaWSHl\n KloPqOTszPOWikswgd59zV7z+5xVMmjK4RgSWYyQ=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "Ajit Khaparde <ajit.khaparde@broadcom.com>,\n Andrew Boyer <andrew.boyer@amd.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>,\n David Christensen <drc@linux.vnet.ibm.com>,\n Hyong Youb Kim <hyonkim@cisco.com>, Jerin Jacob <jerinj@marvell.com>,\n Jie Hai <haijie1@huawei.com>, Jingjing Wu <jingjing.wu@intel.com>,\n John Daley <johndale@cisco.com>, Kevin Laatz <kevin.laatz@intel.com>,\n Kiran Kumar K <kirankumark@marvell.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Satha Rao <skoteshwar@marvell.com>,\n Somnath Kotur <somnath.kotur@broadcom.com>,\n Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Yisen Zhuang <yisen.zhuang@huawei.com>,\n Yuying Zhang <Yuying.Zhang@intel.com>, mb@smartsharesystems.com,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v6 09/23] net/i40e: use mbuf descriptor accessors", "Date": "Mon, 26 Feb 2024 21:41:25 -0800", "Message-Id": "<1709012499-12813-10-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1709012499-12813-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1706657173-26166-1-git-send-email-roretzla@linux.microsoft.com>\n <1709012499-12813-1-git-send-email-roretzla@linux.microsoft.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "RTE_MARKER typedefs are a GCC extension unsupported by MSVC. Use\nnew rte_mbuf_rearm_data and rte_mbuf_rx_descriptor_fields1 accessors\nthat provide a compatible type pointer without using the marker fields.\n\nUse rte_mbuf_prefetch_part2() to prefetch cacheline1 and remove\nreference to rte marker field.\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\n---\n drivers/net/i40e/i40e_rxtx_vec_altivec.c | 18 +++++--------\n drivers/net/i40e/i40e_rxtx_vec_avx2.c | 34 ++++++-------------------\n drivers/net/i40e/i40e_rxtx_vec_avx512.c | 35 +++++++-------------------\n drivers/net/i40e/i40e_rxtx_vec_common.h | 4 +--\n drivers/net/i40e/i40e_rxtx_vec_neon.c | 16 ++++++------\n drivers/net/i40e/i40e_rxtx_vec_sse.c | 43 +++++++-------------------------\n 6 files changed, 41 insertions(+), 109 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_rxtx_vec_altivec.c b/drivers/net/i40e/i40e_rxtx_vec_altivec.c\nindex b6b0d38..3e065ee 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_altivec.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_altivec.c\n@@ -55,7 +55,6 @@\n \t/* Initialize the mbufs in vector, process 2 mbufs in one loop */\n \tfor (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {\n \t\t__vector unsigned long vaddr0, vaddr1;\n-\t\tuintptr_t p0, p1;\n \n \t\tmb0 = rxep[0].mbuf;\n \t\tmb1 = rxep[1].mbuf;\n@@ -66,10 +65,8 @@\n \t\t * anyway. So overwrite whole 8 bytes with one load:\n \t\t * 6 bytes of rearm_data plus first 2 bytes of ol_flags.\n \t\t */\n-\t\tp0 = (uintptr_t)&mb0->rearm_data;\n-\t\t*(uint64_t *)p0 = rxq->mbuf_initializer;\n-\t\tp1 = (uintptr_t)&mb1->rearm_data;\n-\t\t*(uint64_t *)p1 = rxq->mbuf_initializer;\n+\t\t*rte_mbuf_rearm_data(mb0) = rxq->mbuf_initializer;\n+\t\t*rte_mbuf_rearm_data(mb1) = rxq->mbuf_initializer;\n \n \t\t/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */\n \t\tvaddr0 = vec_ld(0, (__vector unsigned long *)&mb0->buf_addr);\n@@ -370,12 +367,10 @@\n \n \t\t/* D.3 copy final 3,4 data to rx_pkts */\n \t\tvec_st(pkt_mb4, 0,\n-\t\t (__vector unsigned char *)&rx_pkts[pos + 3]\n-\t\t\t->rx_descriptor_fields1\n+\t\t (__vector unsigned char *)rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 3])\n \t\t);\n \t\tvec_st(pkt_mb3, 0,\n-\t\t (__vector unsigned char *)&rx_pkts[pos + 2]\n-\t\t\t->rx_descriptor_fields1\n+\t\t (__vector unsigned char *)rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 2])\n \t\t);\n \n \t\t/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */\n@@ -422,11 +417,10 @@\n \n \t\t/* D.3 copy final 1,2 data to rx_pkts */\n \t\tvec_st(pkt_mb2, 0,\n-\t\t (__vector unsigned char *)&rx_pkts[pos + 1]\n-\t\t\t->rx_descriptor_fields1\n+\t\t (__vector unsigned char *)rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 1])\n \t\t);\n \t\tvec_st(pkt_mb1, 0,\n-\t\t (__vector unsigned char *)&rx_pkts[pos]->rx_descriptor_fields1\n+\t\t (__vector unsigned char *)rte_mbuf_rx_descriptor_fields1(rx_pkts[pos])\n \t\t);\n \t\tdesc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);\n \t\tdesc_to_olflags_v(descs, &rx_pkts[pos]);\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_avx2.c b/drivers/net/i40e/i40e_rxtx_vec_avx2.c\nindex f468c1f..360d80f 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_avx2.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_avx2.c\n@@ -180,19 +180,6 @@\n \t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n \t\t\t0xFF, 0xFF /*pkt_type set as unknown */\n \t);\n-\t/*\n-\t * compile-time check the above crc and shuffle layout is correct.\n-\t * NOTE: the first field (lowest address) is given last in set_epi\n-\t * calls above.\n-\t */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n \n \t/* Status/Error flag masks */\n \t/*\n@@ -525,11 +512,6 @@\n \t\t * add in the previously computed rx_descriptor fields to\n \t\t * make a single 256-bit write per mbuf\n \t\t */\n-\t\t/* check the structure matches expectations */\n-\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n-\t\t\t\toffsetof(struct rte_mbuf, rearm_data) + 8);\n-\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n-\t\t\t\tRTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));\n \t\t/* build up data and do writes */\n \t\t__m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,\n \t\t\t\trearm6, rearm7;\n@@ -543,10 +525,10 @@\n \t\trearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);\n \t\trearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);\n \t\t/* write to mbuf */\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data, rearm6);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data, rearm4);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data, rearm2);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data, rearm0);\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 6]), rearm6);\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 4]), rearm4);\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 2]), rearm2);\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 0]), rearm0);\n \n \t\t/* repeat for the odd mbufs */\n \t\tconst __m256i odd_flags = _mm256_castsi128_si256(\n@@ -561,10 +543,10 @@\n \t\trearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);\n \t\trearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);\n \t\t/* again write to mbufs */\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data, rearm7);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data, rearm5);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data, rearm3);\n-\t\t_mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data, rearm1);\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 7]), rearm7);\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 5]), rearm5);\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 3]), rearm3);\n+\t\t_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 1]), rearm1);\n \n \t\t/* extract and record EOP bit */\n \t\tif (split_packet) {\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_avx512.c b/drivers/net/i40e/i40e_rxtx_vec_avx512.c\nindex f3050cd..e13bd2f 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_avx512.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_avx512.c\n@@ -170,18 +170,6 @@\n \t\t\t /* pkt_type set as unknown */\n \t\t\t 0xFFFFFFFF\n \t\t\t);\n-\t/* compile-time check the above crc and shuffle layout is correct.\n-\t * NOTE: the first field (lowest address) is given last in set_epi\n-\t * calls above.\n-\t */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n \n \t/* Status/Error flag masks */\n \t/* mask everything except RSS, flow director and VLAN flags\n@@ -557,11 +545,6 @@\n \t\t * add in the previously computed rx_descriptor fields to\n \t\t * make a single 256-bit write per mbuf\n \t\t */\n-\t\t/* check the structure matches expectations */\n-\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n-\t\t\t\toffsetof(struct rte_mbuf, rearm_data) + 8);\n-\t\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n-\t\t\t\tRTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));\n \t\t/* build up data and do writes */\n \t\t__m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,\n \t\t\t\trearm6, rearm7;\n@@ -580,13 +563,13 @@\n \t\trearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);\n \t\t/* write to mbuf */\n \t\t_mm256_storeu_si256\n-\t\t\t((__m256i *)&rx_pkts[i + 6]->rearm_data, rearm6);\n+\t\t\t((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 6]), rearm6);\n \t\t_mm256_storeu_si256\n-\t\t\t((__m256i *)&rx_pkts[i + 4]->rearm_data, rearm4);\n+\t\t\t((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 4]), rearm4);\n \t\t_mm256_storeu_si256\n-\t\t\t((__m256i *)&rx_pkts[i + 2]->rearm_data, rearm2);\n+\t\t\t((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 2]), rearm2);\n \t\t_mm256_storeu_si256\n-\t\t\t((__m256i *)&rx_pkts[i + 0]->rearm_data, rearm0);\n+\t\t\t((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 0]), rearm0);\n \n \t\t/* repeat for the odd mbufs */\n \t\tconst __m256i odd_flags = _mm256_castsi128_si256\n@@ -606,13 +589,13 @@\n \t\trearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);\n \t\t/* again write to mbufs */\n \t\t_mm256_storeu_si256\n-\t\t\t((__m256i *)&rx_pkts[i + 7]->rearm_data, rearm7);\n+\t\t\t((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 7]), rearm7);\n \t\t_mm256_storeu_si256\n-\t\t\t((__m256i *)&rx_pkts[i + 5]->rearm_data, rearm5);\n+\t\t\t((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 5]), rearm5);\n \t\t_mm256_storeu_si256\n-\t\t\t((__m256i *)&rx_pkts[i + 3]->rearm_data, rearm3);\n+\t\t\t((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 3]), rearm3);\n \t\t_mm256_storeu_si256\n-\t\t\t((__m256i *)&rx_pkts[i + 1]->rearm_data, rearm1);\n+\t\t\t((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 1]), rearm1);\n \n \t\t/* extract and record EOP bit */\n \t\tif (split_packet) {\n@@ -826,7 +809,7 @@\n \t\tfree[0] = m;\n \t\tnb_free = 1;\n \t\tfor (i = 1; i < n; i++) {\n-\t\t\trte_prefetch0(&txep[i + 3].mbuf->cacheline1);\n+\t\t\trte_mbuf_prefetch_part2(txep[i + 3].mbuf);\n \t\t\tm = rte_pktmbuf_prefree_seg(txep[i].mbuf);\n \t\t\tif (likely(m)) {\n \t\t\t\tif (likely(m->pool == free[0]->pool)) {\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_common.h b/drivers/net/i40e/i40e_rxtx_vec_common.h\nindex 8b74563..5633268 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_common.h\n+++ b/drivers/net/i40e/i40e_rxtx_vec_common.h\n@@ -189,7 +189,6 @@\n static inline int\n i40e_rxq_vec_setup_default(struct i40e_rx_queue *rxq)\n {\n-\tuintptr_t p;\n \tstruct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */\n \n \tmb_def.nb_segs = 1;\n@@ -199,8 +198,7 @@\n \n \t/* prevent compiler reordering: rearm_data covers previous fields */\n \trte_compiler_barrier();\n-\tp = (uintptr_t)&mb_def.rearm_data;\n-\trxq->mbuf_initializer = *(uint64_t *)p;\n+\trxq->mbuf_initializer = *rte_mbuf_rearm_data(&mb_def);\n \trxq->rx_using_sse = 1;\n \treturn 0;\n }\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_neon.c b/drivers/net/i40e/i40e_rxtx_vec_neon.c\nindex d873e30..29dfd92 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_neon.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_neon.c\n@@ -300,10 +300,10 @@\n \trearm2 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 2), mbuf_init, 1);\n \trearm3 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 3), mbuf_init, 1);\n \n-\tvst1q_u64((uint64_t *)&rx_pkts[0]->rearm_data, rearm0);\n-\tvst1q_u64((uint64_t *)&rx_pkts[1]->rearm_data, rearm1);\n-\tvst1q_u64((uint64_t *)&rx_pkts[2]->rearm_data, rearm2);\n-\tvst1q_u64((uint64_t *)&rx_pkts[3]->rearm_data, rearm3);\n+\tvst1q_u64(rte_mbuf_rearm_data(rx_pkts[0]), rearm0);\n+\tvst1q_u64(rte_mbuf_rearm_data(rx_pkts[1]), rearm1);\n+\tvst1q_u64(rte_mbuf_rearm_data(rx_pkts[2]), rearm2);\n+\tvst1q_u64(rte_mbuf_rearm_data(rx_pkts[3]), rearm3);\n }\n \n #define PKTLEN_SHIFT 10\n@@ -492,13 +492,13 @@\n \t\tpkt_mb1 = vreinterpretq_u8_u16(tmp);\n \n \t\t/* D.3 copy final data to rx_pkts */\n-\t\tvst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,\n+\t\tvst1q_u8(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 3]),\n \t\t\t\tpkt_mb4);\n-\t\tvst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,\n+\t\tvst1q_u8(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 2]),\n \t\t\t\tpkt_mb3);\n-\t\tvst1q_u8((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,\n+\t\tvst1q_u8(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 1]),\n \t\t\t\tpkt_mb2);\n-\t\tvst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,\n+\t\tvst1q_u8(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos]),\n \t\t\t\tpkt_mb1);\n \n \t\tdesc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_sse.c b/drivers/net/i40e/i40e_rxtx_vec_sse.c\nindex 2d4480a..994c5e1 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_sse.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_sse.c\n@@ -315,14 +315,10 @@\n \trearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);\n \n \t/* write the rearm data and the olflags in one write */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n-\t\t\toffsetof(struct rte_mbuf, rearm_data) + 8);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=\n-\t\t\tRTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));\n-\t_mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);\n-\t_mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);\n-\t_mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);\n-\t_mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);\n+\t_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[0]), rearm0);\n+\t_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[1]), rearm1);\n+\t_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[2]), rearm2);\n+\t_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[3]), rearm3);\n }\n \n #define PKTLEN_SHIFT 10\n@@ -369,15 +365,7 @@\n \t\t\t\t-rxq->crc_len, /* sub crc on pkt_len */\n \t\t\t\t0, 0 /* ignore pkt_type field */\n \t\t\t);\n-\t/*\n-\t * compile-time check the above crc_adjust layout is correct.\n-\t * NOTE: the first field (lowest address) is given last in set_epi16\n-\t * call above.\n-\t */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n+\n \t__m128i dd_check, eop_check;\n \n \t/* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */\n@@ -419,19 +407,6 @@\n \t\t0xFF, 0xFF, /* pkt_type set as unknown */\n \t\t0xFF, 0xFF /*pkt_type set as unknown */\n \t\t);\n-\t/*\n-\t * Compile-time verify the shuffle mask\n-\t * NOTE: some field positions already verified above, but duplicated\n-\t * here for completeness in case of future modifications.\n-\t */\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=\n-\t\t\toffsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);\n \n \t/* Cache is empty -> need to scan the buffer rings, but first move\n \t * the next 'n' mbufs into the cache\n@@ -535,9 +510,9 @@\n \t\tstaterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);\n \n \t\t/* D.3 copy final 3,4 data to rx_pkts */\n-\t\t_mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,\n+\t\t_mm_storeu_si128(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 3]),\n \t\t\t\t pkt_mb4);\n-\t\t_mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,\n+\t\t_mm_storeu_si128(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 2]),\n \t\t\t\t pkt_mb3);\n \n \t\t/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */\n@@ -571,9 +546,9 @@\n \t\tstaterr = _mm_packs_epi32(staterr, zero);\n \n \t\t/* D.3 copy final 1,2 data to rx_pkts */\n-\t\t_mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,\n+\t\t_mm_storeu_si128(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 1]),\n \t\t\t\t pkt_mb2);\n-\t\t_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,\n+\t\t_mm_storeu_si128(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos]),\n \t\t\t\t pkt_mb1);\n \t\tdesc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);\n \t\t/* C.4 calc available number of desc */\n", "prefixes": [ "v6", "09/23" ] }