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GET /api/patches/137237/?format=api
{ "id": 137237, "url": "http://patches.dpdk.org/api/patches/137237/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240226170818.533793-5-ciara.power@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240226170818.533793-5-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240226170818.533793-5-ciara.power@intel.com", "date": "2024-02-26T17:08:18", "name": "[v3,4/4] common/qat: add gen5 device", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5b606612391163b9034b0c3a95eec5430decaaf0", "submitter": { "id": 978, "url": "http://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240226170818.533793-5-ciara.power@intel.com/mbox/", "series": [ { "id": 31228, "url": "http://patches.dpdk.org/api/series/31228/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31228", "date": "2024-02-26T17:08:14", "name": "add new QAT gen3 and gen5", "version": 3, "mbox": "http://patches.dpdk.org/series/31228/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137237/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137237/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C260143BF1;\n\tMon, 26 Feb 2024 18:08:54 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 16CEE42E6F;\n\tMon, 26 Feb 2024 18:08:34 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.14])\n by mails.dpdk.org (Postfix) with ESMTP id 768C442E6F\n for <dev@dpdk.org>; Mon, 26 Feb 2024 18:08:32 +0100 (CET)", "from orviesa002.jf.intel.com ([10.64.159.142])\n by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Feb 2024 09:08:32 -0800", "from silpixa00401797.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.113])\n by orviesa002.jf.intel.com with ESMTP; 26 Feb 2024 09:08:29 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1708967313; x=1740503313;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=IOmhxa+wEE9KAgah/rgHbg6fwhExhdqn4xxm3f5JCIQ=;\n b=L5Y7OEjteEKHJjTVoEm0iT9WUriQLlWrjVVNFay45cC79DQ4xA8QVmIo\n UZEgDBeTFgBKq884TGQhO2G/z+rlwH30EfJYVKg/8b043SBs5/RCJqCVz\n /wGR+gnszxjIoqsf3vLjhvFqqNnTYE1ZSw/9OyH8e+q58jn4kaugVvAGc\n MdzenZak3U4T945y2NCCHIYzAmUlxEfrtaSE32EYBSLcG0hCY4L5Cm87l\n h5kSAM8FTaEdOnCPWcHUOEpGKEwuYBI6l/9ij+ICK7dGy1dN1eoCEsDrW\n fp/LV5u0ne0RT94pvNTNRKx8EL1hPh45yMIF1eNFfEsaO3kgmh6zKwzfH g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10996\"; a=\"3429574\"", "E=Sophos;i=\"6.06,186,1705392000\";\n d=\"scan'208\";a=\"3429574\"", "E=Sophos;i=\"6.06,186,1705392000\"; d=\"scan'208\";a=\"37519756\"" ], "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "arkadiuszx.kusztal@intel.com, gakhil@marvell.com,\n Ciara Power <ciara.power@intel.com>, Kai Ji <kai.ji@intel.com>,\n Fan Zhang <fanzhang.oss@gmail.com>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>", "Subject": "[PATCH v3 4/4] common/qat: add gen5 device", "Date": "Mon, 26 Feb 2024 17:08:18 +0000", "Message-Id": "<20240226170818.533793-5-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240226170818.533793-1-ciara.power@intel.com>", "References": "<20231219155124.4133385-1-ciara.power@intel.com>\n <20240226170818.533793-1-ciara.power@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add new gen5 QAT device ID.\nThis device has a wireless slice, so we must set a flag to indicate\nthis wireless enabled device.\nAsides from the wireless slices and some extra capabilities for\nwireless algorithms, the device is functionally the same as gen4 and can\nreuse most functions and macros.\n\nSymmetric, asymmetric and compression services are enabled.\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\nAcked-by: Kai Ji <kai.ji@intel.com>\n---\nv3:\n - Fixed copyright tag in new files to 2024.\n - Removed v2 changes in notes of commit, this patch was new in v2.\n---\n doc/guides/cryptodevs/qat.rst | 4 +\n doc/guides/rel_notes/release_24_03.rst | 6 +-\n drivers/common/qat/dev/qat_dev_gen4.c | 31 ++-\n drivers/common/qat/dev/qat_dev_gen5.c | 51 ++++\n drivers/common/qat/dev/qat_dev_gens.h | 54 ++++\n drivers/common/qat/meson.build | 3 +\n drivers/common/qat/qat_common.h | 1 +\n drivers/common/qat/qat_device.c | 8 +-\n drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 8 +-\n drivers/compress/qat/dev/qat_comp_pmd_gen5.c | 73 +++++\n drivers/compress/qat/dev/qat_comp_pmd_gens.h | 14 +\n drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 4 +-\n drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c | 278 +++++++++++++++++++\n drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 6 +\n drivers/crypto/qat/qat_sym_session.c | 13 +-\n 15 files changed, 524 insertions(+), 30 deletions(-)\n create mode 100644 drivers/common/qat/dev/qat_dev_gen5.c\n create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen5.c\n create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c", "diff": "diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex 51190e12d6..28945bb5f3 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -27,6 +27,7 @@ poll mode crypto driver support for the following hardware accelerator devices:\n * ``Intel QuickAssist Technology C4xxx``\n * ``Intel QuickAssist Technology 4xxx``\n * ``Intel QuickAssist Technology 300xx``\n+* ``Intel QuickAssist Technology 420xx``\n \n \n Features\n@@ -179,6 +180,7 @@ poll mode crypto driver support for the following hardware accelerator devices:\n * ``Intel QuickAssist Technology 4xxx``\n * ``Intel QuickAssist Technology 401xxx``\n * ``Intel QuickAssist Technology 300xx``\n+* ``Intel QuickAssist Technology 420xx``\n \n The QAT ASYM PMD has support for:\n \n@@ -472,6 +474,8 @@ to see the full table)\n +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+\n | Yes | No | No | 4 | 402xx | IDZ/ N/A | qat_4xxx | 4xxx | 4944 | 2 | 4945 | 16 |\n +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+\n+ | Yes | Yes | Yes | 5 | 420xx | linux/6.8+ | qat_420xx | 420xx | 4946 | 2 | 4947 | 16 |\n+ +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+\n \n * Note: Symmetric mixed crypto algorithms feature on Gen 2 works only with IDZ driver version 4.9.0+\n \ndiff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 0dee1ff104..439d354cd8 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -133,8 +133,10 @@ New Features\n \n * **Updated Intel QuickAssist Technology driver.**\n \n- * Enabled support for new QAT GEN3 (578a) devices in QAT crypto driver.\n- * Enabled ZUC256 cipher and auth algorithm for wireless slice enabled GEN3 device.\n+ * Enabled support for new QAT GEN3 (578a) and QAT GEN5 (4946)\n+ devices in QAT crypto driver.\n+ * Enabled ZUC256 cipher and auth algorithm for wireless slice\n+ enabled GEN3 and GEN5 devices.\n \n * **Updated Marvell cnxk crypto driver.**\n \ndiff --git a/drivers/common/qat/dev/qat_dev_gen4.c b/drivers/common/qat/dev/qat_dev_gen4.c\nindex 1ce262f715..2525e1e695 100644\n--- a/drivers/common/qat/dev/qat_dev_gen4.c\n+++ b/drivers/common/qat/dev/qat_dev_gen4.c\n@@ -10,6 +10,7 @@\n #include \"adf_transport_access_macros_gen4vf.h\"\n #include \"adf_pf2vf_msg.h\"\n #include \"qat_pf2vf.h\"\n+#include \"qat_dev_gens.h\"\n \n #include <stdint.h>\n \n@@ -60,7 +61,7 @@ qat_select_valid_queue_gen4(struct qat_pci_device *qat_dev, int qp_id,\n \treturn -1;\n }\n \n-static const struct qat_qp_hw_data *\n+const struct qat_qp_hw_data *\n qat_qp_get_hw_data_gen4(struct qat_pci_device *qat_dev,\n \t\tenum qat_service_type service_type, uint16_t qp_id)\n {\n@@ -74,7 +75,7 @@ qat_qp_get_hw_data_gen4(struct qat_pci_device *qat_dev,\n \treturn &dev_extra->qp_gen4_data[ring_pair][0];\n }\n \n-static int\n+int\n qat_qp_rings_per_service_gen4(struct qat_pci_device *qat_dev,\n \t\tenum qat_service_type service)\n {\n@@ -103,7 +104,7 @@ gen4_pick_service(uint8_t hw_service)\n \t}\n }\n \n-static int\n+int\n qat_dev_read_config_gen4(struct qat_pci_device *qat_dev)\n {\n \tint i = 0;\n@@ -143,7 +144,7 @@ qat_dev_read_config_gen4(struct qat_pci_device *qat_dev)\n \treturn 0;\n }\n \n-static void\n+void\n qat_qp_build_ring_base_gen4(void *io_addr,\n \t\t\tstruct qat_queue *queue)\n {\n@@ -155,7 +156,7 @@ qat_qp_build_ring_base_gen4(void *io_addr,\n \t\tqueue->hw_queue_number, queue_base);\n }\n \n-static void\n+void\n qat_qp_adf_arb_enable_gen4(const struct qat_queue *txq,\n \t\t\tvoid *base_addr, rte_spinlock_t *lock)\n {\n@@ -172,7 +173,7 @@ qat_qp_adf_arb_enable_gen4(const struct qat_queue *txq,\n \trte_spinlock_unlock(lock);\n }\n \n-static void\n+void\n qat_qp_adf_arb_disable_gen4(const struct qat_queue *txq,\n \t\t\tvoid *base_addr, rte_spinlock_t *lock)\n {\n@@ -189,7 +190,7 @@ qat_qp_adf_arb_disable_gen4(const struct qat_queue *txq,\n \trte_spinlock_unlock(lock);\n }\n \n-static void\n+void\n qat_qp_adf_configure_queues_gen4(struct qat_qp *qp)\n {\n \tuint32_t q_tx_config, q_resp_config;\n@@ -208,14 +209,14 @@ qat_qp_adf_configure_queues_gen4(struct qat_qp *qp)\n \t\tq_resp_config);\n }\n \n-static void\n+void\n qat_qp_csr_write_tail_gen4(struct qat_qp *qp, struct qat_queue *q)\n {\n \tWRITE_CSR_RING_TAIL_GEN4VF(qp->mmap_bar_addr,\n \t\tq->hw_bundle_number, q->hw_queue_number, q->tail);\n }\n \n-static void\n+void\n qat_qp_csr_write_head_gen4(struct qat_qp *qp, struct qat_queue *q,\n \t\t\tuint32_t new_head)\n {\n@@ -223,7 +224,7 @@ qat_qp_csr_write_head_gen4(struct qat_qp *qp, struct qat_queue *q,\n \t\t\tq->hw_bundle_number, q->hw_queue_number, new_head);\n }\n \n-static void\n+void\n qat_qp_csr_setup_gen4(struct qat_pci_device *qat_dev,\n \t\t\tvoid *io_addr, struct qat_qp *qp)\n {\n@@ -246,7 +247,7 @@ static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen4 = {\n \t.qat_qp_get_hw_data = qat_qp_get_hw_data_gen4,\n };\n \n-static int\n+int\n qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev)\n {\n \tint ret = 0, i;\n@@ -268,13 +269,13 @@ qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev)\n \treturn 0;\n }\n \n-static const struct rte_mem_resource *\n+const struct rte_mem_resource *\n qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev)\n {\n \treturn &pci_dev->mem_resource[0];\n }\n \n-static int\n+int\n qat_dev_get_misc_bar_gen4(struct rte_mem_resource **mem_resource,\n \t\tstruct rte_pci_device *pci_dev)\n {\n@@ -282,14 +283,14 @@ qat_dev_get_misc_bar_gen4(struct rte_mem_resource **mem_resource,\n \treturn 0;\n }\n \n-static int\n+int\n qat_dev_get_slice_map_gen4(uint32_t *map __rte_unused,\n \tconst struct rte_pci_device *pci_dev __rte_unused)\n {\n \treturn 0;\n }\n \n-static int\n+int\n qat_dev_get_extra_size_gen4(void)\n {\n \treturn sizeof(struct qat_dev_gen4_extra);\ndiff --git a/drivers/common/qat/dev/qat_dev_gen5.c b/drivers/common/qat/dev/qat_dev_gen5.c\nnew file mode 100644\nindex 0000000000..b79187b4d0\n--- /dev/null\n+++ b/drivers/common/qat/dev/qat_dev_gen5.c\n@@ -0,0 +1,51 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#include <dev_driver.h>\n+#include <rte_pci.h>\n+\n+#include \"qat_device.h\"\n+#include \"qat_qp.h\"\n+#include \"adf_pf2vf_msg.h\"\n+#include \"qat_dev_gens.h\"\n+\n+#include <stdint.h>\n+\n+static struct qat_pf2vf_dev qat_pf2vf_gen5 = {\n+\t.pf2vf_offset = ADF_4XXXIOV_PF2VM_OFFSET,\n+\t.vf2pf_offset = ADF_4XXXIOV_VM2PF_OFFSET,\n+\t.pf2vf_type_shift = ADF_PFVF_2X_MSGTYPE_SHIFT,\n+\t.pf2vf_type_mask = ADF_PFVF_2X_MSGTYPE_MASK,\n+\t.pf2vf_data_shift = ADF_PFVF_2X_MSGDATA_SHIFT,\n+\t.pf2vf_data_mask = ADF_PFVF_2X_MSGDATA_MASK,\n+};\n+\n+static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen5 = {\n+\t.qat_qp_rings_per_service = qat_qp_rings_per_service_gen4,\n+\t.qat_qp_build_ring_base = qat_qp_build_ring_base_gen4,\n+\t.qat_qp_adf_arb_enable = qat_qp_adf_arb_enable_gen4,\n+\t.qat_qp_adf_arb_disable = qat_qp_adf_arb_disable_gen4,\n+\t.qat_qp_adf_configure_queues = qat_qp_adf_configure_queues_gen4,\n+\t.qat_qp_csr_write_tail = qat_qp_csr_write_tail_gen4,\n+\t.qat_qp_csr_write_head = qat_qp_csr_write_head_gen4,\n+\t.qat_qp_csr_setup = qat_qp_csr_setup_gen4,\n+\t.qat_qp_get_hw_data = qat_qp_get_hw_data_gen4,\n+};\n+\n+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen5 = {\n+\t.qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen4,\n+\t.qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen4,\n+\t.qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen4,\n+\t.qat_dev_read_config = qat_dev_read_config_gen4,\n+\t.qat_dev_get_extra_size = qat_dev_get_extra_size_gen4,\n+\t.qat_dev_get_slice_map = qat_dev_get_slice_map_gen4,\n+};\n+\n+RTE_INIT(qat_dev_gen_5_init)\n+{\n+\tqat_qp_hw_spec[QAT_GEN5] = &qat_qp_hw_spec_gen5;\n+\tqat_dev_hw_spec[QAT_GEN5] = &qat_dev_hw_spec_gen5;\n+\tqat_gen_config[QAT_GEN5].dev_gen = QAT_GEN5;\n+\tqat_gen_config[QAT_GEN5].pf2vf_dev = &qat_pf2vf_gen5;\n+}\ndiff --git a/drivers/common/qat/dev/qat_dev_gens.h b/drivers/common/qat/dev/qat_dev_gens.h\nindex 7c92f1938c..14c172f22d 100644\n--- a/drivers/common/qat/dev/qat_dev_gens.h\n+++ b/drivers/common/qat/dev/qat_dev_gens.h\n@@ -62,4 +62,58 @@ qat_dev_get_misc_bar_gen1(struct rte_mem_resource **mem_resource,\n int\n qat_dev_read_config_gen1(struct qat_pci_device *qat_dev);\n \n+int\n+qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev);\n+\n+const struct rte_mem_resource *\n+qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev);\n+\n+int\n+qat_dev_get_misc_bar_gen4(struct rte_mem_resource **mem_resource,\n+\t\tstruct rte_pci_device *pci_dev);\n+\n+int\n+qat_dev_read_config_gen4(struct qat_pci_device *qat_dev);\n+\n+int\n+qat_dev_get_extra_size_gen4(void);\n+\n+int\n+qat_dev_get_slice_map_gen4(uint32_t *map __rte_unused,\n+\tconst struct rte_pci_device *pci_dev __rte_unused);\n+\n+int\n+qat_qp_rings_per_service_gen4(struct qat_pci_device *qat_dev,\n+\t\tenum qat_service_type service);\n+\n+void\n+qat_qp_build_ring_base_gen4(void *io_addr,\n+\t\t\tstruct qat_queue *queue);\n+\n+void\n+qat_qp_adf_arb_enable_gen4(const struct qat_queue *txq,\n+\t\t\tvoid *base_addr, rte_spinlock_t *lock);\n+\n+void\n+qat_qp_adf_arb_disable_gen4(const struct qat_queue *txq,\n+\t\t\tvoid *base_addr, rte_spinlock_t *lock);\n+\n+void\n+qat_qp_adf_configure_queues_gen4(struct qat_qp *qp);\n+\n+void\n+qat_qp_csr_write_tail_gen4(struct qat_qp *qp, struct qat_queue *q);\n+\n+void\n+qat_qp_csr_write_head_gen4(struct qat_qp *qp, struct qat_queue *q,\n+\t\t\tuint32_t new_head);\n+\n+void\n+qat_qp_csr_setup_gen4(struct qat_pci_device *qat_dev,\n+\t\t\tvoid *io_addr, struct qat_qp *qp);\n+\n+const struct qat_qp_hw_data *\n+qat_qp_get_hw_data_gen4(struct qat_pci_device *qat_dev,\n+\t\tenum qat_service_type service_type, uint16_t qp_id);\n+\n #endif\ndiff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build\nindex 62abcb6fe3..d79085258f 100644\n--- a/drivers/common/qat/meson.build\n+++ b/drivers/common/qat/meson.build\n@@ -82,6 +82,7 @@ sources += files(\n 'dev/qat_dev_gen2.c',\n 'dev/qat_dev_gen3.c',\n 'dev/qat_dev_gen4.c',\n+ 'dev/qat_dev_gen5.c',\n )\n includes += include_directories(\n 'qat_adf',\n@@ -95,6 +96,7 @@ if qat_compress\n 'dev/qat_comp_pmd_gen2.c',\n 'dev/qat_comp_pmd_gen3.c',\n 'dev/qat_comp_pmd_gen4.c',\n+ 'dev/qat_comp_pmd_gen5.c',\n ]\n sources += files(join_paths(qat_compress_relpath, f))\n endforeach\n@@ -108,6 +110,7 @@ if qat_crypto\n 'dev/qat_crypto_pmd_gen2.c',\n 'dev/qat_crypto_pmd_gen3.c',\n 'dev/qat_crypto_pmd_gen4.c',\n+ 'dev/qat_crypto_pmd_gen5.c',\n ]\n sources += files(join_paths(qat_crypto_relpath, f))\n endforeach\ndiff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h\nindex 9411a79301..dc48a2e1ee 100644\n--- a/drivers/common/qat/qat_common.h\n+++ b/drivers/common/qat/qat_common.h\n@@ -21,6 +21,7 @@ enum qat_device_gen {\n \tQAT_GEN2,\n \tQAT_GEN3,\n \tQAT_GEN4,\n+\tQAT_GEN5,\n \tQAT_N_GENS\n };\n \ndiff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c\nindex 0e7d387d78..0ccc3f85fd 100644\n--- a/drivers/common/qat/qat_device.c\n+++ b/drivers/common/qat/qat_device.c\n@@ -65,6 +65,9 @@ static const struct rte_pci_id pci_id_qat_map[] = {\n \t\t{\n \t\t\tRTE_PCI_DEVICE(0x8086, 0x4945),\n \t\t},\n+\t\t{\n+\t\t\tRTE_PCI_DEVICE(0x8086, 0x4947),\n+\t\t},\n \t\t{.device_id = 0},\n };\n \n@@ -203,6 +206,8 @@ pick_gen(const struct rte_pci_device *pci_dev)\n \tcase 0x4943:\n \tcase 0x4945:\n \t\treturn QAT_GEN4;\n+\tcase 0x4947:\n+\t\treturn QAT_GEN5;\n \tdefault:\n \t\tQAT_LOG(ERR, \"Invalid dev_id, can't determine generation\");\n \t\treturn QAT_N_GENS;\n@@ -212,7 +217,8 @@ pick_gen(const struct rte_pci_device *pci_dev)\n static int\n wireless_slice_support(uint16_t pci_dev_id)\n {\n-\treturn pci_dev_id == 0x578b;\n+\treturn pci_dev_id == 0x578b ||\n+\t\t\tpci_dev_id == 0x4947;\n }\n \n struct qat_pci_device *\ndiff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c\nindex 05906f13e0..68d111e07c 100644\n--- a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c\n+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c\n@@ -27,7 +27,7 @@ qat_gen4_comp_capabilities[] = {\n \t .window_size = {.min = 15, .max = 15, .increment = 0} },\n \t RTE_COMP_END_OF_CAPABILITIES_LIST() };\n \n-static int\n+int\n qat_comp_dev_config_gen4(struct rte_compressdev *dev,\n \t\tstruct rte_compressdev_config *config)\n {\n@@ -67,13 +67,13 @@ qat_comp_cap_get_gen4(struct qat_pci_device *qat_dev __rte_unused)\n \treturn capa_info;\n }\n \n-static uint16_t\n+uint16_t\n qat_comp_get_ram_bank_flags_gen4(void)\n {\n \treturn 0;\n }\n \n-static int\n+int\n qat_comp_set_slice_cfg_word_gen4(struct qat_comp_xform *qat_xform,\n \t\tconst struct rte_comp_xform *xform,\n \t\tenum rte_comp_op_type op_type, uint32_t *comp_slice_cfg_word)\n@@ -189,7 +189,7 @@ qat_comp_set_slice_cfg_word_gen4(struct qat_comp_xform *qat_xform,\n \treturn 0;\n }\n \n-static unsigned int\n+unsigned int\n qat_comp_get_num_im_bufs_required_gen4(void)\n {\n \treturn QAT_NUM_INTERM_BUFS_GEN4;\ndiff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen5.c b/drivers/compress/qat/dev/qat_comp_pmd_gen5.c\nnew file mode 100644\nindex 0000000000..3cfa07e605\n--- /dev/null\n+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen5.c\n@@ -0,0 +1,73 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#include \"qat_comp.h\"\n+#include \"qat_comp_pmd.h\"\n+#include \"qat_comp_pmd_gens.h\"\n+#include \"icp_qat_hw_gen4_comp.h\"\n+#include \"icp_qat_hw_gen4_comp_defs.h\"\n+\n+static const struct rte_compressdev_capabilities\n+qat_gen5_comp_capabilities[] = {\n+\t{/* COMPRESSION - deflate */\n+\t .algo = RTE_COMP_ALGO_DEFLATE,\n+\t .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_CRC32_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_ADLER32_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_CRC32_ADLER32_CHECKSUM |\n+\t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n+\t\t\t\tRTE_COMP_FF_HUFFMAN_FIXED |\n+\t\t\t\tRTE_COMP_FF_HUFFMAN_DYNAMIC |\n+\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_SGL_OUT |\n+\t\t\t\tRTE_COMP_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\t\tRTE_COMP_FF_OOP_LB_IN_SGL_OUT,\n+\t .window_size = {.min = 15, .max = 15, .increment = 0} },\n+\t RTE_COMP_END_OF_CAPABILITIES_LIST() };\n+\n+static struct rte_compressdev_ops qat_comp_ops_gen5 = {\n+\n+\t/* Device related operations */\n+\t.dev_configure\t\t= qat_comp_dev_config_gen4,\n+\t.dev_start\t\t= qat_comp_dev_start,\n+\t.dev_stop\t\t= qat_comp_dev_stop,\n+\t.dev_close\t\t= qat_comp_dev_close,\n+\t.dev_infos_get\t\t= qat_comp_dev_info_get,\n+\n+\t.stats_get\t\t= qat_comp_stats_get,\n+\t.stats_reset\t\t= qat_comp_stats_reset,\n+\t.queue_pair_setup\t= qat_comp_qp_setup,\n+\t.queue_pair_release\t= qat_comp_qp_release,\n+\n+\t/* Compression related operations */\n+\t.private_xform_create\t= qat_comp_private_xform_create,\n+\t.private_xform_free\t= qat_comp_private_xform_free,\n+\t.stream_create\t\t= qat_comp_stream_create,\n+\t.stream_free\t\t= qat_comp_stream_free\n+};\n+\n+static struct qat_comp_capabilities_info\n+qat_comp_cap_get_gen5(struct qat_pci_device *qat_dev __rte_unused)\n+{\n+\tstruct qat_comp_capabilities_info capa_info = {\n+\t\t.data = qat_gen5_comp_capabilities,\n+\t\t.size = sizeof(qat_gen5_comp_capabilities)\n+\t};\n+\treturn capa_info;\n+}\n+\n+RTE_INIT(qat_comp_pmd_gen5_init)\n+{\n+\tqat_comp_gen_dev_ops[QAT_GEN5].compressdev_ops =\n+\t\t\t&qat_comp_ops_gen5;\n+\tqat_comp_gen_dev_ops[QAT_GEN5].qat_comp_get_capabilities =\n+\t\t\tqat_comp_cap_get_gen5;\n+\tqat_comp_gen_dev_ops[QAT_GEN5].qat_comp_get_num_im_bufs_required =\n+\t\t\tqat_comp_get_num_im_bufs_required_gen4;\n+\tqat_comp_gen_dev_ops[QAT_GEN5].qat_comp_get_ram_bank_flags =\n+\t\t\tqat_comp_get_ram_bank_flags_gen4;\n+\tqat_comp_gen_dev_ops[QAT_GEN5].qat_comp_set_slice_cfg_word =\n+\t\t\tqat_comp_set_slice_cfg_word_gen4;\n+\tqat_comp_gen_dev_ops[QAT_GEN5].qat_comp_get_feature_flags =\n+\t\t\tqat_comp_get_features_gen1;\n+}\ndiff --git a/drivers/compress/qat/dev/qat_comp_pmd_gens.h b/drivers/compress/qat/dev/qat_comp_pmd_gens.h\nindex 67293092ea..e329fe3e18 100644\n--- a/drivers/compress/qat/dev/qat_comp_pmd_gens.h\n+++ b/drivers/compress/qat/dev/qat_comp_pmd_gens.h\n@@ -25,6 +25,20 @@ int qat_comp_set_slice_cfg_word_gen1(struct qat_comp_xform *qat_xform,\n \n uint64_t qat_comp_get_features_gen1(void);\n \n+unsigned int\n+qat_comp_get_num_im_bufs_required_gen4(void);\n+\n+int\n+qat_comp_set_slice_cfg_word_gen4(struct qat_comp_xform *qat_xform,\n+\t\tconst struct rte_comp_xform *xform,\n+\t\tenum rte_comp_op_type op_type, uint32_t *comp_slice_cfg_word);\n+\n+uint16_t qat_comp_get_ram_bank_flags_gen4(void);\n+\n+int\n+qat_comp_dev_config_gen4(struct rte_compressdev *dev,\n+\t\tstruct rte_compressdev_config *config);\n+\n extern struct rte_compressdev_ops qat_comp_ops_gen1;\n \n #endif /* _QAT_COMP_PMD_GENS_H_ */\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\nindex de72383d4b..9c7f7d98c8 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n@@ -233,7 +233,7 @@ qat_sym_build_op_aead_gen4(void *in_op, struct qat_sym_session *ctx,\n \treturn 0;\n }\n \n-static int\n+int\n qat_sym_crypto_set_session_gen4(void *cdev, void *session)\n {\n \tstruct qat_sym_session *ctx = session;\n@@ -385,7 +385,7 @@ qat_sym_dp_enqueue_aead_jobs_gen4(void *qp_data, uint8_t *drv_ctx,\n \treturn i;\n }\n \n-static int\n+int\n qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx)\n {\n \tstruct rte_crypto_raw_dp_ctx *raw_dp_ctx = _raw_dp_ctx;\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c\nnew file mode 100644\nindex 0000000000..1902430480\n--- /dev/null\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c\n@@ -0,0 +1,278 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n+#include \"qat_sym_session.h\"\n+#include \"qat_sym.h\"\n+#include \"qat_asym.h\"\n+#include \"qat_crypto.h\"\n+#include \"qat_crypto_pmd_gens.h\"\n+\n+\n+static struct rte_cryptodev_capabilities qat_sym_crypto_legacy_caps_gen5[] = {\n+\tQAT_SYM_PLAIN_AUTH_CAP(SHA1,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(digest_size, 1, 20, 1)),\n+\tQAT_SYM_AUTH_CAP(SHA224,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA224_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 28, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA1_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(SM4_ECB,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 0, 0, 0)),\n+};\n+\n+static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen5[] = {\n+\tQAT_SYM_CIPHER_CAP(AES_CBC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(SHA256_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512_HMAC,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(AES_XCBC_MAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 12, 12, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(AES_CMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 4),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(AES_DOCSISBPI,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(digest_size),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(NULL,\n+\t\tCAP_SET(block_size, 1),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA256,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 32, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA384,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 48, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_AUTH_CAP(SHA512,\n+\t\tCAP_SET(block_size, 128),\n+\t\tCAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(AES_CTR,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AEAD_CAP(AES_GCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AEAD_CAP(AES_CCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 2),\n+\t\tCAP_RNG(aad_size, 0, 224, 1), CAP_RNG(iv_size, 7, 13, 1)),\n+\tQAT_SYM_AUTH_CAP(AES_GMAC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 0, 12, 12)),\n+\tQAT_SYM_AEAD_CAP(CHACHA20_POLY1305,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 32, 32, 0),\n+\t\tCAP_RNG(digest_size, 16, 16, 0),\n+\t\tCAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)),\n+\tQAT_SYM_CIPHER_CAP(SM4_CBC,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_CIPHER_CAP(SM4_CTR,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_PLAIN_AUTH_CAP(SM3,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(digest_size, 32, 32, 0)),\n+\tQAT_SYM_AUTH_CAP(SM3_HMAC,\n+\t\tCAP_SET(block_size, 64),\n+\t\tCAP_RNG(key_size, 16, 64, 4), CAP_RNG(digest_size, 32, 32, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),\n+\tQAT_SYM_CIPHER_CAP(ZUC_EEA3,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 25, 1)),\n+\tQAT_SYM_AUTH_CAP(ZUC_EIA3,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 32, 16), CAP_RNG(digest_size, 4, 16, 4),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 25, 1)),\n+\tQAT_SYM_CIPHER_CAP(SNOW3G_UEA2,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),\n+\tQAT_SYM_AUTH_CAP(SNOW3G_UIA2,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),\n+\t\tCAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)),\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+static int\n+check_cipher_capa(const struct rte_cryptodev_capabilities *cap,\n+\t\tenum rte_crypto_cipher_algorithm algo)\n+{\n+\tif (cap->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)\n+\t\treturn 0;\n+\tif (cap->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)\n+\t\treturn 0;\n+\tif (cap->sym.cipher.algo != algo)\n+\t\treturn 0;\n+\treturn 1;\n+}\n+\n+static int\n+check_auth_capa(const struct rte_cryptodev_capabilities *cap,\n+\t\tenum rte_crypto_auth_algorithm algo)\n+{\n+\tif (cap->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)\n+\t\treturn 0;\n+\tif (cap->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)\n+\t\treturn 0;\n+\tif (cap->sym.auth.algo != algo)\n+\t\treturn 0;\n+\treturn 1;\n+}\n+\n+static int\n+qat_sym_crypto_cap_get_gen5(struct qat_cryptodev_private *internals,\n+\t\t\tconst char *capa_memz_name,\n+\t\t\tconst uint16_t __rte_unused slice_map)\n+{\n+\tuint32_t legacy_capa_num, capa_num;\n+\tuint32_t size = sizeof(qat_sym_crypto_caps_gen5);\n+\tuint32_t legacy_size = sizeof(qat_sym_crypto_legacy_caps_gen5);\n+\tuint32_t i, iter = 0;\n+\tuint32_t curr_capa = 0;\n+\tlegacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities);\n+\tcapa_num = RTE_DIM(qat_sym_crypto_caps_gen5);\n+\n+\tif (unlikely(qat_legacy_capa))\n+\t\tsize = size + legacy_size;\n+\n+\tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n+\tif (internals->capa_mz == NULL) {\n+\t\tinternals->capa_mz = rte_memzone_reserve(capa_memz_name,\n+\t\t\t\tsize, rte_socket_id(), 0);\n+\t\tif (internals->capa_mz == NULL) {\n+\t\t\tQAT_LOG(DEBUG,\n+\t\t\t\t\"Error allocating memzone for capabilities\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tstruct rte_cryptodev_capabilities *addr =\n+\t\t\t(struct rte_cryptodev_capabilities *)\n+\t\t\t\tinternals->capa_mz->addr;\n+\n+\tstruct rte_cryptodev_capabilities *capabilities;\n+\n+\tif (unlikely(qat_legacy_capa)) {\n+\t\tcapabilities = qat_sym_crypto_legacy_caps_gen5;\n+\t\tmemcpy(addr, capabilities, legacy_size);\n+\t\taddr += legacy_capa_num;\n+\t}\n+\tcapabilities = qat_sym_crypto_caps_gen5;\n+\n+\tfor (i = 0; i < capa_num; i++, iter++) {\n+\t\tif (slice_map & ICP_ACCEL_MASK_ZUC_256_SLICE && (\n+\t\t\tcheck_auth_capa(&capabilities[iter],\n+\t\t\t\tRTE_CRYPTO_AUTH_ZUC_EIA3) ||\n+\t\t\tcheck_cipher_capa(&capabilities[iter],\n+\t\t\t\tRTE_CRYPTO_CIPHER_ZUC_EEA3))) {\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tmemcpy(addr + curr_capa, capabilities + iter,\n+\t\t\tsizeof(struct rte_cryptodev_capabilities));\n+\t\tcurr_capa++;\n+\t}\n+\tinternals->qat_dev_capabilities = internals->capa_mz->addr;\n+\n+\treturn 0;\n+}\n+\n+static int\n+qat_sym_crypto_set_session_gen5(void *cdev, void *session)\n+{\n+\tstruct qat_sym_session *ctx = session;\n+\tenum rte_proc_type_t proc_type = rte_eal_process_type();\n+\tint ret;\n+\n+\tif (proc_type == RTE_PROC_AUTO || proc_type == RTE_PROC_INVALID)\n+\t\treturn -EINVAL;\n+\n+\tret = qat_sym_crypto_set_session_gen4(cdev, session);\n+\n+\tif (ret == -ENOTSUP) {\n+\t\t/* GEN4 returning -ENOTSUP as it cannot handle some mixed algo,\n+\t\t * this is addressed by GEN5\n+\t\t */\n+\t\tif ((ctx->aes_cmac ||\n+\t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) &&\n+\t\t\t\t(ctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n+\t\t\t\tctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 ||\n+\t\t\t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_256)) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx, 0);\n+\t\t} else if ((ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 ||\n+\t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64 ||\n+\t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128) &&\n+\t\t\t\tctx->qat_cipher_alg != ICP_QAT_HW_CIPHER_ALGO_ZUC_256) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx,\n+\t\t\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);\n+\t\t}\n+\n+\t\tret = 0;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+RTE_INIT(qat_sym_crypto_gen5_init)\n+{\n+\tqat_sym_gen_dev_ops[QAT_GEN5].cryptodev_ops = &qat_sym_crypto_ops_gen1;\n+\tqat_sym_gen_dev_ops[QAT_GEN5].get_capabilities =\n+\t\t\tqat_sym_crypto_cap_get_gen5;\n+\tqat_sym_gen_dev_ops[QAT_GEN5].set_session =\n+\t\t\tqat_sym_crypto_set_session_gen5;\n+\tqat_sym_gen_dev_ops[QAT_GEN5].set_raw_dp_ctx =\n+\t\t\tqat_sym_configure_raw_dp_ctx_gen4;\n+\tqat_sym_gen_dev_ops[QAT_GEN5].get_feature_flags =\n+\t\t\tqat_sym_crypto_feature_flags_get_gen1;\n+\tqat_sym_gen_dev_ops[QAT_GEN5].create_security_ctx =\n+\t\t\tqat_sym_create_security_gen1;\n+}\n+\n+RTE_INIT(qat_asym_crypto_gen5_init)\n+{\n+\tqat_asym_gen_dev_ops[QAT_GEN5].cryptodev_ops =\n+\t\t\t&qat_asym_crypto_ops_gen1;\n+\tqat_asym_gen_dev_ops[QAT_GEN5].get_capabilities =\n+\t\t\tqat_asym_crypto_cap_get_gen1;\n+\tqat_asym_gen_dev_ops[QAT_GEN5].get_feature_flags =\n+\t\t\tqat_asym_crypto_feature_flags_get_gen1;\n+\tqat_asym_gen_dev_ops[QAT_GEN5].set_session =\n+\t\t\tqat_asym_crypto_set_session_gen1;\n+}\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\nindex ff7ba55c01..60b0f0551c 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n@@ -1048,10 +1048,16 @@ qat_sym_crypto_feature_flags_get_gen1(struct qat_pci_device *qat_dev);\n int\n qat_sym_crypto_set_session_gen1(void *cryptodev, void *session);\n \n+int\n+qat_sym_crypto_set_session_gen4(void *cryptodev, void *session);\n+\n void\n qat_sym_session_set_ext_hash_flags_gen2(struct qat_sym_session *session,\n \t\tuint8_t hash_flag);\n \n+int\n+qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx);\n+\n int\n qat_asym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals,\n \t\t\tconst char *capa_memz_name, const uint16_t slice_map);\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex b1649b8d18..39e4a833ec 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -407,7 +407,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n \t\t\tgoto error_out;\n \t\t}\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n-\t\tif (qat_dev_gen == QAT_GEN4)\n+\t\tif (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5)\n \t\t\tsession->is_ucs = 1;\n \t\tbreak;\n \tcase RTE_CRYPTO_CIPHER_SNOW3G_UEA2:\n@@ -950,7 +950,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\tsession->auth_iv.length = AES_GCM_J0_LEN;\n \t\telse\n \t\t\tsession->is_iv12B = 1;\n-\t\tif (qat_dev_gen == QAT_GEN4) {\n+\t\tif (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) {\n \t\t\tsession->is_cnt_zero = 1;\n \t\t\tsession->is_ucs = 1;\n \t\t}\n@@ -1126,7 +1126,7 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n \n-\t\tif (qat_dev_gen == QAT_GEN4)\n+\t\tif (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5)\n \t\t\tsession->is_ucs = 1;\n \t\tif (session->cipher_iv.length == 0) {\n \t\t\tsession->cipher_iv.length = AES_GCM_J0_LEN;\n@@ -1146,13 +1146,13 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\t}\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC;\n-\t\tif (qat_dev_gen == QAT_GEN4)\n+\t\tif (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5)\n \t\t\tsession->is_ucs = 1;\n \t\tbreak;\n \tcase RTE_CRYPTO_AEAD_CHACHA20_POLY1305:\n \t\tif (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ)\n \t\t\treturn -EINVAL;\n-\t\tif (qat_dev_gen == QAT_GEN4)\n+\t\tif (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5)\n \t\t\tsession->is_ucs = 1;\n \t\tsession->qat_cipher_alg =\n \t\t\t\tICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305;\n@@ -2418,7 +2418,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\tauth_param->u2.inner_prefix_sz =\n \t\t\tqat_hash_get_block_size(cdesc->qat_hash_alg);\n \t\tauth_param->hash_state_sz = digestsize;\n-\t\tif (qat_dev_gen == QAT_GEN4) {\n+\t\tif (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) {\n \t\t\tICP_QAT_FW_HASH_FLAG_MODE2_SET(\n \t\t\t\thash_cd_ctrl->hash_flags,\n \t\t\t\tQAT_FW_LA_MODE2);\n@@ -2984,6 +2984,7 @@ qat_sym_cd_crc_set(struct qat_sym_session *cdesc,\n \t\tcdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_gen3_crc_cd);\n \t\tbreak;\n \tcase QAT_GEN4:\n+\tcase QAT_GEN5:\n \t\tcrc_cfg.mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n \t\tcrc_cfg.algo = ICP_QAT_HW_CIPHER_ALGO_NULL;\n \t\tcrc_cfg.hash_cmp_val = 0;\n", "prefixes": [ "v3", "4/4" ] }