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GET /api/patches/137186/?format=api
{ "id": 137186, "url": "http://patches.dpdk.org/api/patches/137186/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240226030739.3775514-6-haijie1@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240226030739.3775514-6-haijie1@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240226030739.3775514-6-haijie1@huawei.com", "date": "2024-02-26T03:07:37", "name": "[v4,5/7] net/hns3: add names for registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "69197f04de05ee40b414fc9bbb424f37cc7bb020", "submitter": { "id": 2935, "url": "http://patches.dpdk.org/api/people/2935/?format=api", "name": "Jie Hai", "email": "haijie1@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240226030739.3775514-6-haijie1@huawei.com/mbox/", "series": [ { "id": 31212, "url": "http://patches.dpdk.org/api/series/31212/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31212", "date": "2024-02-26T03:07:32", "name": "support dump reigser names and filter them", "version": 4, "mbox": "http://patches.dpdk.org/series/31212/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137186/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/137186/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4C98343BDE;\n\tMon, 26 Feb 2024 04:12:26 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B09FA42DE3;\n\tMon, 26 Feb 2024 04:12:05 +0100 (CET)", "from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189])\n by mails.dpdk.org (Postfix) with ESMTP id 06D1E402C2\n for <dev@dpdk.org>; Mon, 26 Feb 2024 04:11:57 +0100 (CET)", "from mail.maildlp.com (unknown [172.19.163.48])\n by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4Tjlwz2NNVzNlmd;\n Mon, 26 Feb 2024 11:10:27 +0800 (CST)", "from kwepemd100004.china.huawei.com (unknown [7.221.188.31])\n by mail.maildlp.com (Postfix) with ESMTPS id 61FFD180068;\n Mon, 26 Feb 2024 11:11:55 +0800 (CST)", "from localhost.localdomain (10.67.165.2) by\n kwepemd100004.china.huawei.com (7.221.188.31) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.2.1258.28; Mon, 26 Feb 2024 11:11:54 +0800" ], "From": "Jie Hai <haijie1@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<lihuisong@huawei.com>, <fengchengwen@huawei.com>,\n <liuyonglong@huawei.com>, <huangdengdui@huawei.com>, <ferruh.yigit@amd.com>", "Subject": "[PATCH v4 5/7] net/hns3: add names for registers", "Date": "Mon, 26 Feb 2024 11:07:37 +0800", "Message-ID": "<20240226030739.3775514-6-haijie1@huawei.com>", "X-Mailer": "git-send-email 2.30.0", "In-Reply-To": "<20240226030739.3775514-1-haijie1@huawei.com>", "References": "<20231214015650.3738578-1-haijie1@huawei.com>\n <20240226030739.3775514-1-haijie1@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.165.2]", "X-ClientProxiedBy": "dggems705-chm.china.huawei.com (10.3.19.182) To\n kwepemd100004.china.huawei.com (7.221.188.31)", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds names for all registers to be dumped.\nFor those who can be directly accessed by their addresses,\na new structure containing both name and address is added\nand the related arrays is refactored and renamed.\n\nFor the remaining modules, there may be different meanings\non different platforms for the same field. Therefore, two\nname fields are provided.\n\nThere are some 64-bit registers, dump them as two 32-bit\nregisters.\n\nSigned-off-by: Jie Hai <haijie1@huawei.com>\n---\n drivers/net/hns3/hns3_regs.c | 877 ++++++++++++++++++++++++++++++++---\n 1 file changed, 801 insertions(+), 76 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c\nindex b1c0d538a3c8..b7e4f78eecde 100644\n--- a/drivers/net/hns3/hns3_regs.c\n+++ b/drivers/net/hns3/hns3_regs.c\n@@ -14,67 +14,84 @@\n \n static int hns3_get_dfx_reg_cnt(struct hns3_hw *hw, uint32_t *count);\n \n-static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,\n-\t\t\t\t\t HNS3_CMDQ_TX_ADDR_H_REG,\n-\t\t\t\t\t HNS3_CMDQ_TX_DEPTH_REG,\n-\t\t\t\t\t HNS3_CMDQ_TX_TAIL_REG,\n-\t\t\t\t\t HNS3_CMDQ_TX_HEAD_REG,\n-\t\t\t\t\t HNS3_CMDQ_RX_ADDR_L_REG,\n-\t\t\t\t\t HNS3_CMDQ_RX_ADDR_H_REG,\n-\t\t\t\t\t HNS3_CMDQ_RX_DEPTH_REG,\n-\t\t\t\t\t HNS3_CMDQ_RX_TAIL_REG,\n-\t\t\t\t\t HNS3_CMDQ_RX_HEAD_REG,\n-\t\t\t\t\t HNS3_VECTOR0_CMDQ_SRC_REG,\n-\t\t\t\t\t HNS3_CMDQ_INTR_STS_REG,\n-\t\t\t\t\t HNS3_CMDQ_INTR_EN_REG,\n-\t\t\t\t\t HNS3_CMDQ_INTR_GEN_REG};\n-\n-static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,\n-\t\t\t\t\t HNS3_VECTOR0_OTER_EN_REG,\n-\t\t\t\t\t HNS3_MISC_RESET_STS_REG,\n-\t\t\t\t\t HNS3_VECTOR0_OTHER_INT_STS_REG,\n-\t\t\t\t\t HNS3_GLOBAL_RESET_REG,\n-\t\t\t\t\t HNS3_FUN_RST_ING,\n-\t\t\t\t\t HNS3_GRO_EN_REG};\n-\n-static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,\n-\t\t\t\t\t HNS3_FUN_RST_ING,\n-\t\t\t\t\t HNS3_GRO_EN_REG};\n-\n-static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,\n-\t\t\t\t\t HNS3_RING_RX_BASEADDR_H_REG,\n-\t\t\t\t\t HNS3_RING_RX_BD_NUM_REG,\n-\t\t\t\t\t HNS3_RING_RX_BD_LEN_REG,\n-\t\t\t\t\t HNS3_RING_RX_EN_REG,\n-\t\t\t\t\t HNS3_RING_RX_MERGE_EN_REG,\n-\t\t\t\t\t HNS3_RING_RX_TAIL_REG,\n-\t\t\t\t\t HNS3_RING_RX_HEAD_REG,\n-\t\t\t\t\t HNS3_RING_RX_FBDNUM_REG,\n-\t\t\t\t\t HNS3_RING_RX_OFFSET_REG,\n-\t\t\t\t\t HNS3_RING_RX_FBD_OFFSET_REG,\n-\t\t\t\t\t HNS3_RING_RX_STASH_REG,\n-\t\t\t\t\t HNS3_RING_RX_BD_ERR_REG,\n-\t\t\t\t\t HNS3_RING_TX_BASEADDR_L_REG,\n-\t\t\t\t\t HNS3_RING_TX_BASEADDR_H_REG,\n-\t\t\t\t\t HNS3_RING_TX_BD_NUM_REG,\n-\t\t\t\t\t HNS3_RING_TX_EN_REG,\n-\t\t\t\t\t HNS3_RING_TX_PRIORITY_REG,\n-\t\t\t\t\t HNS3_RING_TX_TC_REG,\n-\t\t\t\t\t HNS3_RING_TX_MERGE_EN_REG,\n-\t\t\t\t\t HNS3_RING_TX_TAIL_REG,\n-\t\t\t\t\t HNS3_RING_TX_HEAD_REG,\n-\t\t\t\t\t HNS3_RING_TX_FBDNUM_REG,\n-\t\t\t\t\t HNS3_RING_TX_OFFSET_REG,\n-\t\t\t\t\t HNS3_RING_TX_EBD_NUM_REG,\n-\t\t\t\t\t HNS3_RING_TX_EBD_OFFSET_REG,\n-\t\t\t\t\t HNS3_RING_TX_BD_ERR_REG,\n-\t\t\t\t\t HNS3_RING_EN_REG};\n-\n-static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,\n-\t\t\t\t\t HNS3_TQP_INTR_GL0_REG,\n-\t\t\t\t\t HNS3_TQP_INTR_GL1_REG,\n-\t\t\t\t\t HNS3_TQP_INTR_GL2_REG,\n-\t\t\t\t\t HNS3_TQP_INTR_RL_REG};\n+struct direct_reg_list {\n+\tconst char *name;\n+\tuint32_t addr;\n+};\n+\n+#define STR(s) #s\n+\n+static const struct direct_reg_list cmdq_reg_list[] = {\n+\t{STR(HNS3_CMDQ_TX_ADDR_L_REG),\t\tHNS3_CMDQ_TX_ADDR_L_REG},\n+\t{STR(HNS3_CMDQ_TX_ADDR_H_REG),\t\tHNS3_CMDQ_TX_ADDR_H_REG},\n+\t{STR(HNS3_CMDQ_TX_DEPTH_REG),\t\tHNS3_CMDQ_TX_DEPTH_REG},\n+\t{STR(HNS3_CMDQ_TX_TAIL_REG),\t\tHNS3_CMDQ_TX_TAIL_REG},\n+\t{STR(HNS3_CMDQ_TX_HEAD_REG),\t\tHNS3_CMDQ_TX_HEAD_REG},\n+\t{STR(HNS3_CMDQ_RX_ADDR_L_REG),\t\tHNS3_CMDQ_RX_ADDR_L_REG},\n+\t{STR(HNS3_CMDQ_RX_ADDR_H_REG),\t\tHNS3_CMDQ_RX_ADDR_H_REG},\n+\t{STR(HNS3_CMDQ_RX_DEPTH_REG),\t\tHNS3_CMDQ_RX_DEPTH_REG},\n+\t{STR(HNS3_CMDQ_RX_TAIL_REG),\t\tHNS3_CMDQ_RX_TAIL_REG},\n+\t{STR(HNS3_CMDQ_RX_HEAD_REG),\t\tHNS3_CMDQ_RX_HEAD_REG},\n+\t{STR(HNS3_VECTOR0_CMDQ_SRC_REG),\tHNS3_VECTOR0_CMDQ_SRC_REG},\n+\t{STR(HNS3_CMDQ_INTR_STS_REG),\t\tHNS3_CMDQ_INTR_STS_REG},\n+\t{STR(HNS3_CMDQ_INTR_EN_REG),\t\tHNS3_CMDQ_INTR_EN_REG},\n+\t{STR(HNS3_CMDQ_INTR_GEN_REG),\t\tHNS3_CMDQ_INTR_GEN_REG},\n+};\n+\n+static const struct direct_reg_list common_reg_list[] = {\n+\t{STR(HNS3_MISC_VECTOR_REG_BASE),\tHNS3_MISC_VECTOR_REG_BASE},\n+\t{STR(HNS3_VECTOR0_OTER_EN_REG),\t\tHNS3_VECTOR0_OTER_EN_REG},\n+\t{STR(HNS3_MISC_RESET_STS_REG),\t\tHNS3_MISC_RESET_STS_REG},\n+\t{STR(HNS3_VECTOR0_OTHER_INT_STS_REG),\tHNS3_VECTOR0_OTHER_INT_STS_REG},\n+\t{STR(HNS3_GLOBAL_RESET_REG),\t\tHNS3_GLOBAL_RESET_REG},\n+\t{STR(HNS3_FUN_RST_ING),\t\t\tHNS3_FUN_RST_ING},\n+\t{STR(HNS3_GRO_EN_REG),\t\t\tHNS3_GRO_EN_REG},\n+};\n+\n+static const struct direct_reg_list common_vf_reg_list[] = {\n+\t{STR(HNS3_MISC_VECTOR_REG_BASE),\tHNS3_MISC_VECTOR_REG_BASE},\n+\t{STR(HNS3_FUN_RST_ING),\t\t\tHNS3_FUN_RST_ING},\n+\t{STR(HNS3_GRO_EN_REG),\t\t\tHNS3_GRO_EN_REG},\n+};\n+\n+static const struct direct_reg_list ring_reg_list[] = {\n+\t{STR(HNS3_RING_RX_BASEADDR_L_REG),\tHNS3_RING_RX_BASEADDR_L_REG},\n+\t{STR(HNS3_RING_RX_BASEADDR_H_REG),\tHNS3_RING_RX_BASEADDR_H_REG},\n+\t{STR(HNS3_RING_RX_BD_NUM_REG),\t\tHNS3_RING_RX_BD_NUM_REG},\n+\t{STR(HNS3_RING_RX_BD_LEN_REG),\t\tHNS3_RING_RX_BD_LEN_REG},\n+\t{STR(HNS3_RING_RX_EN_REG),\t\tHNS3_RING_RX_EN_REG},\n+\t{STR(HNS3_RING_RX_MERGE_EN_REG),\tHNS3_RING_RX_MERGE_EN_REG},\n+\t{STR(HNS3_RING_RX_TAIL_REG),\t\tHNS3_RING_RX_TAIL_REG},\n+\t{STR(HNS3_RING_RX_HEAD_REG),\t\tHNS3_RING_RX_HEAD_REG},\n+\t{STR(HNS3_RING_RX_FBDNUM_REG),\t\tHNS3_RING_RX_FBDNUM_REG},\n+\t{STR(HNS3_RING_RX_OFFSET_REG),\t\tHNS3_RING_RX_OFFSET_REG},\n+\t{STR(HNS3_RING_RX_FBD_OFFSET_REG),\tHNS3_RING_RX_FBD_OFFSET_REG},\n+\t{STR(HNS3_RING_RX_STASH_REG),\t\tHNS3_RING_RX_STASH_REG},\n+\t{STR(HNS3_RING_RX_BD_ERR_REG),\t\tHNS3_RING_RX_BD_ERR_REG},\n+\t{STR(HNS3_RING_TX_BASEADDR_L_REG),\tHNS3_RING_TX_BASEADDR_L_REG},\n+\t{STR(HNS3_RING_TX_BASEADDR_H_REG),\tHNS3_RING_TX_BASEADDR_H_REG},\n+\t{STR(HNS3_RING_TX_BD_NUM_REG),\t\tHNS3_RING_TX_BD_NUM_REG},\n+\t{STR(HNS3_RING_TX_EN_REG),\t\tHNS3_RING_TX_EN_REG},\n+\t{STR(HNS3_RING_TX_PRIORITY_REG),\tHNS3_RING_TX_PRIORITY_REG},\n+\t{STR(HNS3_RING_TX_TC_REG),\t\tHNS3_RING_TX_TC_REG},\n+\t{STR(HNS3_RING_TX_MERGE_EN_REG),\tHNS3_RING_TX_MERGE_EN_REG},\n+\t{STR(HNS3_RING_TX_TAIL_REG),\t\tHNS3_RING_TX_TAIL_REG},\n+\t{STR(HNS3_RING_TX_HEAD_REG),\t\tHNS3_RING_TX_HEAD_REG},\n+\t{STR(HNS3_RING_TX_FBDNUM_REG),\t\tHNS3_RING_TX_FBDNUM_REG},\n+\t{STR(HNS3_RING_TX_OFFSET_REG),\t\tHNS3_RING_TX_OFFSET_REG},\n+\t{STR(HNS3_RING_TX_EBD_NUM_REG),\t\tHNS3_RING_TX_EBD_NUM_REG},\n+\t{STR(HNS3_RING_TX_EBD_OFFSET_REG),\tHNS3_RING_TX_EBD_OFFSET_REG},\n+\t{STR(HNS3_RING_TX_BD_ERR_REG),\t\tHNS3_RING_TX_BD_ERR_REG},\n+\t{STR(HNS3_RING_EN_REG),\t\t\tHNS3_RING_EN_REG},\n+};\n+\n+static const struct direct_reg_list tqp_intr_reg_list[] = {\n+\t{STR(HNS3_TQP_INTR_CTRL_REG),\tHNS3_TQP_INTR_CTRL_REG},\n+\t{STR(HNS3_TQP_INTR_GL0_REG),\tHNS3_TQP_INTR_GL0_REG},\n+\t{STR(HNS3_TQP_INTR_GL1_REG),\tHNS3_TQP_INTR_GL1_REG},\n+\t{STR(HNS3_TQP_INTR_GL2_REG),\tHNS3_TQP_INTR_GL2_REG},\n+\t{STR(HNS3_TQP_INTR_RL_REG),\tHNS3_TQP_INTR_RL_REG},\n+};\n \n static const uint32_t hns3_dfx_reg_opcode_list[] = {\n \tHNS3_OPC_DFX_BIOS_COMMON_REG,\n@@ -91,6 +108,708 @@ static const uint32_t hns3_dfx_reg_opcode_list[] = {\n \tHNS3_OPC_DFX_SSU_REG_2\n };\n \n+struct hns3_reg_entry {\n+\tconst char *new_name;\n+\tconst char *old_name;\n+};\n+\n+static struct hns3_reg_entry regs_32_bit_list[] = {\n+\t{\"ssu_common_err_int\"},\n+\t{\"ssu_port_based_err_int\"},\n+\t{\"ssu_fifo_overflow_int\"},\n+\t{\"ssu_ets_tcg_int\"},\n+\t{\"ssu_bp_status_0\"},\n+\t{\"ssu_bp_status_1\"},\n+\n+\t{\"ssu_bp_status_2\"},\n+\t{\"ssu_bp_status_3\"},\n+\t{\"ssu_bp_status_4\"},\n+\t{\"ssu_bp_status_5\"},\n+\t{\"ssu_mac_tx_pfc_ind\"},\n+\t{\"ssu_mac_rx_pfc_ind\"},\n+\n+\t{\"ssu_rx_oq_drop_pkt_cnt\"},\n+\t{\"ssu_tx_oq_drop_pkt_cnt\"},\n+};\n+\n+static struct hns3_reg_entry regs_64_bit_list[] = {\n+\t{\"ppp_get_rx_pkt_cnt_l\"},\n+\t{\"ppp_get_rx_pkt_cnt_h\"},\n+\t{\"ppp_get_tx_pkt_cnt_l\"},\n+\t{\"ppp_get_tx_pkt_cnt_h\"},\n+\t{\"ppp_send_uc_prt2host_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_prt2host_pkt_cnt_h\"},\n+\n+\t{\"ppp_send_uc_prt2prt_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_prt2prt_pkt_cnt_h\"},\n+\t{\"ppp_send_uc_host2host_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_host2host_pkt_cnt_h\"},\n+\t{\"ppp_send_uc_host2prt_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_host2prt_pkt_cnt_h\"},\n+\t{\"ppp_send_mc_from_prt_cnt_l\"},\n+\t{\"ppp_send_mc_from_prt_cnt_h\"},\n+};\n+\n+static struct hns3_reg_entry dfx_bios_common_reg_list[] = {\n+\t{\"bios_rsv0\"},\n+\t{\"bp_cpu_state\"},\n+\t{\"dfx_msix_info_nic_0\"},\n+\t{\"dfx_msix_info_nic_1\"},\n+\t{\"dfx_msix_info_nic_2\"},\n+\t{\"dfx_msix_info_nic_3\"},\n+\n+\t{\"dfx_msix_info_roce_0\"},\n+\t{\"dfx_msix_info_roce_1\"},\n+\t{\"dfx_msix_info_roce_2\"},\n+\t{\"dfx_msix_info_roce_3\"},\n+\t{\"bios_rsv1\"},\n+\t{\"bios_rsv2\"},\n+};\n+\n+static struct hns3_reg_entry dfx_ssu_reg_0_list[] = {\n+\t{\"dfx_ssu0_rsv0\"},\n+\t{\"ssu_ets_port_status\"},\n+\t{\"ssu_ets_tcg_status\"},\n+\t{\"dfx_ssu0_rsv1\"},\n+\t{\"dfx_ssu0_rsv2\"},\n+\t{\"ssu_bp_status_0\"},\n+\n+\t{\"ssu_bp_status_1\"},\n+\t{\"ssu_bp_status_2\"},\n+\t{\"ssu_bp_status_3\"},\n+\t{\"ssu_bp_status_4\"},\n+\t{\"ssu_bp_status_5\"},\n+\t{\"ssu_mac_tx_pfc_ind\"},\n+\n+\t{\"mac_ssu_rx_pfc_ind\"},\n+\t{\"ssu_btmp_ageing_st_b0\"},\n+\t{\"ssu_btmp_ageing_st_b1\"},\n+\t{\"ssu_btmp_ageing_st_b2\"},\n+\t{\"dfx_ssu0_rsv3\"},\n+\t{\"dfx_ssu0_rsv4\"},\n+\n+\t{\"ssu_full_drop_num\"},\n+\t{\"ssu_part_drop_num\"},\n+\t{\"ppp_key_drop_num\"},\n+\t{\"ppp_rlt_drop_num\"},\n+\t{\"ssu_lo_pri_unicast_rlt_drop_num\"},\n+\t{\"ssu_hi_pri_multicast_rlt_drop_num\"},\n+\n+\t{\"ssu_lo_pri_multicast_rlt_drop_num\"},\n+\t{\"ssu_ncsi_packet_curr_buffer_cnt\"},\n+\t{\"dfx_ssu0_rsv5\",\t\t\"ssu_btmp_ageing_rls_cnt_bank0\"},\n+\t{\"dfx_ssu0_rsv6\",\t\t\"ssu_btmp_ageing_rls_cnt_bank1\"},\n+\t{\"dfx_ssu0_rsv7\",\t\t\"ssu_btmp_ageing_rls_cnt_bank2\"},\n+\t{\"ssu_mb_rd_rlt_drop_cnt\"},\n+\n+\t{\"ssu_ppp_mac_key_num_l\"},\n+\t{\"ssu_ppp_mac_key_num_h\"},\n+\t{\"ssu_ppp_host_key_num_l\"},\n+\t{\"ssu_ppp_host_key_num_h\"},\n+\t{\"ppp_ssu_mac_rlt_num_l\"},\n+\t{\"ppp_ssu_mac_rlt_num_h\"},\n+\n+\t{\"ppp_ssu_host_rlt_num_l\"},\n+\t{\"ppp_ssu_host_rlt_num_h\"},\n+\t{\"ssu_ncsi_rx_packet_in_cnt_l\"},\n+\t{\"ssu_ncsi_rx_packet_in_cnt_h\"},\n+\t{\"ssu_ncsi_tx_packet_out_cnt_l\"},\n+\t{\"ssu_ncsi_tx_packet_out_cnt_h\"},\n+\n+\t{\"ssu_key_drop_num\"},\n+\t{\"ssu_mb_uncopy_num\"},\n+\t{\"ssu_rx_oq_drop_pkt_cnt\"},\n+\t{\"ssu_tx_oq_drop_pkt_cnt\"},\n+\t{\"ssu_bank_unbalance_drop_cnt\"},\n+\t{\"ssu_bank_unbalance_rx_drop_cnt\"},\n+\n+\t{\"ssu_nic_l2_eer_drop_pkt_cnt\"},\n+\t{\"ssu_roc_l2_eer_drop_pkt_cnt\"},\n+\t{\"ssu_nic_l2_eer_drop_pkt_cnt_rx\"},\n+\t{\"ssu_roc_l2_eer_drop_pkt_cnt_rx\"},\n+\t{\"ssu_rx_oq_glb_drop_pkt_cnt\"},\n+\t{\"ssu_dfx_ssu0_rsv8\"},\n+\n+\t{\"ssu_lo_pri_unicast_cur_cnt\"},\n+\t{\"ssu_hi_pri_multicast_cur_cnt\"},\n+\t{\"ssu_lo_pri_multicast_cur_cnt\"},\n+\t{\"dfx_ssu0_rsv9\"},\n+\t{\"dfx_ssu0_rsv10\"},\n+\t{\"dfx_ssu0_rsv11\"},\n+};\n+\n+static struct hns3_reg_entry dfx_ssu_reg_1_list[] = {\n+\t{\"dfx_ssu1_prt_id\"},\n+\t{\"ssu_packet_tc_curr_buffer_cnt_0\"},\n+\t{\"ssu_packet_tc_curr_buffer_cnt_1\"},\n+\t{\"ssu_packet_tc_curr_buffer_cnt_2\"},\n+\t{\"ssu_packet_tc_curr_buffer_cnt_3\"},\n+\t{\"ssu_packet_tc_curr_buffer_cnt_4\"},\n+\n+\t{\"ssu_packet_tc_curr_buffer_cnt_5\"},\n+\t{\"ssu_packet_tc_curr_buffer_cnt_6\"},\n+\t{\"ssu_packet_tc_curr_buffer_cnt_7\"},\n+\t{\"ssu_packet_curr_buffer_cnt\"},\n+\t{\"dfx_ssu1_rsv0\"},\n+\t{\"dfx_ssu1_rsv1\"},\n+\n+\t{\"ssu_rx_packet_in_cnt_l\"},\n+\t{\"ssu_rx_packet_in_cnt_h\"},\n+\t{\"ssu_rx_packet_out_cnt_l\"},\n+\t{\"ssu_rx_packet_out_cnt_h\"},\n+\t{\"ssu_tx_packet_in_cnt_l\"},\n+\t{\"ssu_tx_packet_in_cnt_h\"},\n+\n+\t{\"ssu_tx_packet_out_cnt_l\"},\n+\t{\"ssu_tx_packet_out_cnt_h\"},\n+\t{\"ssu_roc_rx_packet_in_cnt_l\"},\n+\t{\"ssu_roc_rx_packet_in_cnt_h\"},\n+\t{\"ssu_roc_tx_packet_in_cnt_l\"},\n+\t{\"ssu_roc_tx_packet_in_cnt_h\"},\n+\n+\t{\"ssu_rx_packet_tc_in_cnt_0_l\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_0_h\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_1_l\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_1_h\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_2_l\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_2_h\"},\n+\n+\t{\"ssu_rx_packet_tc_in_cnt_3_l\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_3_h\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_4_l\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_4_h\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_5_l\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_5_h\"},\n+\n+\t{\"ssu_rx_packet_tc_in_cnt_6_l\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_6_h\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_7_l\"},\n+\t{\"ssu_rx_packet_tc_in_cnt_7_h\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_0_l\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_0_h\"},\n+\n+\t{\"ssu_rx_packet_tc_out_cnt_1_l\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_1_h\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_2_l\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_2_h\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_3_l\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_3_h\"},\n+\n+\t{\"ssu_rx_packet_tc_out_cnt_4_l\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_4_h\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_5_l\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_5_h\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_6_l\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_6_h\"},\n+\n+\t{\"ssu_rx_packet_tc_out_cnt_7_l\"},\n+\t{\"ssu_rx_packet_tc_out_cnt_7_h\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_0_l\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_0_h\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_1_l\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_1_h\"},\n+\n+\t{\"ssu_tx_packet_tc_in_cnt_2_l\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_2_h\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_3_l\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_3_h\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_4_l\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_4_h\"},\n+\n+\t{\"ssu_tx_packet_tc_in_cnt_5_l\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_5_h\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_6_l\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_6_h\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_7_l\"},\n+\t{\"ssu_tx_packet_tc_in_cnt_7_h\"},\n+\n+\t{\"ssu_tx_packet_tc_out_cnt_0_l\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_0_h\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_1_l\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_1_h\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_2_l\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_2_h\"},\n+\n+\t{\"ssu_tx_packet_tc_out_cnt_3_l\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_3_h\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_4_l\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_4_h\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_5_l\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_5_h\"},\n+\n+\t{\"ssu_tx_packet_tc_out_cnt_6_l\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_6_h\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_7_l\"},\n+\t{\"ssu_tx_packet_tc_out_cnt_7_h\"},\n+\t{\"dfx_ssu1_rsv2\"},\n+\t{\"dfx_ssu1_rsv3\"},\n+};\n+\n+static struct hns3_reg_entry dfx_igu_egu_reg_list[] = {\n+\t{\"igu_egu_prt_id\"},\n+\t{\"igu_rx_err_pkt\"},\n+\t{\"igu_rx_no_sof_pkt\"},\n+\t{\"egu_tx_1588_short_pkt\"},\n+\t{\"egu_tx_1588_pkt\"},\n+\t{\"egu_tx_1588_err_pkt\"},\n+\n+\t{\"igu_rx_out_l2_pkt\"},\n+\t{\"igu_rx_out_l3_pkt\"},\n+\t{\"igu_rx_out_l4_pkt\"},\n+\t{\"igu_rx_in_l2_pkt\"},\n+\t{\"igu_rx_in_l3_pkt\"},\n+\t{\"igu_rx_in_l4_pkt\"},\n+\n+\t{\"igu_rx_el3e_pkt\"},\n+\t{\"igu_rx_el4e_pkt\"},\n+\t{\"igu_rx_l3e_pkt\"},\n+\t{\"igu_rx_l4e_pkt\"},\n+\t{\"igu_rx_rocee_pkt\"},\n+\t{\"igu_rx_out_udp0_pkt\"},\n+\n+\t{\"igu_rx_in_udp0_pkt\"},\n+\t{\"igu_egu_mul_car_drop_pkt_cnt_l\",\t\"igu_egu_rsv0\"},\n+\t{\"igu_egu_mul_car_drop_pkt_cnt_h\",\t\"igu_egu_rsv1\"},\n+\t{\"igu_egu_bro_car_drop_pkt_cnt_l\",\t\"igu_egu_rsv2\"},\n+\t{\"igu_egu_bro_car_drop_pkt_cnt_h\",\t\"igu_egu_rsv3\"},\n+\t{\"igu_egu_rsv0\",\t\t\"igu_egu_rsv4\"},\n+\n+\t{\"igu_rx_oversize_pkt_l\"},\n+\t{\"igu_rx_oversize_pkt_h\"},\n+\t{\"igu_rx_undersize_pkt_l\"},\n+\t{\"igu_rx_undersize_pkt_h\"},\n+\t{\"igu_rx_out_all_pkt_l\"},\n+\t{\"igu_rx_out_all_pkt_h\"},\n+\n+\t{\"igu_tx_out_all_pkt_l\"},\n+\t{\"igu_tx_out_all_pkt_h\"},\n+\t{\"igu_rx_uni_pkt_l\"},\n+\t{\"igu_rx_uni_pkt_h\"},\n+\t{\"igu_rx_multi_pkt_l\"},\n+\t{\"igu_rx_multi_pkt_h\"},\n+\n+\t{\"igu_rx_broad_pkt_l\"},\n+\t{\"igu_rx_broad_pkt_h\"},\n+\t{\"egu_tx_out_all_pkt_l\"},\n+\t{\"egu_tx_out_all_pkt_h\"},\n+\t{\"egu_tx_uni_pkt_l\"},\n+\t{\"egu_tx_uni_pkt_h\"},\n+\n+\t{\"egu_tx_multi_pkt_l\"},\n+\t{\"egu_tx_multi_pkt_h\"},\n+\t{\"egu_tx_broad_pkt_l\"},\n+\t{\"egu_tx_broad_pkt_h\"},\n+\t{\"igu_tx_key_num_l\"},\n+\t{\"igu_tx_key_num_h\"},\n+\n+\t{\"igu_rx_non_tun_pkt_l\"},\n+\t{\"igu_rx_non_tun_pkt_h\"},\n+\t{\"igu_rx_tun_pkt_l\"},\n+\t{\"igu_rx_tun_pkt_h\"},\n+\t{\"igu_egu_rsv5\"},\n+\t{\"igu_egu_rsv6\"},\n+};\n+\n+static struct hns3_reg_entry dfx_rpu_reg_0_list[] = {\n+\t{\"rpu_currport_tnl_index\",\t\"rpu_tc_queue_num\"},\n+\t{\"rpu_fsm_dfx_st0\"},\n+\t{\"rpu_fsm_dfx_st1\"},\n+\t{\"rpu_rpu_rx_pkt_drop_cnt\"},\n+\t{\"rpu_buf_wait_timeout\"},\n+\t{\"rpu_buf_wait_timeout_qid\"},\n+};\n+\n+static struct hns3_reg_entry dfx_rpu_reg_1_list[] = {\n+\t{\"rpu_rsv0\"},\n+\t{\"rpu_fifo_dfx_st0\"},\n+\t{\"rpu_fifo_dfx_st1\"},\n+\t{\"rpu_fifo_dfx_st2\"},\n+\t{\"rpu_fifo_dfx_st3\"},\n+\t{\"rpu_fifo_dfx_st4\"},\n+\n+\t{\"rpu_fifo_dfx_st5\"},\n+\t{\"rpu_rsv1\"},\n+\t{\"rpu_rsv2\"},\n+\t{\"rpu_rsv3\"},\n+\t{\"rpu_rsv4\"},\n+\t{\"rpu_rsv5\"},\n+};\n+\n+static struct hns3_reg_entry dfx_ncsi_reg_list[] = {\n+\t{\"ncsi_rsv0\"},\n+\t{\"ncsi_egu_tx_fifo_sts\"},\n+\t{\"ncsi_pause_status\"},\n+\t{\"ncsi_rx_ctrl_dmac_err_cnt\"},\n+\t{\"ncsi_rx_ctrl_smac_err_cnt\"},\n+\t{\"ncsi_rx_ctrl_cks_err_cnt\"},\n+\n+\t{\"ncsi_rx_ctrl_pkt_err_cnt\"},\n+\t{\"ncsi_rx_pt_dmac_err_cnt\"},\n+\t{\"ncsi_rx_pt_smac_err_cnt\"},\n+\t{\"ncsi_rx_pt_pkt_cnt\"},\n+\t{\"ncsi_rx_fcs_err_cnt\"},\n+\t{\"ncsi_tx_ctrl_dmac_err_cnt\"},\n+\n+\t{\"ncsi_tx_ctrl_smac_err_cnt\"},\n+\t{\"ncsi_tx_ctrl_pkt_cnt\"},\n+\t{\"ncsi_tx_pt_dmac_err_cnt\"},\n+\t{\"ncsi_tx_pt_smac_err_cnt\"},\n+\t{\"ncsi_tx_pt_pkt_cnt\"},\n+\t{\"ncsi_tx_pt_pkt_trun_cnt\"},\n+\n+\t{\"ncsi_tx_pt_pkt_err_cnt\"},\n+\t{\"ncsi_tx_ctrl_pkt_err_cnt\"},\n+\t{\"ncsi_rx_ctrl_pkt_trun_cnt\"},\n+\t{\"ncsi_rx_ctrl_pkt_cflit_cnt\"},\n+\t{\"ncsi_rsv1\"},\n+\t{\"ncsi_rsv2\"},\n+\n+\t{\"ncsi_mac_rx_octets_ok\"},\n+\t{\"ncsi_mac_rx_octets_bad\"},\n+\t{\"ncsi_mac_rx_uc_pkts\"},\n+\t{\"ncsi_mac_rx_mc_pkts\"},\n+\t{\"ncsi_mac_rx_bc_pkts\"},\n+\t{\"ncsi_mac_rx_pkts_64octets\"},\n+\n+\t{\"ncsi_mac_rx_pkts_64to127_octets\"},\n+\t{\"ncsi_mac_rx_pkts_128to255_octets\"},\n+\t{\"ncsi_mac_rx_pkts_256to511_octets\"},\n+\t{\"ncsi_mac_rx_pkts_512to1023_octets\"},\n+\t{\"ncsi_mac_rx_pkts_1024to1518_octets\"},\n+\t{\"ncsi_mac_rx_pkts_1519tomax_octets\"},\n+\n+\t{\"ncsi_mac_rx_fcs_errors\"},\n+\t{\"ncsi_mac_rx_long_errors\"},\n+\t{\"ncsi_mac_rx_jabber_errors\"},\n+\t{\"ncsi_mac_rx_runt_err_cnt\"},\n+\t{\"ncsi_mac_rx_short_err_cnt\"},\n+\t{\"ncsi_mac_rx_filt_pkt_cnt\"},\n+\n+\t{\"ncsi_mac_rx_octets_total_filt\"},\n+\t{\"ncsi_mac_tx_octets_ok\"},\n+\t{\"ncsi_mac_tx_octets_bad\"},\n+\t{\"ncsi_mac_tx_uc_pkts\"},\n+\t{\"ncsi_mac_tx_mc_pkts\"},\n+\t{\"ncsi_mac_tx_bc_pkts\"},\n+\n+\t{\"ncsi_mac_tx_pkts_64octets\"},\n+\t{\"ncsi_mac_tx_pkts_64to127_octets\"},\n+\t{\"ncsi_mac_tx_pkts_128to255_octets\"},\n+\t{\"ncsi_mac_tx_pkts_256to511_octets\"},\n+\t{\"ncsi_mac_tx_pkts_512to1023_octets\"},\n+\t{\"ncsi_mac_tx_pkts_1024to1518_octets\"},\n+\n+\t{\"ncsi_mac_tx_pkts_1519tomax_octets\"},\n+\t{\"ncsi_mac_tx_underrun\"},\n+\t{\"ncsi_mac_tx_crc_error\"},\n+\t{\"ncsi_mac_tx_pause_frames\"},\n+\t{\"ncsi_mac_rx_pad_pkts\"},\n+\t{\"ncsi_mac_rx_pause_frames\"},\n+};\n+\n+static struct hns3_reg_entry dfx_rtc_reg_list[] = {\n+\t{\"rtc_rsv0\"},\n+\t{\"lge_igu_afifo_dfx_0\"},\n+\t{\"lge_igu_afifo_dfx_1\"},\n+\t{\"lge_igu_afifo_dfx_2\"},\n+\t{\"lge_igu_afifo_dfx_3\"},\n+\t{\"lge_igu_afifo_dfx_4\"},\n+\n+\t{\"lge_igu_afifo_dfx_5\"},\n+\t{\"lge_igu_afifo_dfx_6\"},\n+\t{\"lge_igu_afifo_dfx_7\"},\n+\t{\"lge_egu_afifo_dfx_0\"},\n+\t{\"lge_egu_afifo_dfx_1\"},\n+\t{\"lge_egu_afifo_dfx_2\"},\n+\n+\t{\"lge_egu_afifo_dfx_3\"},\n+\t{\"lge_egu_afifo_dfx_4\"},\n+\t{\"lge_egu_afifo_dfx_5\"},\n+\t{\"lge_egu_afifo_dfx_6\"},\n+\t{\"lge_egu_afifo_dfx_7\"},\n+\t{\"cge_igu_afifo_dfx_0\"},\n+\n+\t{\"cge_igu_afifo_dfx_1\"},\n+\t{\"cge_egu_afifo_dfx_0\"},\n+\t{\"cge_egu_afifo_dfx_i\"},\n+\t{\"rtc_rsv1\"},\n+\t{\"rtc_rsv2\"},\n+\t{\"rtc_rsv3\"},\n+};\n+\n+static struct hns3_reg_entry dfx_ppp_reg_list[] = {\n+\t{\"ppp_rsv0\"},\n+\t{\"ppp_drop_from_prt_pkt_cnt\"},\n+\t{\"ppp_drop_from_host_pkt_cnt\"},\n+\t{\"ppp_drop_tx_vlan_proc_cnt\"},\n+\t{\"ppp_drop_mng_cnt\"},\n+\t{\"ppp_drop_fd_cnt\"},\n+\n+\t{\"ppp_drop_no_dst_cnt\"},\n+\t{\"ppp_drop_mc_mbid_full_cnt\"},\n+\t{\"ppp_drop_sc_filtered\"},\n+\t{\"ppp_ppp_mc_drop_pkt_cnt\"},\n+\t{\"ppp_drop_pt_cnt\"},\n+\t{\"ppp_drop_mac_anti_spoof_cnt\"},\n+\n+\t{\"ppp_drop_ig_vfv_cnt\"},\n+\t{\"ppp_drop_ig_prtv_cnt\"},\n+\t{\"ppp_drop_cnm_pfc_pause_cnt\"},\n+\t{\"ppp_drop_torus_tc_cnt\"},\n+\t{\"ppp_drop_torus_lpbk_cnt\"},\n+\t{\"ppp_ppp_hfs_sts\"},\n+\n+\t{\"ppp_mc_rslt_sts\"},\n+\t{\"ppp_p3u_sts\"},\n+\t{\"ppp_rsv1\",\t\t\"ppp_rslt_descr_sts\"},\n+\t{\"ppp_umv_sts_0\"},\n+\t{\"ppp_umv_sts_1\"},\n+\t{\"ppp_vfv_sts\"},\n+\n+\t{\"ppp_gro_key_cnt\"},\n+\t{\"ppp_gro_info_cnt\"},\n+\t{\"ppp_gro_drop_cnt\"},\n+\t{\"ppp_gro_out_cnt\"},\n+\t{\"ppp_gro_key_match_data_cnt\"},\n+\t{\"ppp_gro_key_match_tcam_cnt\"},\n+\n+\t{\"ppp_gro_info_match_cnt\"},\n+\t{\"ppp_gro_free_entry_cnt\"},\n+\t{\"ppp_gro_inner_dfx_signal\"},\n+\t{\"ppp_rsv2\"},\n+\t{\"ppp_rsv3\"},\n+\t{\"ppp_rsv4\"},\n+\n+\t{\"ppp_get_rx_pkt_cnt_l\"},\n+\t{\"ppp_get_rx_pkt_cnt_h\"},\n+\t{\"ppp_get_tx_pkt_cnt_l\"},\n+\t{\"ppp_get_tx_pkt_cnt_h\"},\n+\t{\"ppp_send_uc_prt2host_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_prt2host_pkt_cnt_h\"},\n+\n+\t{\"ppp_send_uc_prt2prt_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_prt2prt_pkt_cnt_h\"},\n+\t{\"ppp_send_uc_host2host_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_host2host_pkt_cnt_h\"},\n+\t{\"ppp_send_uc_host2prt_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_host2prt_pkt_cnt_h\"},\n+\n+\t{\"ppp_send_mc_from_prt_cnt_l\"},\n+\t{\"ppp_send_mc_from_prt_cnt_h\"},\n+\t{\"ppp_send_mc_from_host_cnt_l\"},\n+\t{\"ppp_send_mc_from_host_cnt_h\"},\n+\t{\"ppp_ssu_mc_rd_cnt_l\"},\n+\t{\"ppp_ssu_mc_rd_cnt_h\"},\n+\n+\t{\"ppp_ssu_mc_drop_cnt_l\"},\n+\t{\"ppp_ssu_mc_drop_cnt_h\"},\n+\t{\"ppp_ssu_mc_rd_pkt_cnt_l\"},\n+\t{\"ppp_ssu_mc_rd_pkt_cnt_h\"},\n+\t{\"ppp_mc_2host_pkt_cnt_l\"},\n+\t{\"ppp_mc_2host_pkt_cnt_h\"},\n+\n+\t{\"ppp_mc_2prt_pkt_cnt_l\"},\n+\t{\"ppp_mc_2prt_pkt_cnt_h\"},\n+\t{\"ppp_ntsnos_pkt_cnt_l\"},\n+\t{\"ppp_ntsnos_pkt_cnt_h\"},\n+\t{\"ppp_ntup_pkt_cnt_l\"},\n+\t{\"ppp_ntup_pkt_cnt_h\"},\n+\n+\t{\"ppp_ntlcl_pkt_cnt_l\"},\n+\t{\"ppp_ntlcl_pkt_cnt_h\"},\n+\t{\"ppp_nttgt_pkt_cnt_l\"},\n+\t{\"ppp_nttgt_pkt_cnt_h\"},\n+\t{\"ppp_rtns_pkt_cnt_l\"},\n+\t{\"ppp_rtns_pkt_cnt_h\"},\n+\n+\t{\"ppp_rtlpbk_pkt_cnt_l\"},\n+\t{\"ppp_rtlpbk_pkt_cnt_h\"},\n+\t{\"ppp_nr_pkt_cnt_l\"},\n+\t{\"ppp_nr_pkt_cnt_h\"},\n+\t{\"ppp_rr_pkt_cnt_l\"},\n+\t{\"ppp_rr_pkt_cnt_h\"},\n+\n+\t{\"ppp_mng_tbl_hit_cnt_l\"},\n+\t{\"ppp_mng_tbl_hit_cnt_h\"},\n+\t{\"ppp_fd_tbl_hit_cnt_l\"},\n+\t{\"ppp_fd_tbl_hit_cnt_h\"},\n+\t{\"ppp_fd_lkup_cnt_l\"},\n+\t{\"ppp_fd_lkup_cnt_h\"},\n+\n+\t{\"ppp_bc_hit_cnt\"},\n+\t{\"ppp_bc_hit_cnt_h\"},\n+\t{\"ppp_um_tbl_uc_hit_cnt\"},\n+\t{\"ppp_um_tbl_uc_hit_cnt_h\"},\n+\t{\"ppp_um_tbl_mc_hit_cnt\"},\n+\t{\"ppp_um_tbl_mc_hit_cnt_h\"},\n+\n+\t{\"ppp_um_tbl_snq_hit_cnt_l\",\t\"ppp_um_tbl_vmdq1_hit_cnt_l\"},\n+\t{\"ppp_um_tbl_snq_hit_cnt_h\",\t\"ppp_um_tbl_vmdq1_hit_cnt_h\"},\n+\t{\"ppp_rsv5\",\t\t\t\"ppp_mta_tbl_hit_cnt_l\"},\n+\t{\"ppp_rsv6\",\t\t\t\"ppp_mta_tbl_hit_cnt_h\"},\n+\t{\"ppp_fwd_bonding_hit_cnt_l\"},\n+\t{\"ppp_fwd_bonding_hit_cnt_h\"},\n+\n+\t{\"ppp_promisc_tbl_hit_cnt_l\"},\n+\t{\"ppp_promisc_tbl_hit_cnt_h\"},\n+\t{\"ppp_get_tunl_pkt_cnt_l\"},\n+\t{\"ppp_get_tunl_pkt_cnt_h\"},\n+\t{\"ppp_get_bmc_pkt_cnt_l\"},\n+\t{\"ppp_get_bmc_pkt_cnt_h\"},\n+\n+\t{\"ppp_send_uc_prt2bmc_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_prt2bmc_pkt_cnt_h\"},\n+\t{\"ppp_send_uc_host2bmc_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_host2bmc_pkt_cnt_h\"},\n+\t{\"ppp_send_uc_bmc2host_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_bmc2host_pkt_cnt_h\"},\n+\n+\t{\"ppp_send_uc_bmc2prt_pkt_cnt_l\"},\n+\t{\"ppp_send_uc_bmc2prt_pkt_cnt_h\"},\n+\t{\"ppp_mc_2bmc_pkt_cnt_l\"},\n+\t{\"ppp_mc_2bmc_pkt_cnt_h\"},\n+\t{\"ppp_rsv7\",\t\"ppp_vlan_mirr_cnt_l\"},\n+\t{\"ppp_rsv8\",\t\"ppp_vlan_mirr_cnt_h\"},\n+\n+\t{\"ppp_rsv9\",\t\"ppp_ig_mirr_cnt_l\"},\n+\t{\"ppp_rsv10\",\t\"ppp_ig_mirr_cnt_h\"},\n+\t{\"ppp_rsv11\",\t\"ppp_eg_mirr_cnt_l\"},\n+\t{\"ppp_rsv12\",\t\"ppp_eg_mirr_cnt_h\"},\n+\t{\"ppp_rx_default_host_hit_cnt_l\"},\n+\t{\"ppp_rx_default_host_hit_cnt_h\"},\n+\n+\t{\"ppp_lan_pair_cnt_l\"},\n+\t{\"ppp_lan_pair_cnt_h\"},\n+\t{\"ppp_um_tbl_mc_hit_pkt_cnt_l\"},\n+\t{\"ppp_um_tbl_mc_hit_pkt_cnt_h\"},\n+\t{\"ppp_mta_tbl_hit_pkt_cnt_l\"},\n+\t{\"ppp_mta_tbl_hit_pkt_cnt_h\"},\n+\n+\t{\"ppp_promisc_tbl_hit_pkt_cnt_l\"},\n+\t{\"ppp_promisc_tbl_hit_pkt_cnt_h\"},\n+\t{\"ppp_rsv13\"},\n+\t{\"ppp_rsv14\"},\n+\t{\"ppp_rsv15\"},\n+\t{\"ppp_rsv16\"},\n+};\n+\n+static struct hns3_reg_entry dfx_rcb_reg_list[] = {\n+\t{\"rcb_rsv0\"},\n+\t{\"rcb_fsm_dfx_st0\"},\n+\t{\"rcb_fsm_dfx_st1\"},\n+\t{\"rcb_fsm_dfx_st2\"},\n+\t{\"rcb_fifo_dfx_st0\"},\n+\t{\"rcb_fifo_dfx_st1\"},\n+\n+\t{\"rcb_fifo_dfx_st2\"},\n+\t{\"rcb_fifo_dfx_st3\"},\n+\t{\"rcb_fifo_dfx_st4\"},\n+\t{\"rcb_fifo_dfx_st5\"},\n+\t{\"rcb_fifo_dfx_st6\"},\n+\t{\"rcb_fifo_dfx_st7\"},\n+\n+\t{\"rcb_fifo_dfx_st8\"},\n+\t{\"rcb_fifo_dfx_st9\"},\n+\t{\"rcb_fifo_dfx_st10\"},\n+\t{\"rcb_fifo_dfx_st11\"},\n+\t{\"rcb_q_credit_vld_0\"},\n+\t{\"rcb_q_credit_vld_1\"},\n+\n+\t{\"rcb_q_credit_vld_2\"},\n+\t{\"rcb_q_credit_vld_3\"},\n+\t{\"rcb_q_credit_vld_4\"},\n+\t{\"rcb_q_credit_vld_5\"},\n+\t{\"rcb_q_credit_vld_6\"},\n+\t{\"rcb_q_credit_vld_7\"},\n+\n+\t{\"rcb_q_credit_vld_8\"},\n+\t{\"rcb_q_credit_vld_9\"},\n+\t{\"rcb_q_credit_vld_10\"},\n+\t{\"rcb_q_credit_vld_11\"},\n+\t{\"rcb_q_credit_vld_12\"},\n+\t{\"rcb_q_credit_vld_13\"},\n+\n+\t{\"rcb_q_credit_vld_14\"},\n+\t{\"rcb_q_credit_vld_15\"},\n+\t{\"rcb_q_credit_vld_16\"},\n+\t{\"rcb_q_credit_vld_17\"},\n+\t{\"rcb_q_credit_vld_18\"},\n+\t{\"rcb_q_credit_vld_19\"},\n+\n+\t{\"rcb_q_credit_vld_20\"},\n+\t{\"rcb_q_credit_vld_21\"},\n+\t{\"rcb_q_credit_vld_22\"},\n+\t{\"rcb_q_credit_vld_23\"},\n+\t{\"rcb_q_credit_vld_24\"},\n+\t{\"rcb_q_credit_vld_25\"},\n+\n+\t{\"rcb_q_credit_vld_26\"},\n+\t{\"rcb_q_credit_vld_27\"},\n+\t{\"rcb_q_credit_vld_28\"},\n+\t{\"rcb_q_credit_vld_29\"},\n+\t{\"rcb_q_credit_vld_30\"},\n+\t{\"rcb_q_credit_vld_31\"},\n+\n+\t{\"rcb_gro_bd_serr_cnt\"},\n+\t{\"rcb_gro_context_serr_cnt\"},\n+\t{\"rcb_rx_stash_cfg_serr_cnt\"},\n+\t{\"rcb_rcb_tx_mem_serr_cnt\",\t\"rcb_axi_rd_fbd_serr_cnt\"},\n+\t{\"rcb_gro_bd_merr_cnt\"},\n+\t{\"rcb_gro_context_merr_cnt\"},\n+\n+\t{\"rcb_rx_stash_cfg_merr_cnt\"},\n+\t{\"rcb_axi_rd_fbd_merr_cnt\"},\n+\t{\"rcb_rsv1\"},\n+\t{\"rcb_rsv2\"},\n+\t{\"rcb_rsv3\"},\n+\t{\"rcb_rsv4\"},\n+};\n+\n+static struct hns3_reg_entry dfx_tqp_reg_list[] = {\n+\t{\"dfx_tqp_q_num\"},\n+\t{\"rcb_cfg_rx_ring_tail\"},\n+\t{\"rcb_cfg_rx_ring_head\"},\n+\t{\"rcb_cfg_rx_ring_fbdnum\"},\n+\t{\"rcb_cfg_rx_ring_offset\"},\n+\t{\"rcb_cfg_rx_ring_fbdoffset\"},\n+\n+\t{\"rcb_cfg_rx_ring_pktnum_record\"},\n+\t{\"rcb_cfg_tx_ring_tail\"},\n+\t{\"rcb_cfg_tx_ring_head\"},\n+\t{\"rcb_cfg_tx_ring_fbdnum\"},\n+\t{\"rcb_cfg_tx_ring_offset\"},\n+\t{\"rcb_cfg_tx_ring_ebdnum\"},\n+};\n+\n+static struct hns3_reg_entry dfx_ssu_reg_2_list[] = {\n+\t{\"dfx_ssu2_oq_index\"},\n+\t{\"dfx_ssu2_queue_cnt\"},\n+\t{\"dfx_ssu2_rsv0\"},\n+\t{\"dfx_ssu2_rsv1\"},\n+\t{\"dfx_ssu2_rsv2\"},\n+\t{\"dfx_ssu2_rsv3\"},\n+};\n+\n+struct hns3_dfx_reg_entry {\n+\tconst struct hns3_reg_entry *regs;\n+\tuint32_t entry_num;\n+};\n+\n+struct hns3_dfx_reg_entry hns3_dfx_reg_list[] = {\n+\t{dfx_bios_common_reg_list,\tRTE_DIM(dfx_bios_common_reg_list)},\n+\t{dfx_ssu_reg_0_list,\t\tRTE_DIM(dfx_ssu_reg_0_list)},\n+\t{dfx_ssu_reg_1_list,\t\tRTE_DIM(dfx_ssu_reg_1_list)},\n+\t{dfx_igu_egu_reg_list,\t\tRTE_DIM(dfx_igu_egu_reg_list)},\n+\t{dfx_rpu_reg_0_list,\t\tRTE_DIM(dfx_rpu_reg_0_list)},\n+\t{dfx_rpu_reg_1_list,\t\tRTE_DIM(dfx_rpu_reg_1_list)},\n+\t{dfx_ncsi_reg_list,\t\tRTE_DIM(dfx_ncsi_reg_list)},\n+\t{dfx_rtc_reg_list,\t\tRTE_DIM(dfx_rtc_reg_list)},\n+\t{dfx_ppp_reg_list,\t\tRTE_DIM(dfx_ppp_reg_list)},\n+\t{dfx_rcb_reg_list,\t\tRTE_DIM(dfx_rcb_reg_list)},\n+\t{dfx_tqp_reg_list,\t\tRTE_DIM(dfx_tqp_reg_list)},\n+\t{dfx_ssu_reg_2_list,\t\tRTE_DIM(dfx_ssu_reg_2_list)},\n+};\n+\n static int\n hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,\n \t\t uint32_t *regs_num_64_bit)\n@@ -108,6 +827,12 @@ hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,\n \n \t*regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);\n \t*regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);\n+\tif (*regs_num_32_bit != RTE_DIM(regs_32_bit_list) ||\n+\t *regs_num_64_bit * HNS3_64_BIT_REG_SIZE !=\n+\t\t\tRTE_DIM(regs_64_bit_list)) {\n+\t\thns3_err(hw, \"Query register number differ from the list!\");\n+\t\treturn -EINVAL;\n+\t}\n \n \treturn 0;\n }\n@@ -122,13 +847,13 @@ hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)\n \tuint32_t len;\n \tint ret;\n \n-\tcmdq_cnt = sizeof(cmdq_reg_addrs);\n+\tcmdq_cnt = RTE_DIM(cmdq_reg_list);\n \tif (hns->is_vf)\n-\t\tcommon_cnt = sizeof(common_vf_reg_addrs);\n+\t\tcommon_cnt = sizeof(common_vf_reg_list);\n \telse\n-\t\tcommon_cnt = sizeof(common_reg_addrs);\n-\tring_cnt = sizeof(ring_reg_addrs);\n-\ttqp_intr_cnt = sizeof(tqp_intr_reg_addrs);\n+\t\tcommon_cnt = RTE_DIM(common_reg_list);\n+\tring_cnt = RTE_DIM(ring_reg_list);\n+\ttqp_intr_cnt = RTE_DIM(tqp_intr_reg_list);\n \n \tlen = cmdq_cnt + common_cnt + ring_cnt * hw->tqps_num +\n \t tqp_intr_cnt * hw->intr_tqps_num;\n@@ -281,33 +1006,33 @@ hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)\n \tsize_t i;\n \n \t/* fetching per-PF registers values from PF PCIe register space */\n-\treg_num = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);\n+\treg_num = RTE_DIM(cmdq_reg_list);\n \tfor (i = 0; i < reg_num; i++)\n-\t\t*data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);\n+\t\t*data++ = hns3_read_dev(hw, cmdq_reg_list[i].addr);\n \n \tif (hns->is_vf)\n-\t\treg_num = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);\n+\t\treg_num = RTE_DIM(common_vf_reg_list);\n \telse\n-\t\treg_num = sizeof(common_reg_addrs) / sizeof(uint32_t);\n+\t\treg_num = RTE_DIM(common_reg_list);\n \tfor (i = 0; i < reg_num; i++)\n \t\tif (hns->is_vf)\n-\t\t\t*data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);\n+\t\t\t*data++ = hns3_read_dev(hw, common_vf_reg_list[i].addr);\n \t\telse\n-\t\t\t*data++ = hns3_read_dev(hw, common_reg_addrs[i]);\n+\t\t\t*data++ = hns3_read_dev(hw, common_reg_list[i].addr);\n \n-\treg_num = sizeof(ring_reg_addrs) / sizeof(uint32_t);\n+\treg_num = RTE_DIM(ring_reg_list);\n \tfor (j = 0; j < hw->tqps_num; j++) {\n \t\treg_offset = hns3_get_tqp_reg_offset(j);\n \t\tfor (i = 0; i < reg_num; i++)\n \t\t\t*data++ = hns3_read_dev(hw,\n-\t\t\t\t\t\tring_reg_addrs[i] + reg_offset);\n+\t\t\t\t\t\tring_reg_list[i].addr + reg_offset);\n \t}\n \n-\treg_num = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);\n+\treg_num = RTE_DIM(tqp_intr_reg_list);\n \tfor (j = 0; j < hw->intr_tqps_num; j++) {\n \t\treg_offset = hns3_get_tqp_intr_reg_offset(j);\n \t\tfor (i = 0; i < reg_num; i++)\n-\t\t\t*data++ = hns3_read_dev(hw, tqp_intr_reg_addrs[i] +\n+\t\t\t*data++ = hns3_read_dev(hw, tqp_intr_reg_list[i].addr +\n \t\t\t\t\t\treg_offset);\n \t}\n \treturn data - origin_data_ptr;\n", "prefixes": [ "v4", "5/7" ] }