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GET /api/patches/137111/?format=api
{ "id": 137111, "url": "http://patches.dpdk.org/api/patches/137111/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1708715054-22386-2-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1708715054-22386-2-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1708715054-22386-2-git-send-email-roretzla@linux.microsoft.com", "date": "2024-02-23T19:03:36", "name": "[v5,01/39] eal: use C11 alignas", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4e66e3b709d067b5a5b3407554ea3a09ffccd23f", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1708715054-22386-2-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31207, "url": "http://patches.dpdk.org/api/series/31207/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31207", "date": "2024-02-23T19:03:37", "name": "use C11 alignas", "version": 5, "mbox": "http://patches.dpdk.org/series/31207/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137111/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137111/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B1BBD43BA4;\n\tFri, 23 Feb 2024 20:04:25 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 37A604029C;\n\tFri, 23 Feb 2024 20:04:19 +0100 (CET)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id 1F1514027A\n for <dev@dpdk.org>; Fri, 23 Feb 2024 20:04:17 +0100 (CET)", "by linux.microsoft.com (Postfix, from userid 1086)\n id 1CF4120B74C1; Fri, 23 Feb 2024 11:04:16 -0800 (PST)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 1CF4120B74C1", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1708715056;\n bh=hjPUzGNMYhaHfJN4WfFITYnLQhcTLv0FFOQvnR7sxz4=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=C9imAbQkbgIx7lgDrK8pCNLZNyxciT2y4T7q5cLQ1KGL7PO4B85TR+YhM7SnY/3Jh\n 6JU2lHydetM6HYJ7XH6cVyn+HJl1HKloOi31+iLugBKWlnEWNo6TzVOmt290sdPCG0\n zxZFo2A2ehFsPuKSqqmxt3pMPQyc3r3jiaAax34A=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Chengwen Feng <fengchengwen@huawei.com>,\n Cristian Dumitrescu <cristian.dumitrescu@intel.com>,\n David Christensen <drc@linux.vnet.ibm.com>,\n David Hunt <david.hunt@intel.com>, Ferruh Yigit <ferruh.yigit@amd.com>,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,\n Jasvinder Singh <jasvinder.singh@intel.com>,\n Jerin Jacob <jerinj@marvell.com>, Kevin Laatz <kevin.laatz@intel.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Min Zhou <zhoumin@loongson.cn>, Ruifeng Wang <ruifeng.wang@arm.com>,\n Sameh Gobriel <sameh.gobriel@intel.com>,\n Stanislaw Kardach <kda@semihalf.com>,\n Thomas Monjalon <thomas@monjalon.net>,\n Vladimir Medvedkin <vladimir.medvedkin@intel.com>,\n Yipeng Wang <yipeng1.wang@intel.com>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v5 01/39] eal: use C11 alignas", "Date": "Fri, 23 Feb 2024 11:03:36 -0800", "Message-Id": "<1708715054-22386-2-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1708715054-22386-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1707873986-29352-1-git-send-email-roretzla@linux.microsoft.com>\n <1708715054-22386-1-git-send-email-roretzla@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The current location used for __rte_aligned(a) for alignment of types\nand variables is not compatible with MSVC. There is only a single\nlocation accepted by both toolchains.\n\nFor variables standard C11 offers alignas(a) supported by conformant\ncompilers i.e. both MSVC and GCC.\n\nFor types the standard offers no alignment facility that compatibly\ninteroperates with C and C++ but may be achieved by relocating the\nplacement of __rte_aligned(a) to the aforementioned location accepted\nby all currently supported toolchains.\n\nTo allow alignment for both compilers do the following:\n\n* Expand __rte_aligned(a) to __declspec(align(a)) when building\n with MSVC.\n\n* Move __rte_aligned from the end of {struct,union} definitions to\n be between {struct,union} and tag.\n\n The placement between {struct,union} and the tag allows the desired\n alignment to be imparted on the type regardless of the toolchain being\n used for all of GCC, LLVM, MSVC compilers building both C and C++.\n\n* Replace use of __rte_aligned(a) on variables/fields with alignas(a).\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\n---\n lib/eal/arm/include/rte_vect.h | 4 ++--\n lib/eal/common/malloc_elem.h | 4 ++--\n lib/eal/common/malloc_heap.h | 4 ++--\n lib/eal/common/rte_keepalive.c | 3 ++-\n lib/eal/common/rte_random.c | 4 ++--\n lib/eal/common/rte_service.c | 8 ++++----\n lib/eal/include/generic/rte_atomic.h | 4 ++--\n lib/eal/include/rte_common.h | 23 +++++++++++++++--------\n lib/eal/loongarch/include/rte_vect.h | 8 ++++----\n lib/eal/ppc/include/rte_vect.h | 4 ++--\n lib/eal/riscv/include/rte_vect.h | 4 ++--\n lib/eal/x86/include/rte_vect.h | 4 ++--\n lib/eal/x86/rte_power_intrinsics.c | 10 ++++++----\n 13 files changed, 47 insertions(+), 37 deletions(-)", "diff": "diff --git a/lib/eal/arm/include/rte_vect.h b/lib/eal/arm/include/rte_vect.h\nindex 8cfe4bd..c97d299 100644\n--- a/lib/eal/arm/include/rte_vect.h\n+++ b/lib/eal/arm/include/rte_vect.h\n@@ -24,14 +24,14 @@\n #define\tXMM_SIZE\t(sizeof(xmm_t))\n #define\tXMM_MASK\t(XMM_SIZE - 1)\n \n-typedef union rte_xmm {\n+typedef union __rte_aligned(16) rte_xmm {\n \txmm_t x;\n \tuint8_t u8[XMM_SIZE / sizeof(uint8_t)];\n \tuint16_t u16[XMM_SIZE / sizeof(uint16_t)];\n \tuint32_t u32[XMM_SIZE / sizeof(uint32_t)];\n \tuint64_t u64[XMM_SIZE / sizeof(uint64_t)];\n \tdouble pd[XMM_SIZE / sizeof(double)];\n-} __rte_aligned(16) rte_xmm_t;\n+} rte_xmm_t;\n \n #if defined(RTE_ARCH_ARM) && defined(RTE_ARCH_32)\n /* NEON intrinsic vqtbl1q_u8() is not supported in ARMv7-A(AArch32) */\ndiff --git a/lib/eal/common/malloc_elem.h b/lib/eal/common/malloc_elem.h\nindex 952ce73..c7ff671 100644\n--- a/lib/eal/common/malloc_elem.h\n+++ b/lib/eal/common/malloc_elem.h\n@@ -20,7 +20,7 @@ enum elem_state {\n \tELEM_PAD /* element is a padding-only header */\n };\n \n-struct malloc_elem {\n+struct __rte_cache_aligned malloc_elem {\n \tstruct malloc_heap *heap;\n \tstruct malloc_elem *volatile prev;\n \t/**< points to prev elem in memseg */\n@@ -48,7 +48,7 @@ struct malloc_elem {\n \tsize_t user_size;\n \tuint64_t asan_cookie[2]; /* must be next to header_cookie */\n #endif\n-} __rte_cache_aligned;\n+};\n \n static const unsigned int MALLOC_ELEM_HEADER_LEN = sizeof(struct malloc_elem);\n \ndiff --git a/lib/eal/common/malloc_heap.h b/lib/eal/common/malloc_heap.h\nindex 8f3ab57..0c49588 100644\n--- a/lib/eal/common/malloc_heap.h\n+++ b/lib/eal/common/malloc_heap.h\n@@ -21,7 +21,7 @@\n /**\n * Structure to hold malloc heap\n */\n-struct malloc_heap {\n+struct __rte_cache_aligned malloc_heap {\n \trte_spinlock_t lock;\n \tLIST_HEAD(, malloc_elem) free_head[RTE_HEAP_NUM_FREELISTS];\n \tstruct malloc_elem *volatile first;\n@@ -31,7 +31,7 @@ struct malloc_heap {\n \tunsigned int socket_id;\n \tsize_t total_size;\n \tchar name[RTE_HEAP_NAME_MAX_LEN];\n-} __rte_cache_aligned;\n+};\n \n void *\n malloc_heap_alloc(const char *type, size_t size, int socket, unsigned int flags,\ndiff --git a/lib/eal/common/rte_keepalive.c b/lib/eal/common/rte_keepalive.c\nindex f6db973..391c1be 100644\n--- a/lib/eal/common/rte_keepalive.c\n+++ b/lib/eal/common/rte_keepalive.c\n@@ -2,6 +2,7 @@\n * Copyright(c) 2015-2016 Intel Corporation\n */\n \n+#include <stdalign.h>\n #include <inttypes.h>\n \n #include <rte_common.h>\n@@ -19,7 +20,7 @@ struct rte_keepalive {\n \t\t/*\n \t\t * Each element must be cache aligned to prevent false sharing.\n \t\t */\n-\t\tenum rte_keepalive_state core_state __rte_cache_aligned;\n+\t\talignas(RTE_CACHE_LINE_SIZE) enum rte_keepalive_state core_state;\n \t} live_data[RTE_KEEPALIVE_MAXCORES];\n \n \t/** Last-seen-alive timestamps */\ndiff --git a/lib/eal/common/rte_random.c b/lib/eal/common/rte_random.c\nindex 7709b8f..90e91b3 100644\n--- a/lib/eal/common/rte_random.c\n+++ b/lib/eal/common/rte_random.c\n@@ -13,14 +13,14 @@\n #include <rte_lcore.h>\n #include <rte_random.h>\n \n-struct rte_rand_state {\n+struct __rte_cache_aligned rte_rand_state {\n \tuint64_t z1;\n \tuint64_t z2;\n \tuint64_t z3;\n \tuint64_t z4;\n \tuint64_t z5;\n \tRTE_CACHE_GUARD;\n-} __rte_cache_aligned;\n+};\n \n /* One instance each for every lcore id-equipped thread, and one\n * additional instance to be shared by all others threads (i.e., all\ndiff --git a/lib/eal/common/rte_service.c b/lib/eal/common/rte_service.c\nindex d959c91..5637993 100644\n--- a/lib/eal/common/rte_service.c\n+++ b/lib/eal/common/rte_service.c\n@@ -32,7 +32,7 @@\n #define RUNSTATE_RUNNING 1\n \n /* internal representation of a service */\n-struct rte_service_spec_impl {\n+struct __rte_cache_aligned rte_service_spec_impl {\n \t/* public part of the struct */\n \tstruct rte_service_spec spec;\n \n@@ -53,7 +53,7 @@ struct rte_service_spec_impl {\n \t * on currently.\n \t */\n \tRTE_ATOMIC(uint32_t) num_mapped_cores;\n-} __rte_cache_aligned;\n+};\n \n struct service_stats {\n \tRTE_ATOMIC(uint64_t) calls;\n@@ -61,7 +61,7 @@ struct service_stats {\n };\n \n /* the internal values of a service core */\n-struct core_state {\n+struct __rte_cache_aligned core_state {\n \t/* map of services IDs are run on this core */\n \tuint64_t service_mask;\n \tRTE_ATOMIC(uint8_t) runstate; /* running or stopped */\n@@ -71,7 +71,7 @@ struct core_state {\n \tRTE_ATOMIC(uint64_t) loops;\n \tRTE_ATOMIC(uint64_t) cycles;\n \tstruct service_stats service_stats[RTE_SERVICE_NUM_MAX];\n-} __rte_cache_aligned;\n+};\n \n static uint32_t rte_service_count;\n static struct rte_service_spec_impl *rte_services;\ndiff --git a/lib/eal/include/generic/rte_atomic.h b/lib/eal/include/generic/rte_atomic.h\nindex 0e639da..f859707 100644\n--- a/lib/eal/include/generic/rte_atomic.h\n+++ b/lib/eal/include/generic/rte_atomic.h\n@@ -1094,7 +1094,7 @@ static inline void rte_atomic64_clear(rte_atomic64_t *v)\n /**\n * 128-bit integer structure.\n */\n-typedef struct {\n+typedef struct __rte_aligned(16) {\n \tunion {\n \t\tuint64_t val[2];\n #ifdef RTE_ARCH_64\n@@ -1103,7 +1103,7 @@ static inline void rte_atomic64_clear(rte_atomic64_t *v)\n #endif\n #endif\n \t};\n-} __rte_aligned(16) rte_int128_t;\n+} rte_int128_t;\n \n #ifdef __DOXYGEN__\n \ndiff --git a/lib/eal/include/rte_common.h b/lib/eal/include/rte_common.h\nindex 1cc1222..0908aa0 100644\n--- a/lib/eal/include/rte_common.h\n+++ b/lib/eal/include/rte_common.h\n@@ -12,6 +12,8 @@\n * for DPDK.\n */\n \n+#include <stdalign.h>\n+\n #ifdef __cplusplus\n extern \"C\" {\n #endif\n@@ -63,10 +65,19 @@\n #endif\n \n /**\n- * Force alignment\n+ * Force type alignment\n+ *\n+ * This macro should be used when alignment of a struct or union type\n+ * is required. For toolchain compatibility it should appear between\n+ * the {struct,union} keyword and tag. e.g.\n+ *\n+ * struct __rte_aligned(8) tag { ... };\n+ *\n+ * If alignment of an object/variable is required then this macro should\n+ * not be used, instead prefer C11 alignas(a).\n */\n #ifdef RTE_TOOLCHAIN_MSVC\n-#define __rte_aligned(a)\n+#define __rte_aligned(a) __declspec(align(a))\n #else\n #define __rte_aligned(a) __attribute__((__aligned__(a)))\n #endif\n@@ -538,18 +549,14 @@ static void __attribute__((destructor(RTE_PRIO(prio)), used)) func(void)\n #define RTE_CACHE_LINE_MIN_SIZE 64\n \n /** Force alignment to cache line. */\n-#ifdef RTE_TOOLCHAIN_MSVC\n-#define __rte_cache_aligned\n-#else\n #define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE)\n-#endif\n \n /** Force minimum cache line alignment. */\n #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)\n \n #define _RTE_CACHE_GUARD_HELPER2(unique) \\\n-\tchar cache_guard_ ## unique[RTE_CACHE_LINE_SIZE * RTE_CACHE_GUARD_LINES] \\\n-\t__rte_cache_aligned\n+\talignas(RTE_CACHE_LINE_SIZE) \\\n+\tchar cache_guard_ ## unique[RTE_CACHE_LINE_SIZE * RTE_CACHE_GUARD_LINES]\n #define _RTE_CACHE_GUARD_HELPER1(unique) _RTE_CACHE_GUARD_HELPER2(unique)\n /**\n * Empty cache lines, to guard against false sharing-like effects\ndiff --git a/lib/eal/loongarch/include/rte_vect.h b/lib/eal/loongarch/include/rte_vect.h\nindex 1546515..aa334e8 100644\n--- a/lib/eal/loongarch/include/rte_vect.h\n+++ b/lib/eal/loongarch/include/rte_vect.h\n@@ -15,7 +15,7 @@\n \n #define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED\n \n-typedef union xmm {\n+typedef union __rte_aligned(16) xmm {\n \tint8_t i8[16];\n \tint16_t i16[8];\n \tint32_t i32[4];\n@@ -25,19 +25,19 @@\n \tuint32_t u32[4];\n \tuint64_t u64[2];\n \tdouble pd[2];\n-} __rte_aligned(16) xmm_t;\n+} xmm_t;\n \n #define XMM_SIZE (sizeof(xmm_t))\n #define XMM_MASK (XMM_SIZE - 1)\n \n-typedef union rte_xmm {\n+typedef union __rte_aligned(16) rte_xmm {\n \txmm_t\t x;\n \tuint8_t\t u8[XMM_SIZE / sizeof(uint8_t)];\n \tuint16_t u16[XMM_SIZE / sizeof(uint16_t)];\n \tuint32_t u32[XMM_SIZE / sizeof(uint32_t)];\n \tuint64_t u64[XMM_SIZE / sizeof(uint64_t)];\n \tdouble pd[XMM_SIZE / sizeof(double)];\n-} __rte_aligned(16) rte_xmm_t;\n+} rte_xmm_t;\n \n static inline xmm_t\n vect_load_128(void *p)\ndiff --git a/lib/eal/ppc/include/rte_vect.h b/lib/eal/ppc/include/rte_vect.h\nindex a5f009b..c8bace2 100644\n--- a/lib/eal/ppc/include/rte_vect.h\n+++ b/lib/eal/ppc/include/rte_vect.h\n@@ -22,14 +22,14 @@\n #define\tXMM_SIZE\t(sizeof(xmm_t))\n #define\tXMM_MASK\t(XMM_SIZE - 1)\n \n-typedef union rte_xmm {\n+typedef union __rte_aligned(16) rte_xmm {\n \txmm_t x;\n \tuint8_t u8[XMM_SIZE / sizeof(uint8_t)];\n \tuint16_t u16[XMM_SIZE / sizeof(uint16_t)];\n \tuint32_t u32[XMM_SIZE / sizeof(uint32_t)];\n \tuint64_t u64[XMM_SIZE / sizeof(uint64_t)];\n \tdouble pd[XMM_SIZE / sizeof(double)];\n-} __rte_aligned(16) rte_xmm_t;\n+} rte_xmm_t;\n \n #ifdef __cplusplus\n }\ndiff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h\nindex da9092a..6df10fa 100644\n--- a/lib/eal/riscv/include/rte_vect.h\n+++ b/lib/eal/riscv/include/rte_vect.h\n@@ -22,14 +22,14 @@\n #define XMM_SIZE\t(sizeof(xmm_t))\n #define XMM_MASK\t(XMM_SIZE - 1)\n \n-typedef union rte_xmm {\n+typedef union __rte_aligned(16) rte_xmm {\n \txmm_t\t\tx;\n \tuint8_t\t\tu8[XMM_SIZE / sizeof(uint8_t)];\n \tuint16_t\tu16[XMM_SIZE / sizeof(uint16_t)];\n \tuint32_t\tu32[XMM_SIZE / sizeof(uint32_t)];\n \tuint64_t\tu64[XMM_SIZE / sizeof(uint64_t)];\n \tdouble\t\tpd[XMM_SIZE / sizeof(double)];\n-} __rte_aligned(16) rte_xmm_t;\n+} rte_xmm_t;\n \n static inline xmm_t\n vect_load_128(void *p)\ndiff --git a/lib/eal/x86/include/rte_vect.h b/lib/eal/x86/include/rte_vect.h\nindex 560f9e4..a1a537e 100644\n--- a/lib/eal/x86/include/rte_vect.h\n+++ b/lib/eal/x86/include/rte_vect.h\n@@ -91,7 +91,7 @@\n #define RTE_X86_ZMM_SIZE\t(sizeof(__m512i))\n #define RTE_X86_ZMM_MASK\t(RTE_X86_ZMM_SIZE - 1)\n \n-typedef union __rte_x86_zmm {\n+typedef union __rte_aligned(RTE_X86_ZMM_SIZE) __rte_x86_zmm {\n \t__m512i\t z;\n \tymm_t y[RTE_X86_ZMM_SIZE / sizeof(ymm_t)];\n \txmm_t x[RTE_X86_ZMM_SIZE / sizeof(xmm_t)];\n@@ -100,7 +100,7 @@\n \tuint32_t u32[RTE_X86_ZMM_SIZE / sizeof(uint32_t)];\n \tuint64_t u64[RTE_X86_ZMM_SIZE / sizeof(uint64_t)];\n \tdouble pd[RTE_X86_ZMM_SIZE / sizeof(double)];\n-} __rte_aligned(RTE_X86_ZMM_SIZE) __rte_x86_zmm_t;\n+} __rte_x86_zmm_t;\n \n #endif /* __AVX512F__ */\n \ndiff --git a/lib/eal/x86/rte_power_intrinsics.c b/lib/eal/x86/rte_power_intrinsics.c\nindex 532a2e6..6d9b642 100644\n--- a/lib/eal/x86/rte_power_intrinsics.c\n+++ b/lib/eal/x86/rte_power_intrinsics.c\n@@ -2,6 +2,8 @@\n * Copyright(c) 2020 Intel Corporation\n */\n \n+#include <stdalign.h>\n+\n #include <rte_common.h>\n #include <rte_lcore.h>\n #include <rte_rtm.h>\n@@ -12,10 +14,10 @@\n /*\n * Per-lcore structure holding current status of C0.2 sleeps.\n */\n-static struct power_wait_status {\n+static alignas(RTE_CACHE_LINE_SIZE) struct power_wait_status {\n \trte_spinlock_t lock;\n \tvolatile void *monitor_addr; /**< NULL if not currently sleeping */\n-} __rte_cache_aligned wait_status[RTE_MAX_LCORE];\n+} wait_status[RTE_MAX_LCORE];\n \n /*\n * This function uses UMONITOR/UMWAIT instructions and will enter C0.2 state.\n@@ -85,10 +87,10 @@ static void amd_mwaitx(const uint64_t timeout)\n #endif\n }\n \n-static struct {\n+static alignas(RTE_CACHE_LINE_SIZE) struct {\n \tvoid (*mmonitor)(volatile void *addr);\n \tvoid (*mwait)(const uint64_t timeout);\n-} __rte_cache_aligned power_monitor_ops;\n+} power_monitor_ops;\n \n static inline void\n __umwait_wakeup(volatile void *addr)\n", "prefixes": [ "v5", "01/39" ] }