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GET /api/patches/137109/?format=api
{ "id": 137109, "url": "http://patches.dpdk.org/api/patches/137109/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240223153938.1393597-1-vattunuru@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240223153938.1393597-1-vattunuru@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240223153938.1393597-1-vattunuru@marvell.com", "date": "2024-02-23T15:39:38", "name": "[1/1] net/octeon_ep: use devarg to enable ISM accesses", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "fbe2ae33a187541008df2b5cda204b18ec3b2442", "submitter": { "id": 1277, "url": "http://patches.dpdk.org/api/people/1277/?format=api", "name": "Vamsi Krishna Attunuru", "email": "vattunuru@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240223153938.1393597-1-vattunuru@marvell.com/mbox/", "series": [ { "id": 31206, "url": "http://patches.dpdk.org/api/series/31206/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31206", "date": "2024-02-23T15:39:38", "name": "[1/1] net/octeon_ep: use devarg to enable ISM accesses", "version": 1, "mbox": "http://patches.dpdk.org/series/31206/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137109/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137109/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9DF0843B9C;\n\tFri, 23 Feb 2024 16:39:55 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 27AFA4027A;\n\tFri, 23 Feb 2024 16:39:55 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 0EE064021E\n for <dev@dpdk.org>; Fri, 23 Feb 2024 16:39:52 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 41N9DEGi025225 for <dev@dpdk.org>; Fri, 23 Feb 2024 07:39:52 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3werhd95kq-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 23 Feb 2024 07:39:52 -0800 (PST)", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Fri, 23 Feb 2024 07:39:50 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Fri, 23 Feb 2024 07:39:50 -0800", "from localhost.localdomain (unknown [10.28.36.156])\n by maili.marvell.com (Postfix) with ESMTP id 9C0FF3F723F;\n Fri, 23 Feb 2024 07:39:48 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:mime-version\n :content-transfer-encoding:content-type; s=pfpt0220; bh=2HAkTPR6\n GRQO/XMN0AVHO4pogGPY4gjvg0JV+fanCSw=; b=bro5jGeMbXacP13xwLNXlGzi\n NbvX0ytlW5SNlQTQj3Og64zsn/SCxqX+yMxIKusHT+sOHEaCBKEYIyBdbLcY6mLI\n xX6YHXMSvieMPt0XJa+ZYcyh1HRDIfbed3p/HiSqa7zrNKsJkE9m0Nk+IM+yPRGj\n w6/EPkZp4yOJaA6bfirRVTTnRfnPZMXwD1oR9D6m7WlVzKbz3sHxz+VH6STOI6rY\n Dj6W++75hZ3i/FgThUhTTi9q1b/Hrj9mwO+vOkPa6TjmFBSuVstucibH+0XqTSdK\n jU/NdgO0ekkFpgY+dwbD4n1UmgVD2A27+rg5+sstfObYQFg3D3P5DsruD2iPqA==", "From": "Vamsi Attunuru <vattunuru@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <vattunuru@marvell.com>", "Subject": "[PATCH 1/1] net/octeon_ep: use devarg to enable ISM accesses", "Date": "Fri, 23 Feb 2024 07:39:38 -0800", "Message-ID": "<20240223153938.1393597-1-vattunuru@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "bqowmB2ISWbzJt5L0JldDDplE-VZTYjx", "X-Proofpoint-ORIG-GUID": "bqowmB2ISWbzJt5L0JldDDplE-VZTYjx", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-02-23_01,2024-02-23_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adds a devarg option to enable/disable ISM memory accesses\nfor reading packet count details. This option is disabled\nby default, as ISM memory accesses effect throughput of\nbigger size packets.\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n doc/guides/nics/octeon_ep.rst | 12 ++++++++\n drivers/net/octeon_ep/cnxk_ep_rx.h | 42 +++++++++++++++++++++-----\n drivers/net/octeon_ep/cnxk_ep_tx.c | 42 ++++++++++++++++++++++----\n drivers/net/octeon_ep/cnxk_ep_vf.c | 4 +--\n drivers/net/octeon_ep/otx2_ep_vf.c | 4 +--\n drivers/net/octeon_ep/otx_ep_common.h | 14 +++++++--\n drivers/net/octeon_ep/otx_ep_ethdev.c | 43 +++++++++++++++++++++++++++\n drivers/net/octeon_ep/otx_ep_rxtx.c | 15 ++++++----\n drivers/net/octeon_ep/otx_ep_rxtx.h | 2 ++\n 9 files changed, 153 insertions(+), 25 deletions(-)", "diff": "diff --git a/doc/guides/nics/octeon_ep.rst b/doc/guides/nics/octeon_ep.rst\nindex b5040aeee2..befa0a4097 100644\n--- a/doc/guides/nics/octeon_ep.rst\n+++ b/doc/guides/nics/octeon_ep.rst\n@@ -11,6 +11,18 @@ and **Cavium OCTEON** families of adapters in SR-IOV context.\n More information can be found at `Marvell Official Website\n <https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-liquidio-III-solutions-brief.pdf>`_.\n \n+Runtime Config Options\n+----------------------\n+\n+- ``Rx&Tx ISM memory accesses enable`` (default ``0``)\n+\n+ PMD supports 2 modes for checking Rx & Tx packet count, PMD may read the packet count directly\n+ from hardware registers or it may read from ISM memory, this may be selected at runtime\n+ using ``ism_enable`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:02:00.0,ism_enable=1\n \n Prerequisites\n -------------\ndiff --git a/drivers/net/octeon_ep/cnxk_ep_rx.h b/drivers/net/octeon_ep/cnxk_ep_rx.h\nindex 61263e651e..ecf95cd961 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_rx.h\n+++ b/drivers/net/octeon_ep/cnxk_ep_rx.h\n@@ -88,8 +88,9 @@ cnxk_ep_rx_refill(struct otx_ep_droq *droq)\n }\n \n static inline uint32_t\n-cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq)\n+cnxk_ep_check_rx_ism_mem(void *rx_queue)\n {\n+\tstruct otx_ep_droq *droq = (struct otx_ep_droq *)rx_queue;\n \tuint32_t new_pkts;\n \tuint32_t val;\n \n@@ -98,8 +99,9 @@ cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq)\n \t * number of PCIe writes.\n \t */\n \tval = __atomic_load_n(droq->pkts_sent_ism, __ATOMIC_RELAXED);\n-\tnew_pkts = val - droq->pkts_sent_ism_prev;\n-\tdroq->pkts_sent_ism_prev = val;\n+\n+\tnew_pkts = val - droq->pkts_sent_prev;\n+\tdroq->pkts_sent_prev = val;\n \n \tif (val > RTE_BIT32(31)) {\n \t\t/* Only subtract the packet count in the HW counter\n@@ -113,11 +115,34 @@ cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq)\n \t\t\trte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);\n \t\t\trte_mb();\n \t\t}\n-\n-\t\tdroq->pkts_sent_ism_prev = 0;\n+\t\tdroq->pkts_sent_prev = 0;\n \t}\n+\n \trte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);\n-\tdroq->pkts_pending += new_pkts;\n+\n+\treturn new_pkts;\n+}\n+\n+static inline uint32_t\n+cnxk_ep_check_rx_pkt_reg(void *rx_queue)\n+{\n+\tstruct otx_ep_droq *droq = (struct otx_ep_droq *)rx_queue;\n+\tuint32_t new_pkts;\n+\tuint32_t val;\n+\n+\tval = rte_read32(droq->pkts_sent_reg);\n+\n+\tnew_pkts = val - droq->pkts_sent_prev;\n+\tdroq->pkts_sent_prev = val;\n+\n+\tif (val > RTE_BIT32(31)) {\n+\t\t/* Only subtract the packet count in the HW counter\n+\t\t * when count above halfway to saturation.\n+\t\t */\n+\t\trte_write64((uint64_t)val, droq->pkts_sent_reg);\n+\t\trte_mb();\n+\t\tdroq->pkts_sent_prev = 0;\n+\t}\n \n \treturn new_pkts;\n }\n@@ -125,8 +150,11 @@ cnxk_ep_check_rx_pkts(struct otx_ep_droq *droq)\n static inline int16_t __rte_hot\n cnxk_ep_rx_pkts_to_process(struct otx_ep_droq *droq, uint16_t nb_pkts)\n {\n+\tconst otx_ep_check_pkt_count_t cnxk_rx_pkt_count[2] = { cnxk_ep_check_rx_pkt_reg,\n+\t\t\t\t\t\t\t\tcnxk_ep_check_rx_ism_mem};\n+\n \tif (droq->pkts_pending < nb_pkts)\n-\t\tcnxk_ep_check_rx_pkts(droq);\n+\t\tdroq->pkts_pending += cnxk_rx_pkt_count[droq->ism_ena](droq);\n \n \treturn RTE_MIN(nb_pkts, droq->pkts_pending);\n }\ndiff --git a/drivers/net/octeon_ep/cnxk_ep_tx.c b/drivers/net/octeon_ep/cnxk_ep_tx.c\nindex 9f11a2f317..98c0a861c3 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_tx.c\n+++ b/drivers/net/octeon_ep/cnxk_ep_tx.c\n@@ -5,9 +5,10 @@\n #include \"cnxk_ep_vf.h\"\n #include \"otx_ep_rxtx.h\"\n \n-static uint32_t\n-cnxk_vf_update_read_index(struct otx_ep_instr_queue *iq)\n+static inline uint32_t\n+cnxk_ep_check_tx_ism_mem(void *tx_queue)\n {\n+\tstruct otx_ep_instr_queue *iq = (struct otx_ep_instr_queue *)tx_queue;\n \tuint32_t val;\n \n \t/* Batch subtractions from the HW counter to reduce PCIe traffic\n@@ -15,8 +16,8 @@ cnxk_vf_update_read_index(struct otx_ep_instr_queue *iq)\n \t * number of PCIe writes.\n \t */\n \tval = __atomic_load_n(iq->inst_cnt_ism, __ATOMIC_RELAXED);\n-\tiq->inst_cnt += val - iq->inst_cnt_ism_prev;\n-\tiq->inst_cnt_ism_prev = val;\n+\tiq->inst_cnt += val - iq->inst_cnt_prev;\n+\tiq->inst_cnt_prev = val;\n \n \tif (val > (uint32_t)(1 << 31)) {\n \t\t/* Only subtract the packet count in the HW counter\n@@ -31,7 +32,7 @@ cnxk_vf_update_read_index(struct otx_ep_instr_queue *iq)\n \t\t\trte_mb();\n \t\t}\n \n-\t\tiq->inst_cnt_ism_prev = 0;\n+\t\tiq->inst_cnt_prev = 0;\n \t}\n \trte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);\n \n@@ -41,13 +42,42 @@ cnxk_vf_update_read_index(struct otx_ep_instr_queue *iq)\n \treturn iq->inst_cnt & (iq->nb_desc - 1);\n }\n \n+static inline uint32_t\n+cnxk_ep_check_tx_pkt_reg(void *tx_queue)\n+{\n+\tstruct otx_ep_instr_queue *iq = (struct otx_ep_instr_queue *)tx_queue;\n+\tuint32_t val;\n+\n+\tval = rte_read32(iq->inst_cnt_reg);\n+\tiq->inst_cnt += val - iq->inst_cnt_prev;\n+\tiq->inst_cnt_prev = val;\n+\n+\tif (val > (uint32_t)(1 << 31)) {\n+\t\t/* Only subtract the packet count in the HW counter\n+\t\t * when count above halfway to saturation.\n+\t\t */\n+\t\trte_write64((uint64_t)val, iq->inst_cnt_reg);\n+\t\trte_mb();\n+\n+\t\tiq->inst_cnt_prev = 0;\n+\t}\n+\n+\t/* Modulo of the new index with the IQ size will give us\n+\t * the new index.\n+\t */\n+\treturn iq->inst_cnt & (iq->nb_desc - 1);\n+}\n+\n static inline void\n cnxk_ep_flush_iq(struct otx_ep_instr_queue *iq)\n {\n+\tconst otx_ep_check_pkt_count_t cnxk_tx_pkt_count[2] = { cnxk_ep_check_tx_pkt_reg,\n+\t\t\t\t\t\t\t\tcnxk_ep_check_tx_ism_mem};\n+\n \tuint32_t instr_processed = 0;\n \tuint32_t cnt = 0;\n \n-\tiq->otx_read_index = cnxk_vf_update_read_index(iq);\n+\tiq->otx_read_index = cnxk_tx_pkt_count[iq->ism_ena](iq);\n \n \tif (unlikely(iq->flush_index == iq->otx_read_index))\n \t\treturn;\ndiff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/cnxk_ep_vf.c\nindex ef275703c3..39f357ee81 100644\n--- a/drivers/net/octeon_ep/cnxk_ep_vf.c\n+++ b/drivers/net/octeon_ep/cnxk_ep_vf.c\n@@ -155,7 +155,7 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \totx_ep_err(\"SDP_R[%d] INST Q ISM virt: %p, dma: 0x%\" PRIX64, iq_no,\n \t\t (void *)iq->inst_cnt_ism, ism_addr);\n \t*iq->inst_cnt_ism = 0;\n-\tiq->inst_cnt_ism_prev = 0;\n+\tiq->inst_cnt_prev = 0;\n \tiq->partial_ih = ((uint64_t)otx_ep->pkind) << 36;\n \n \treturn 0;\n@@ -240,7 +240,7 @@ cnxk_ep_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \totx_ep_err(\"SDP_R[%d] OQ ISM virt: %p dma: 0x%\" PRIX64,\n \t\t oq_no, (void *)droq->pkts_sent_ism, ism_addr);\n \t*droq->pkts_sent_ism = 0;\n-\tdroq->pkts_sent_ism_prev = 0;\n+\tdroq->pkts_sent_prev = 0;\n \n \tloop = OTX_EP_BUSY_LOOP_COUNT;\n \twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull) && loop--) {\ndiff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c\nindex 7f4edf8dcf..25e0e5a500 100644\n--- a/drivers/net/octeon_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeon_ep/otx2_ep_vf.c\n@@ -306,7 +306,7 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n \t\t (void *)iq->inst_cnt_ism,\n \t\t (unsigned int)ism_addr);\n \t*iq->inst_cnt_ism = 0;\n-\tiq->inst_cnt_ism_prev = 0;\n+\tiq->inst_cnt_prev = 0;\n \tiq->partial_ih = ((uint64_t)otx_ep->pkind) << 36;\n \n \treturn 0;\n@@ -392,7 +392,7 @@ otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)\n \t\t (void *)droq->pkts_sent_ism,\n \t\t (unsigned int)ism_addr);\n \t*droq->pkts_sent_ism = 0;\n-\tdroq->pkts_sent_ism_prev = 0;\n+\tdroq->pkts_sent_prev = 0;\n \n \tloop = SDP_VF_BUSY_LOOP_COUNT;\n \twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull) && loop--) {\ndiff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h\nindex d64b04d2c2..7776940e1d 100644\n--- a/drivers/net/octeon_ep/otx_ep_common.h\n+++ b/drivers/net/octeon_ep/otx_ep_common.h\n@@ -9,6 +9,7 @@\n #include <unistd.h>\n #include <assert.h>\n #include <rte_eal.h>\n+#include <rte_kvargs.h>\n #include <rte_mempool.h>\n #include <rte_mbuf.h>\n #include <rte_io.h>\n@@ -223,7 +224,7 @@ struct otx_ep_instr_queue {\n \tuint8_t *base_addr;\n \n \t/* track inst count locally to consolidate HW counter updates */\n-\tuint32_t inst_cnt_ism_prev;\n+\tuint32_t inst_cnt_prev;\n \n \t/* Input ring index, where the driver should write the next packet */\n \tuint32_t host_write_index;\n@@ -261,6 +262,9 @@ struct otx_ep_instr_queue {\n \t/* Number of descriptors in this ring. */\n \tuint32_t nb_desc;\n \n+\t/* Use ISM memory */\n+\tuint8_t ism_ena;\n+\n \t/* Size of the descriptor. */\n \tuint8_t desc_size;\n \n@@ -405,9 +409,12 @@ struct otx_ep_droq {\n \t */\n \tvoid *pkts_sent_reg;\n \n+\t/* Use ISM memory */\n+\tuint8_t ism_ena;\n+\n \t/* Pointer to host memory copy of output packet count, set by ISM */\n \tuint32_t *pkts_sent_ism;\n-\tuint32_t pkts_sent_ism_prev;\n+\tuint32_t pkts_sent_prev;\n \n \t/* Statistics for this DROQ. */\n \tstruct otx_ep_droq_stats stats;\n@@ -565,6 +572,9 @@ struct otx_ep_device {\n \n \t/* Generation */\n \tuint32_t chip_gen;\n+\n+\t/* Use ISM memory */\n+\tuint8_t ism_ena;\n };\n \n int otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no,\ndiff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c\nindex 8daa7d225c..86ed6df6a9 100644\n--- a/drivers/net/octeon_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeon_ep/otx_ep_ethdev.c\n@@ -15,6 +15,8 @@\n #define OTX_EP_DEV(_eth_dev) \\\n \t((struct otx_ep_device *)(_eth_dev)->data->dev_private)\n \n+#define OTX_ISM_ENABLE\t\"ism_enable\"\n+\n static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = {\n \t.nb_max\t\t= OTX_EP_MAX_OQ_DESCRIPTORS,\n \t.nb_min\t\t= OTX_EP_MIN_OQ_DESCRIPTORS,\n@@ -27,6 +29,41 @@ static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = {\n \t.nb_align\t= OTX_EP_TXD_ALIGN,\n };\n \n+static int\n+parse_flag(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t*(uint8_t *)extra_args = atoi(value);\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx_ep_device *otx_epvf)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\tuint8_t ism_enable = 0;\n+\n+\tif (devargs == NULL)\n+\t\tgoto null_devargs;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\tgoto exit;\n+\n+\trte_kvargs_process(kvlist, OTX_ISM_ENABLE, &parse_flag, &ism_enable);\n+\trte_kvargs_free(kvlist);\n+\n+null_devargs:\n+\totx_epvf->ism_ena = !!ism_enable;\n+\n+\treturn 0;\n+\n+exit:\n+\treturn -EINVAL;\n+}\n+\n static void\n otx_ep_set_tx_func(struct rte_eth_dev *eth_dev)\n {\n@@ -741,6 +778,12 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t\treturn 0;\n \t}\n \n+\t/* Parse devargs string */\n+\tif (otx_ethdev_parse_devargs(eth_dev->device->devargs, otx_epvf)) {\n+\t\totx_ep_err(\"Failed to parse devargs\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n \trte_eth_copy_pci_info(eth_dev, pdev);\n \totx_epvf->eth_dev = eth_dev;\n \totx_epvf->port_id = eth_dev->data->port_id;\ndiff --git a/drivers/net/octeon_ep/otx_ep_rxtx.c b/drivers/net/octeon_ep/otx_ep_rxtx.c\nindex aea148ee4a..59144e0f84 100644\n--- a/drivers/net/octeon_ep/otx_ep_rxtx.c\n+++ b/drivers/net/octeon_ep/otx_ep_rxtx.c\n@@ -11,6 +11,7 @@\n #include <rte_net.h>\n #include <ethdev_pci.h>\n \n+#include \"cnxk_ep_rx.h\"\n #include \"otx_ep_common.h\"\n #include \"otx_ep_vf.h\"\n #include \"otx_ep_rxtx.h\"\n@@ -159,6 +160,7 @@ otx_ep_init_instr_queue(struct otx_ep_device *otx_ep, int iq_no, int num_descs,\n \t\totx_ep->io_qmask.iq64B |= (1ull << iq_no);\n \n \tiq->iqcmd_64B = (conf->iq.instr_type == 64);\n+\tiq->ism_ena = otx_ep->ism_ena;\n \n \t/* Set up IQ registers */\n \tret = otx_ep->fn_list.setup_iq_regs(otx_ep, iq_no);\n@@ -367,6 +369,7 @@ otx_ep_init_droq(struct otx_ep_device *otx_ep, uint32_t q_no,\n \n \tdroq->refill_threshold = c_refill_threshold;\n \tdroq->rearm_data = otx_ep_set_rearm_data(otx_ep);\n+\tdroq->ism_ena = otx_ep->ism_ena;\n \n \t/* Set up OQ registers */\n \tret = otx_ep->fn_list.setup_oq_regs(otx_ep, q_no);\n@@ -460,8 +463,8 @@ otx_vf_update_read_index(struct otx_ep_instr_queue *iq)\n \t * number of PCIe writes.\n \t */\n \tval = *iq->inst_cnt_ism;\n-\tiq->inst_cnt += val - iq->inst_cnt_ism_prev;\n-\tiq->inst_cnt_ism_prev = val;\n+\tiq->inst_cnt += val - iq->inst_cnt_prev;\n+\tiq->inst_cnt_prev = val;\n \n \tif (val > (uint32_t)(1 << 31)) {\n \t\t/*\n@@ -477,7 +480,7 @@ otx_vf_update_read_index(struct otx_ep_instr_queue *iq)\n \t\t\trte_mb();\n \t\t}\n \n-\t\tiq->inst_cnt_ism_prev = 0;\n+\t\tiq->inst_cnt_prev = 0;\n \t}\n \trte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);\n \n@@ -856,8 +859,8 @@ otx_ep_check_droq_pkts(struct otx_ep_droq *droq)\n \t * number of PCIe writes.\n \t */\n \tval = *droq->pkts_sent_ism;\n-\tnew_pkts = val - droq->pkts_sent_ism_prev;\n-\tdroq->pkts_sent_ism_prev = val;\n+\tnew_pkts = val - droq->pkts_sent_prev;\n+\tdroq->pkts_sent_prev = val;\n \n \tif (val > (uint32_t)(1 << 31)) {\n \t\t/*\n@@ -873,7 +876,7 @@ otx_ep_check_droq_pkts(struct otx_ep_droq *droq)\n \t\t\trte_mb();\n \t\t}\n \n-\t\tdroq->pkts_sent_ism_prev = 0;\n+\t\tdroq->pkts_sent_prev = 0;\n \t}\n \trte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);\n \tdroq->pkts_pending += new_pkts;\ndiff --git a/drivers/net/octeon_ep/otx_ep_rxtx.h b/drivers/net/octeon_ep/otx_ep_rxtx.h\nindex f5bc807dc0..6b3abe21b1 100644\n--- a/drivers/net/octeon_ep/otx_ep_rxtx.h\n+++ b/drivers/net/octeon_ep/otx_ep_rxtx.h\n@@ -24,6 +24,8 @@\n #define DROQ_REFILL_THRESHOLD 64\n #define OTX2_SDP_REQUEST_ISM (0x1ULL << 63)\n \n+typedef uint32_t (*otx_ep_check_pkt_count_t)(void *queue);\n+\n static inline uint32_t\n otx_ep_incr_index(uint32_t index, uint32_t count, uint32_t max)\n {\n", "prefixes": [ "1/1" ] }