Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 137105,
    "url": "http://patches.dpdk.org/api/patches/137105/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240223151255.3310490-3-ciara.power@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20240223151255.3310490-3-ciara.power@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20240223151255.3310490-3-ciara.power@intel.com",
    "date": "2024-02-23T15:12:53",
    "name": "[v2,2/4] common/qat: add zuc256 wireless slice for gen3",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "0699714cad4e7786bdea873c4f8d8a145399845d",
    "submitter": {
        "id": 978,
        "url": "http://patches.dpdk.org/api/people/978/?format=api",
        "name": "Power, Ciara",
        "email": "ciara.power@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240223151255.3310490-3-ciara.power@intel.com/mbox/",
    "series": [
        {
            "id": 31204,
            "url": "http://patches.dpdk.org/api/series/31204/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31204",
            "date": "2024-02-23T15:12:51",
            "name": "add new QAT gen3 and gen5",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/31204/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/137105/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/137105/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7F61943B82;\n\tFri, 23 Feb 2024 16:13:24 +0100 (CET)",
            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3E71B41611;\n\tFri, 23 Feb 2024 16:13:14 +0100 (CET)",
            "from mgamail.intel.com (mgamail.intel.com [198.175.65.20])\n by mails.dpdk.org (Postfix) with ESMTP id 38EFB410D5\n for <dev@dpdk.org>; Fri, 23 Feb 2024 16:13:11 +0100 (CET)",
            "from fmviesa009.fm.intel.com ([10.60.135.149])\n by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 Feb 2024 07:13:11 -0800",
            "from silpixa00401797.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.113])\n by fmviesa009.fm.intel.com with ESMTP; 23 Feb 2024 07:13:09 -0800"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1708701192; x=1740237192;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=eo9IIjx/ebfG7zGx3955u+m7Ryx6vDIvy4GoL5d4JtE=;\n b=lH8gM1fEylJabVYJsIhfWVIImu4frGiF+J/Q4oNWWrVn5Pa76U82bvFm\n djzrVhetUVFZiWbgHOAo4vZ6swrLT5LkoQqXQKWWS3vZD9O22BRVxL3Kn\n I9mE/2ujVoeeQW2T25w+Py1D0ppqn/2YojHKOZuE8arWGdmkB84Xhh3od\n GvJvZNvn+w91E0vVIHnkRuVOwiXCtiQSrsA2zV3ivwyHnl4bHzkz/T2sK\n gB0MBUM3WWROTkxC7xkj6fkfqvAW1UqCGQ+tTPRQSUctE2YcsJsKn1NWj\n mnCdguKrdFE8GjwoSYha9JaDEPuSvNlPGOr0okT8jFJH6NEv6WtN23Q90 A==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6600,9927,10993\"; a=\"2905936\"",
            "E=Sophos;i=\"6.06,180,1705392000\";\n   d=\"scan'208\";a=\"2905936\"",
            "E=Sophos;i=\"6.06,180,1705392000\";\n   d=\"scan'208\";a=\"5881551\""
        ],
        "X-ExtLoop1": "1",
        "From": "Ciara Power <ciara.power@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "gakhil@marvell.com, kai.ji@intel.com, arkadiuszx.kusztal@intel.com,\n Ciara Power <ciara.power@intel.com>",
        "Subject": "[PATCH v2 2/4] common/qat: add zuc256 wireless slice for gen3",
        "Date": "Fri, 23 Feb 2024 15:12:53 +0000",
        "Message-Id": "<20240223151255.3310490-3-ciara.power@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20240223151255.3310490-1-ciara.power@intel.com>",
        "References": "<20231219155124.4133385-1-ciara.power@intel.com>\n <20240223151255.3310490-1-ciara.power@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "The new gen3 device handles wireless algorithms on wireless slices,\nbased on the device wireless slice support, set the required flags for\nthese algorithms to move slice.\n\nOne of the algorithms supported for the wireless slices is ZUC 256,\nsupport is added for this, along with modifying the capability for the\ndevice.\nThe device supports 24 bytes iv for ZUC 256, with iv[20]\nbeing ignored in register.\nFor 25 byte iv, compress this into 23 bytes.\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n---\nv2:\n  - Fixed setting extended protocol flag bit position.\n  - Added slice map check for ZUC256 wireless slice.\n  - Fixed IV modification for ZUC256 in raw datapath.\n  - Added increment size for ZUC256 capabiltiies.\n  - Added release note.\n---\n doc/guides/rel_notes/release_24_03.rst       |   1 +\n drivers/common/qat/qat_adf/icp_qat_fw.h      |   6 +-\n drivers/common/qat/qat_adf/icp_qat_fw_la.h   |  24 ++++\n drivers/common/qat/qat_adf/icp_qat_hw.h      |  24 +++-\n drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |   7 +-\n drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c |  52 ++++++-\n drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  34 ++++-\n drivers/crypto/qat/dev/qat_sym_pmd_gen1.c    |  43 ++++++\n drivers/crypto/qat/qat_sym_session.c         | 142 +++++++++++++++++--\n drivers/crypto/qat/qat_sym_session.h         |   2 +\n 10 files changed, 312 insertions(+), 23 deletions(-)",
    "diff": "diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 55517eabd8..0dee1ff104 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -134,6 +134,7 @@ New Features\n * **Updated Intel QuickAssist Technology driver.**\n \n   * Enabled support for new QAT GEN3 (578a) devices in QAT crypto driver.\n+  * Enabled ZUC256 cipher and auth algorithm for wireless slice enabled GEN3 device.\n \n * **Updated Marvell cnxk crypto driver.**\n \ndiff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h\nindex 3aa17ae041..dd7c926140 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h\n@@ -75,7 +75,8 @@ struct icp_qat_fw_comn_req_hdr {\n \tuint8_t service_type;\n \tuint8_t hdr_flags;\n \tuint16_t serv_specif_flags;\n-\tuint16_t comn_req_flags;\n+\tuint8_t comn_req_flags;\n+\tuint8_t ext_flags;\n };\n \n struct icp_qat_fw_comn_req_rqpars {\n@@ -176,9 +177,6 @@ struct icp_qat_fw_comn_resp {\n #define QAT_COMN_PTR_TYPE_SGL 0x1\n #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0\n #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1\n-#define QAT_COMN_EXT_FLAGS_BITPOS 8\n-#define QAT_COMN_EXT_FLAGS_MASK 0x1\n-#define QAT_COMN_EXT_FLAGS_USED 0x1\n \n #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \\\n \t((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \\\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\nindex 70f0effa62..134c309355 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n@@ -81,6 +81,15 @@ struct icp_qat_fw_la_bulk_req {\n #define ICP_QAT_FW_LA_PARTIAL_END 2\n #define QAT_LA_PARTIAL_BITPOS 0\n #define QAT_LA_PARTIAL_MASK 0x3\n+#define QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_BITPOS 0\n+#define QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS 1\n+#define QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_MASK 0x1\n+#define QAT_LA_USE_WCP_SLICE 1\n+#define QAT_LA_USE_WCP_SLICE_BITPOS 2\n+#define QAT_LA_USE_WCP_SLICE_MASK 0x1\n+#define QAT_LA_USE_WAT_SLICE_BITPOS 3\n+#define QAT_LA_USE_WAT_SLICE 1\n+#define QAT_LA_USE_WAT_SLICE_MASK 0x1\n #define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \\\n \tcmp_auth, ret_auth, update_state, \\\n \tciph_iv, ciphcfg, partial) \\\n@@ -188,6 +197,21 @@ struct icp_qat_fw_la_bulk_req {\n \tQAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \\\n \tQAT_LA_PARTIAL_MASK)\n \n+#define ICP_QAT_FW_USE_EXTENDED_PROTOCOL_FLAGS_SET(flags, val)\t\\\n+\tQAT_FIELD_SET(flags, val,\t\t\t\t\\\n+\tQAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_BITPOS,\t\t\\\n+\tQAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_MASK)\n+\n+#define ICP_QAT_FW_USE_WCP_SLICE_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, \\\n+\tQAT_LA_USE_WCP_SLICE_BITPOS, \\\n+\tQAT_LA_USE_WCP_SLICE_MASK)\n+\n+#define ICP_QAT_FW_USE_WAT_SLICE_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, \\\n+\tQAT_LA_USE_WAT_SLICE_BITPOS, \\\n+\tQAT_LA_USE_WAT_SLICE_MASK)\n+\n #define QAT_FW_LA_MODE2 1\n #define QAT_FW_LA_NO_MODE2 0\n #define QAT_FW_LA_MODE2_MASK 0x1\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h\nindex 33756d512d..4651fb90bb 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_hw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h\n@@ -21,7 +21,8 @@ enum icp_qat_slice_mask {\n \tICP_ACCEL_MASK_CRYPTO1_SLICE = 0x100,\n \tICP_ACCEL_MASK_CRYPTO2_SLICE = 0x200,\n \tICP_ACCEL_MASK_SM3_SLICE = 0x400,\n-\tICP_ACCEL_MASK_SM4_SLICE = 0x800\n+\tICP_ACCEL_MASK_SM4_SLICE = 0x800,\n+\tICP_ACCEL_MASK_ZUC_256_SLICE = 0x2000,\n };\n \n enum icp_qat_hw_ae_id {\n@@ -71,7 +72,16 @@ enum icp_qat_hw_auth_algo {\n \tICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,\n \tICP_QAT_HW_AUTH_ALGO_SHA3_384 = 18,\n \tICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,\n-\tICP_QAT_HW_AUTH_ALGO_DELIMITER = 20\n+\tICP_QAT_HW_AUTH_ALGO_RESERVED = 20,\n+\tICP_QAT_HW_AUTH_ALGO_RESERVED1 = 21,\n+\tICP_QAT_HW_AUTH_ALGO_RESERVED2 = 22,\n+\tICP_QAT_HW_AUTH_ALGO_RESERVED3 = 22,\n+\tICP_QAT_HW_AUTH_ALGO_RESERVED4 = 23,\n+\tICP_QAT_HW_AUTH_ALGO_RESERVED5 = 24,\n+\tICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 = 25,\n+\tICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64 = 26,\n+\tICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128 = 27,\n+\tICP_QAT_HW_AUTH_ALGO_DELIMITER = 28\n };\n \n enum icp_qat_hw_auth_mode {\n@@ -167,6 +177,9 @@ struct icp_qat_hw_auth_setup {\n #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16\n #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8\n #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8\n+#define ICP_QAT_HW_ZUC_256_MAC_32_STATE1_SZ 8\n+#define ICP_QAT_HW_ZUC_256_MAC_64_STATE1_SZ 8\n+#define ICP_QAT_HW_ZUC_256_MAC_128_STATE1_SZ 16\n \n #define ICP_QAT_HW_NULL_STATE2_SZ 32\n #define ICP_QAT_HW_MD5_STATE2_SZ 16\n@@ -191,6 +204,7 @@ struct icp_qat_hw_auth_setup {\n #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ\n #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24\n #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32\n+#define ICP_QAT_HW_ZUC_256_STATE2_SZ 56\n #define ICP_QAT_HW_GALOIS_H_SZ 16\n #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8\n #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16\n@@ -228,7 +242,8 @@ enum icp_qat_hw_cipher_algo {\n \tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,\n \tICP_QAT_HW_CIPHER_ALGO_SM4 = 10,\n \tICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = 11,\n-\tICP_QAT_HW_CIPHER_DELIMITER = 12\n+\tICP_QAT_HW_CIPHER_ALGO_ZUC_256 = 12,\n+\tICP_QAT_HW_CIPHER_DELIMITER = 13\n };\n \n enum icp_qat_hw_cipher_mode {\n@@ -308,6 +323,7 @@ enum icp_qat_hw_cipher_convert {\n #define ICP_QAT_HW_KASUMI_BLK_SZ 8\n #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8\n #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8\n+#define ICP_QAT_HW_ZUC_256_BLK_SZ 8\n #define ICP_QAT_HW_NULL_KEY_SZ 256\n #define ICP_QAT_HW_DES_KEY_SZ 8\n #define ICP_QAT_HW_3DES_KEY_SZ 24\n@@ -343,6 +359,8 @@ enum icp_qat_hw_cipher_convert {\n #define ICP_QAT_HW_SPC_CTR_SZ 16\n #define ICP_QAT_HW_CHACHAPOLY_ICV_SZ 16\n #define ICP_QAT_HW_CHACHAPOLY_AAD_MAX_LOG 14\n+#define ICP_QAT_HW_ZUC_256_KEY_SZ 32\n+#define ICP_QAT_HW_ZUC_256_IV_SZ 24\n \n #define ICP_QAT_HW_CIPHER_MAX_KEY_SZ ICP_QAT_HW_AES_256_F8_KEY_SZ\n \ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\nindex df47767749..62874039a9 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\n@@ -182,10 +182,8 @@ qat_sym_session_set_ext_hash_flags_gen2(struct qat_sym_session *session,\n \t\t\tsession->fw_req.cd_ctrl.content_desc_ctrl_lw;\n \n \t/* Set the Use Extended Protocol Flags bit in LW 1 */\n-\tQAT_FIELD_SET(header->comn_req_flags,\n-\t\t\tQAT_COMN_EXT_FLAGS_USED,\n-\t\t\tQAT_COMN_EXT_FLAGS_BITPOS,\n-\t\t\tQAT_COMN_EXT_FLAGS_MASK);\n+\tICP_QAT_FW_USE_EXTENDED_PROTOCOL_FLAGS_SET(\n+\t\t\theader->ext_flags, QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS);\n \n \t/* Set Hash Flags in LW 28 */\n \tcd_ctrl->hash_flags |= hash_flag;\n@@ -199,6 +197,7 @@ qat_sym_session_set_ext_hash_flags_gen2(struct qat_sym_session *session,\n \t\t\t\theader->serv_specif_flags, 0);\n \t\tbreak;\n \tcase ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3:\n+\tcase ICP_QAT_HW_CIPHER_ALGO_ZUC_256:\n \t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n \t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n \t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\nindex bc53e2e0f1..907c3ce3e2 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n@@ -204,6 +204,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,\n \tuint32_t legacy_size = sizeof(qat_sym_crypto_legacy_caps_gen3);\n \tcapa_num = size/sizeof(struct rte_cryptodev_capabilities);\n \tlegacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities);\n+\tstruct rte_cryptodev_capabilities *cap;\n \n \tif (unlikely(qat_legacy_capa))\n \t\tsize = size + legacy_size;\n@@ -255,6 +256,15 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,\n \t\t\t\tRTE_CRYPTO_AUTH_SM3_HMAC))) {\n \t\t\tcontinue;\n \t\t}\n+\n+\t\tif (slice_map & ICP_ACCEL_MASK_ZUC_256_SLICE && (\n+\t\t\tcheck_auth_capa(&capabilities[iter],\n+\t\t\t\tRTE_CRYPTO_AUTH_ZUC_EIA3) ||\n+\t\t\tcheck_cipher_capa(&capabilities[iter],\n+\t\t\t\tRTE_CRYPTO_CIPHER_ZUC_EEA3))) {\n+\t\t\tcontinue;\n+\t\t}\n+\n \t\tif (internals->qat_dev->has_wireless_slice && (\n \t\t\tcheck_auth_capa(&capabilities[iter],\n \t\t\t\tRTE_CRYPTO_AUTH_KASUMI_F9) ||\n@@ -268,6 +278,27 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,\n \n \t\tmemcpy(addr + curr_capa, capabilities + iter,\n \t\t\tsizeof(struct rte_cryptodev_capabilities));\n+\n+\t\tif (internals->qat_dev->has_wireless_slice && (\n+\t\t\tcheck_auth_capa(&capabilities[iter],\n+\t\t\t\tRTE_CRYPTO_AUTH_ZUC_EIA3))) {\n+\t\t\tcap = addr + curr_capa;\n+\t\t\tcap->sym.auth.key_size.max = 32;\n+\t\t\tcap->sym.auth.key_size.increment = 16;\n+\t\t\tcap->sym.auth.iv_size.max = 25;\n+\t\t\tcap->sym.auth.iv_size.increment = 1;\n+\t\t\tcap->sym.auth.digest_size.max = 16;\n+\t\t\tcap->sym.auth.digest_size.increment = 4;\n+\t\t}\n+\t\tif (internals->qat_dev->has_wireless_slice && (\n+\t\t\tcheck_cipher_capa(&capabilities[iter],\n+\t\t\t\tRTE_CRYPTO_CIPHER_ZUC_EEA3))) {\n+\t\t\tcap = addr + curr_capa;\n+\t\t\tcap->sym.cipher.key_size.max = 32;\n+\t\t\tcap->sym.cipher.key_size.increment = 16;\n+\t\t\tcap->sym.cipher.iv_size.max = 25;\n+\t\t\tcap->sym.cipher.iv_size.increment = 1;\n+\t\t}\n \t\tcurr_capa++;\n \t}\n \tinternals->qat_dev_capabilities = internals->capa_mz->addr;\n@@ -480,11 +511,14 @@ qat_sym_build_op_auth_gen3(void *in_op, struct qat_sym_session *ctx,\n }\n \n static int\n-qat_sym_crypto_set_session_gen3(void *cdev __rte_unused, void *session)\n+qat_sym_crypto_set_session_gen3(void *cdev, void *session)\n {\n \tstruct qat_sym_session *ctx = session;\n \tenum rte_proc_type_t proc_type = rte_eal_process_type();\n \tint ret;\n+\tstruct qat_cryptodev_private *internals;\n+\n+\tinternals = ((struct rte_cryptodev *)cdev)->data->dev_private;\n \n \tif (proc_type == RTE_PROC_AUTO || proc_type == RTE_PROC_INVALID)\n \t\treturn -EINVAL;\n@@ -517,6 +551,22 @@ qat_sym_crypto_set_session_gen3(void *cdev __rte_unused, void *session)\n \t\t\t\tctx->qat_cipher_alg ==\n \t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {\n \t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx, 0);\n+\t\t} else if ((internals->qat_dev->has_wireless_slice) &&\n+\t\t\t\t((ctx->aes_cmac ||\n+\t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) &&\n+\t\t\t\t(ctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n+\t\t\t\tctx->qat_cipher_alg ==\n+\t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 ||\n+\t\t\t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_256))) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx, 0);\n+\t\t} else if ((internals->qat_dev->has_wireless_slice) &&\n+\t\t\t(ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 ||\n+\t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64 ||\n+\t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128) &&\n+\t\t\t\tctx->qat_cipher_alg != ICP_QAT_HW_CIPHER_ALGO_ZUC_256) {\n+\t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx,\n+\t\t\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);\n \t\t}\n \n \t\tret = 0;\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\nindex 911400e53b..ff7ba55c01 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n@@ -117,7 +117,10 @@ qat_auth_is_len_in_bits(struct qat_sym_session *ctx,\n {\n \tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||\n \t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||\n-\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {\n+\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 ||\n+\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 ||\n+\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64 ||\n+\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128) {\n \t\tif (unlikely((op->sym->auth.data.offset % BYTE_LENGTH != 0) ||\n \t\t\t\t(op->sym->auth.data.length % BYTE_LENGTH != 0)))\n \t\t\treturn -EINVAL;\n@@ -132,7 +135,8 @@ qat_cipher_is_len_in_bits(struct qat_sym_session *ctx,\n {\n \tif (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n \t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||\n-\t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n+\t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 ||\n+\t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_256)  {\n \t\tif (unlikely((op->sym->cipher.data.length % BYTE_LENGTH != 0) ||\n \t\t\t((op->sym->cipher.data.offset %\n \t\t\tBYTE_LENGTH) != 0)))\n@@ -589,6 +593,26 @@ qat_sym_convert_op_to_vec_aead(struct rte_crypto_op *op,\n \treturn 0;\n }\n \n+static inline void\n+zuc256_modify_iv(uint8_t *iv)\n+{\n+\tuint8_t iv_tmp[8];\n+\n+\tiv_tmp[0] = iv[16];\n+\t/* pack the last 8 bytes of IV to 6 bytes.\n+\t * discard the 2 MSB bits of each byte\n+\t */\n+\tiv_tmp[1] = (((iv[17] & 0x3f) << 2) | ((iv[18] >> 4) & 0x3));\n+\tiv_tmp[2] = (((iv[18] & 0xf) << 4) | ((iv[19] >> 2) & 0xf));\n+\tiv_tmp[3] = (((iv[19] & 0x3) << 6) | (iv[20] & 0x3f));\n+\n+\tiv_tmp[4] = (((iv[21] & 0x3f) << 2) | ((iv[22] >> 4) & 0x3));\n+\tiv_tmp[5] = (((iv[22] & 0xf) << 4) | ((iv[23] >> 2) & 0xf));\n+\tiv_tmp[6] = (((iv[23] & 0x3) << 6) | (iv[24] & 0x3f));\n+\n+\tmemcpy(iv + 16, iv_tmp, 8);\n+}\n+\n static __rte_always_inline void\n qat_set_cipher_iv(struct icp_qat_fw_la_cipher_req_params *cipher_param,\n \t\tstruct rte_crypto_va_iova_ptr *iv_ptr, uint32_t iv_len,\n@@ -665,6 +689,9 @@ enqueue_one_auth_job_gen1(struct qat_sym_session *ctx,\n \tcase ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:\n \tcase ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:\n \tcase ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128:\n \t\tauth_param->u1.aad_adr = auth_iv->iova;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n@@ -747,6 +774,9 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx,\n \tcase ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:\n \tcase ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:\n \tcase ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128:\n \t\tauth_param->u1.aad_adr = auth_iv->iova;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\ndiff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\nindex 208b7e0ba6..bdd1647ea2 100644\n--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n@@ -248,6 +248,9 @@ qat_sym_build_op_cipher_gen1(void *in_op, struct qat_sym_session *ctx,\n \t\treturn -EINVAL;\n \t}\n \n+\tif (ctx->is_zuc256)\n+\t\tzuc256_modify_iv(cipher_iv.va);\n+\n \tenqueue_one_cipher_job_gen1(ctx, req, &cipher_iv, ofs, total_len, op_cookie);\n \n \tqat_sym_debug_log_dump(req, ctx, in_sgl.vec, in_sgl.num, &cipher_iv,\n@@ -270,6 +273,8 @@ qat_sym_build_op_auth_gen1(void *in_op, struct qat_sym_session *ctx,\n \tstruct rte_crypto_va_iova_ptr digest;\n \tunion rte_crypto_sym_ofs ofs;\n \tint32_t total_len;\n+\tstruct rte_cryptodev *cdev;\n+\tstruct qat_cryptodev_private *internals;\n \n \tin_sgl.vec = in_vec;\n \tout_sgl.vec = out_vec;\n@@ -284,6 +289,13 @@ qat_sym_build_op_auth_gen1(void *in_op, struct qat_sym_session *ctx,\n \t\treturn -EINVAL;\n \t}\n \n+\tcdev = rte_cryptodev_pmd_get_dev(ctx->dev_id);\n+\tinternals = cdev->data->dev_private;\n+\n+\tif (internals->qat_dev->has_wireless_slice && !ctx->is_gmac)\n+\t\tICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(\n+\t\t\t\treq->comn_hdr.serv_specif_flags, 0);\n+\n \ttotal_len = qat_sym_build_req_set_data(req, in_op, cookie,\n \t\t\tin_sgl.vec, in_sgl.num, out_sgl.vec, out_sgl.num);\n \tif (unlikely(total_len < 0)) {\n@@ -291,6 +303,9 @@ qat_sym_build_op_auth_gen1(void *in_op, struct qat_sym_session *ctx,\n \t\treturn -EINVAL;\n \t}\n \n+\tif (ctx->is_zuc256)\n+\t\tzuc256_modify_iv(auth_iv.va);\n+\n \tenqueue_one_auth_job_gen1(ctx, req, &digest, &auth_iv, ofs,\n \t\t\ttotal_len);\n \n@@ -381,6 +396,11 @@ qat_sym_build_op_chain_gen1(void *in_op, struct qat_sym_session *ctx,\n \t\treturn -EINVAL;\n \t}\n \n+\tif (ctx->is_zuc256) {\n+\t\tzuc256_modify_iv(cipher_iv.va);\n+\t\tzuc256_modify_iv(auth_iv.va);\n+\t}\n+\n \tenqueue_one_chain_job_gen1(ctx, req, in_sgl.vec, in_sgl.num,\n \t\t\tout_sgl.vec, out_sgl.num, &cipher_iv, &digest, &auth_iv,\n \t\t\tofs, total_len, cookie);\n@@ -507,6 +527,9 @@ qat_sym_dp_enqueue_single_cipher_gen1(void *qp_data, uint8_t *drv_ctx,\n \tif (unlikely(data_len < 0))\n \t\treturn -1;\n \n+\tif (ctx->is_zuc256)\n+\t\tzuc256_modify_iv(iv->va);\n+\n \tenqueue_one_cipher_job_gen1(ctx, req, iv, ofs, (uint32_t)data_len, cookie);\n \n \tqat_sym_debug_log_dump(req, ctx, data, n_data_vecs, iv,\n@@ -563,6 +586,10 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t *drv_ctx,\n \n \t\tif (unlikely(data_len < 0))\n \t\t\tbreak;\n+\n+\t\tif (ctx->is_zuc256)\n+\t\t\tzuc256_modify_iv(vec->iv[i].va);\n+\n \t\tenqueue_one_cipher_job_gen1(ctx, req, &vec->iv[i], ofs,\n \t\t\t(uint32_t)data_len, cookie);\n \t\ttail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;\n@@ -613,6 +640,9 @@ qat_sym_dp_enqueue_single_auth_gen1(void *qp_data, uint8_t *drv_ctx,\n \tif (unlikely(data_len < 0))\n \t\treturn -1;\n \n+\tif (ctx->is_zuc256)\n+\t\tzuc256_modify_iv(auth_iv->va);\n+\n \tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {\n \t\tnull_digest.iova = cookie->digest_null_phys_addr;\n \t\tjob_digest = &null_digest;\n@@ -678,6 +708,9 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx,\n \t\tif (unlikely(data_len < 0))\n \t\t\tbreak;\n \n+\t\tif (ctx->is_zuc256)\n+\t\t\tzuc256_modify_iv(vec->auth_iv[i].va);\n+\n \t\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {\n \t\t\tnull_digest.iova = cookie->digest_null_phys_addr;\n \t\t\tjob_digest = &null_digest;\n@@ -733,6 +766,11 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx,\n \tif (unlikely(data_len < 0))\n \t\treturn -1;\n \n+\tif (ctx->is_zuc256) {\n+\t\tzuc256_modify_iv(cipher_iv->va);\n+\t\tzuc256_modify_iv(auth_iv->va);\n+\t}\n+\n \tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {\n \t\tnull_digest.iova = cookie->digest_null_phys_addr;\n \t\tjob_digest = &null_digest;\n@@ -801,6 +839,11 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,\n \t\tif (unlikely(data_len < 0))\n \t\t\tbreak;\n \n+\t\tif (ctx->is_zuc256) {\n+\t\t\tzuc256_modify_iv(vec->iv[i].va);\n+\t\t\tzuc256_modify_iv(vec->auth_iv[i].va);\n+\t\t}\n+\n \t\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {\n \t\t\tnull_digest.iova = cookie->digest_null_phys_addr;\n \t\t\tjob_digest = &null_digest;\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 9f4f6c3d93..ebdad0bd67 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -379,7 +379,9 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n \tstruct rte_crypto_cipher_xform *cipher_xform = NULL;\n \tenum qat_device_gen qat_dev_gen =\n \t\t\t\tinternals->qat_dev->qat_dev_gen;\n-\tint ret;\n+\tint ret, is_wireless = 0;\n+\tstruct icp_qat_fw_la_bulk_req *req_tmpl = &session->fw_req;\n+\tstruct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;\n \n \t/* Get cipher xform from crypto xform chain */\n \tcipher_xform = qat_get_cipher_xform(xform);\n@@ -416,6 +418,8 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n \t\t\tgoto error_out;\n \t\t}\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n+\t\tif (internals->qat_dev->has_wireless_slice)\n+\t\t\tis_wireless = 1;\n \t\tbreak;\n \tcase RTE_CRYPTO_CIPHER_NULL:\n \t\tsession->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_NULL;\n@@ -533,6 +537,10 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n \t\t\tgoto error_out;\n \t\t}\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n+\t\tif (cipher_xform->key.length == ICP_QAT_HW_ZUC_256_KEY_SZ)\n+\t\t\tsession->is_zuc256 = 1;\n+\t\tif (internals->qat_dev->has_wireless_slice)\n+\t\t\tis_wireless = 1;\n \t\tbreak;\n \tcase RTE_CRYPTO_CIPHER_AES_XTS:\n \t\tif ((cipher_xform->key.length/2) == ICP_QAT_HW_AES_192_KEY_SZ) {\n@@ -587,6 +595,17 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n \t\tgoto error_out;\n \t}\n \n+\tif (is_wireless) {\n+\t\t/* Set the Use Extended Protocol Flags bit in LW 1 */\n+\t\tICP_QAT_FW_USE_EXTENDED_PROTOCOL_FLAGS_SET(\n+\t\t\t\theader->ext_flags,\n+\t\t\t\tQAT_LA_USE_EXTENDED_PROTOCOL_FLAGS);\n+\t\t/* Force usage of Wireless Cipher slice */\n+\t\tICP_QAT_FW_USE_WCP_SLICE_SET(header->ext_flags,\n+\t\t\t\tQAT_LA_USE_WCP_SLICE);\n+\t\tsession->is_wireless = 1;\n+\t}\n+\n \treturn 0;\n \n error_out:\n@@ -820,9 +839,16 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \tstruct rte_crypto_auth_xform *auth_xform = qat_get_auth_xform(xform);\n \tstruct qat_cryptodev_private *internals = dev->data->dev_private;\n \tconst uint8_t *key_data = auth_xform->key.data;\n-\tuint8_t key_length = auth_xform->key.length;\n+\tuint16_t key_length = auth_xform->key.length;\n \tenum qat_device_gen qat_dev_gen =\n \t\t\tinternals->qat_dev->qat_dev_gen;\n+\tstruct icp_qat_fw_la_bulk_req *req_tmpl = &session->fw_req;\n+\tstruct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;\n+\tstruct icp_qat_fw_cipher_auth_cd_ctrl_hdr *cd_ctrl =\n+\t\t\t(struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *)\n+\t\t\tsession->fw_req.cd_ctrl.content_desc_ctrl_lw;\n+\tuint8_t hash_flag = 0;\n+\tint is_wireless = 0;\n \n \tsession->aes_cmac = 0;\n \tsession->auth_key_length = auth_xform->key.length;\n@@ -898,6 +924,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \tcase RTE_CRYPTO_AUTH_AES_CMAC:\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;\n \t\tsession->aes_cmac = 1;\n+\t\tif (internals->qat_dev->has_wireless_slice) {\n+\t\t\tis_wireless = 1;\n+\t\t\tsession->is_wireless = 1;\n+\t\t}\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_AES_GMAC:\n \t\tif (qat_sym_validate_aes_key(auth_xform->key.length,\n@@ -918,6 +948,11 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SNOW3G_UIA2:\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;\n+\t\tif (internals->qat_dev->has_wireless_slice) {\n+\t\t\tis_wireless = 1;\n+\t\t\tsession->is_wireless = 1;\n+\t\t\thash_flag = 1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS;\n+\t\t}\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;\n@@ -934,7 +969,35 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\t\trte_cryptodev_get_auth_algo_string(auth_xform->algo));\n \t\t\treturn -ENOTSUP;\n \t\t}\n-\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;\n+\t\tif (key_length == ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ)\n+\t\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;\n+\t\telse if (key_length == ICP_QAT_HW_ZUC_256_KEY_SZ) {\n+\t\t\tswitch (auth_xform->digest_length) {\n+\t\t\tcase 4:\n+\t\t\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32;\n+\t\t\t\tbreak;\n+\t\t\tcase 8:\n+\t\t\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64;\n+\t\t\t\tbreak;\n+\t\t\tcase 16:\n+\t\t\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tQAT_LOG(ERR, \"Invalid digest length: %d\",\n+\t\t\t\t\t\tauth_xform->digest_length);\n+\t\t\t\treturn -ENOTSUP;\n+\t\t\t}\n+\t\t\tsession->is_zuc256 = 1;\n+\t\t} else {\n+\t\t\tQAT_LOG(ERR, \"Invalid key length: %d\", key_length);\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\t\tif (internals->qat_dev->has_wireless_slice) {\n+\t\t\tis_wireless = 1;\n+\t\t\tsession->is_wireless = 1;\n+\t\t\thash_flag = 1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS;\n+\t\t} else\n+\t\t\tsession->auth_mode = ICP_QAT_HW_AUTH_MODE0;\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_MD5:\n \tcase RTE_CRYPTO_AUTH_AES_CBC_MAC:\n@@ -1002,6 +1065,21 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\treturn -EINVAL;\n \t}\n \n+\tif (is_wireless) {\n+\t\tif (!session->aes_cmac) {\n+\t\t\t/* Set the Use Extended Protocol Flags bit in LW 1 */\n+\t\t\tICP_QAT_FW_USE_EXTENDED_PROTOCOL_FLAGS_SET(\n+\t\t\t\t\theader->ext_flags,\n+\t\t\t\t\tQAT_LA_USE_EXTENDED_PROTOCOL_FLAGS);\n+\n+\t\t\t/* Set Hash Flags in LW 28 */\n+\t\t\tcd_ctrl->hash_flags |= hash_flag;\n+\t\t}\n+\t\t/* Force usage of Wireless Auth slice */\n+\t\tICP_QAT_FW_USE_WAT_SLICE_SET(header->ext_flags,\n+\t\t\t\tQAT_LA_USE_WAT_SLICE);\n+\t}\n+\n \treturn 0;\n }\n \n@@ -1204,6 +1282,15 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)\n \tcase ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:\n \t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ,\n \t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_ZUC_256_MAC_32_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_ZUC_256_MAC_64_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_ZUC_256_MAC_128_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n \tcase ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:\n \t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ,\n \t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n@@ -1286,6 +1373,10 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)\n \t\treturn ICP_QAT_HW_AES_BLK_SZ;\n \tcase ICP_QAT_HW_AUTH_ALGO_MD5:\n \t\treturn QAT_MD5_CBLOCK;\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128:\n+\t\treturn ICP_QAT_HW_ZUC_256_BLK_SZ;\n \tcase ICP_QAT_HW_AUTH_ALGO_DELIMITER:\n \t\t/* return maximum block size in this case */\n \t\treturn QAT_SHA512_CBLOCK;\n@@ -2040,7 +2131,8 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \t\tkey_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;\n \t} else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2\n \t\t|| cdesc->qat_cipher_alg ==\n-\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3\n+\t\t\t|| cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_256) {\n \t\tkey_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;\n \t\tcdesc->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n \t} else if (cdesc->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT)\n@@ -2075,6 +2167,17 @@ int qat_sym_cd_cipher_set(struct qat_sym_session *cdesc,\n \t\tcipher_cd_ctrl->cipher_state_sz =\n \t\t\tICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;\n \t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n+\t} else if (cdesc->qat_cipher_alg ==\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_256) {\n+\t\tif (cdesc->cipher_iv.length != 23 && cdesc->cipher_iv.length != 25) {\n+\t\t\tQAT_LOG(ERR, \"Invalid IV length for ZUC256, must be 23 or 25.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\ttotal_key_size = ICP_QAT_HW_ZUC_256_KEY_SZ +\n+\t\t\tICP_QAT_HW_ZUC_256_IV_SZ;\n+\t\tcipher_cd_ctrl->cipher_state_sz =\n+\t\t\tICP_QAT_HW_ZUC_256_IV_SZ >> 3;\n+\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n \t} else {\n \t\ttotal_key_size = cipherkeylen;\n \t\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;\n@@ -2246,6 +2349,9 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3\n+\t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32\n+\t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64\n+\t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC\n \t\t|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL\n@@ -2519,7 +2625,8 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\tcdesc->aad_len = aad_length;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:\n-\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;\n+\t\tif (!cdesc->is_wireless)\n+\t\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;\n \t\tstate1_size = qat_hash_get_state1_size(\n \t\t\t\tICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2);\n \t\tstate2_size = ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ;\n@@ -2540,10 +2647,12 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\tauth_param->hash_state_sz = ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:\n-\t\thash->auth_config.config =\n-\t\t\tICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE0,\n-\t\t\t\tcdesc->qat_hash_alg, digestsize);\n-\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n+\t\tif (!cdesc->is_wireless) {\n+\t\t\thash->auth_config.config =\n+\t\t\t\tICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE0,\n+\t\t\t\t\tcdesc->qat_hash_alg, digestsize);\n+\t\t\tcdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;\n+\t\t}\n \t\tstate1_size = qat_hash_get_state1_size(\n \t\t\t\tICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3);\n \t\tstate2_size = ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ;\n@@ -2554,6 +2663,18 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,\n \t\tcd_extra_size += ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;\n \t\tauth_param->hash_state_sz = ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;\n \n+\t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64:\n+\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128:\n+\t\tstate1_size = qat_hash_get_state1_size(cdesc->qat_hash_alg);\n+\t\tstate2_size = ICP_QAT_HW_ZUC_256_STATE2_SZ;\n+\t\tmemset(cdesc->cd_cur_ptr, 0, state1_size + state2_size\n+\t\t\t+ ICP_QAT_HW_ZUC_256_IV_SZ);\n+\n+\t\tmemcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);\n+\t\tcd_extra_size += ICP_QAT_HW_ZUC_256_IV_SZ;\n+\t\tauth_param->hash_state_sz = ICP_QAT_HW_ZUC_256_IV_SZ >> 3;\n \t\tbreak;\n \tcase ICP_QAT_HW_AUTH_ALGO_MD5:\n #ifdef RTE_QAT_OPENSSL\n@@ -2740,6 +2861,9 @@ int qat_sym_validate_zuc_key(int key_len, enum icp_qat_hw_cipher_algo *alg)\n \tcase ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ:\n \t\t*alg = ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3;\n \t\tbreak;\n+\tcase ICP_QAT_HW_ZUC_256_KEY_SZ:\n+\t\t*alg = ICP_QAT_HW_CIPHER_ALGO_ZUC_256;\n+\t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex 9209e2e8df..2e25c90342 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -140,6 +140,8 @@ struct qat_sym_session {\n \tuint8_t is_auth;\n \tuint8_t is_cnt_zero;\n \t/* Some generations need different setup of counter */\n+\tuint8_t is_zuc256;\n+\tuint8_t is_wireless;\n \tuint32_t slice_types;\n \tenum qat_sym_proto_flag qat_proto_flag;\n \tqat_sym_build_request_t build_request[2];\n",
    "prefixes": [
        "v2",
        "2/4"
    ]
}