Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/136927/?format=api
{ "id": 136927, "url": "http://patches.dpdk.org/api/patches/136927/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240220141008.292641-4-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240220141008.292641-4-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240220141008.292641-4-bingz@nvidia.com", "date": "2024-02-20T14:10:06", "name": "[v2,3/5] net/mlx5: create NAT64 actions during configuration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "66545641c956b64fd5eb44d72e9a89c08e3cae4f", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240220141008.292641-4-bingz@nvidia.com/mbox/", "series": [ { "id": 31154, "url": "http://patches.dpdk.org/api/series/31154/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31154", "date": "2024-02-20T14:10:03", "name": "NAT64 support in mlx5 PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/31154/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136927/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/136927/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DBF6843B54;\n\tTue, 20 Feb 2024 15:11:15 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2673040A7F;\n\tTue, 20 Feb 2024 15:11:11 +0100 (CET)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2069.outbound.protection.outlook.com [40.107.94.69])\n by mails.dpdk.org (Postfix) with ESMTP id 7BB73406BC\n for <dev@dpdk.org>; Tue, 20 Feb 2024 15:11:08 +0100 (CET)", "from SJ0P220CA0023.NAMP220.PROD.OUTLOOK.COM (2603:10b6:a03:41b::21)\n by MN2PR12MB4408.namprd12.prod.outlook.com (2603:10b6:208:26c::14)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.20; Tue, 20 Feb\n 2024 14:11:04 +0000", "from SJ5PEPF000001C9.namprd05.prod.outlook.com\n (2603:10b6:a03:41b:cafe::86) by SJ0P220CA0023.outlook.office365.com\n (2603:10b6:a03:41b::21) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.37 via Frontend\n Transport; Tue, 20 Feb 2024 14:11:04 +0000", "from mail.nvidia.com (216.228.117.160) by\n SJ5PEPF000001C9.mail.protection.outlook.com (10.167.242.37) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7292.25 via Frontend Transport; Tue, 20 Feb 2024 14:11:04 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 20 Feb\n 2024 06:10:49 -0800", "from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 20 Feb\n 2024 06:10:46 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=cKPd53PKEcw/lSaJt/Qc77A7HHELSJL7M2b1Hw2/OQeOiLUAapFHDCfNG5U37NBL9u2ZTiPt9+oIno9DkwPY94/UNLkXL4E7aW5kByjovDtmiGF5kX0jamqCtI5b74rAK0n6dCVRkwpwXu5esbqCYMlx9K3/9ApsddlH1Ehdr37wowizEZF78PNwNOcTcr9a1J0afxULgpldrxR2CVzsTiCQaH2yFkO4Xq6yVNycBuzjMwJ7QHB5HYiddvTNq9d59dnW0MZCXB2LvNMfvI4vHFXxttIWRdtwqkSz+Wviv7BU4k6dKIWiwIX9WcVbxo4tz89oIpAqxpPM95B8+a3jfQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=ArsroM3B70LfNgJsR7i2TvObxTbf903PHVdEu6R6b3U=;\n b=iOTY04fQ1jtTRsEnfbruGAkTP2/gQf8kRXt3F7/IxamjU6yp+NEZnJQiT/FTapRvx2e7i1iqML5cUnf2a3/wmtb5K3CbxT9DCTTmaq+yEiKts7SXEZjcBroHm+40SKUcUUGKsjQhrf4da34aBTBiPbsJseTQGzKEWuWbdReqYV2gvl5ZE6sNZuS1YsGJ82u+xydlLWIFABx8hBfQycXUnIKFF2IQp1UrNRcLFxVcER6WpimBoTZv5uibPt3P4ssacxJBwDcCmShgvnbO7KPXBTXWrx4hVhHiq/qPS8f8Q+FQkZNQShGaf8vMkTCA5g7eScayIy2Y3D8dk5hJMzJq9Q==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=ArsroM3B70LfNgJsR7i2TvObxTbf903PHVdEu6R6b3U=;\n b=V7C8GAERo2E3rfzl+wGQig95A+2ncHvfXbITEpeyYyDlut+few8bi5qE7yQQ3fHWGCvamzWJL6q+jSMp+T/ha094fPKT7lUT6kSaBzADWW6SENmI9xNdmA9PBA2y1TEA4gdERwXfAzLUbKztSkBr2Dvy5OFK1O1rEKxCwABviEQNehKJuWQIloLaVXcyQfT/AhpyLu10q+tbNmhLXJYcURKQk+6J83O65VTeXhUdOdTLATtAz3Zoz0oQWqXPqAAOAsaW1GGAm+YS8MqKZKHoTFzLC0pMTY78t+7hf6NZ4stES42LSFWRPyQNkjuXJwOoIP+c6I6D2lkxikW4EN1eeQ==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<orika@nvidia.com>, <aman.deep.singh@intel.com>, <dsosnowski@nvidia.com>,\n <viacheslavo@nvidia.com>, <suanmingm@nvidia.com>, <matan@nvidia.com>,\n <thomas@monjalon.net>, <ferruh.yigit@amd.com>,\n <andrew.rybchenko@oktetlabs.ru>, <dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v2 3/5] net/mlx5: create NAT64 actions during configuration", "Date": "Tue, 20 Feb 2024 16:10:06 +0200", "Message-ID": "<20240220141008.292641-4-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240220141008.292641-1-bingz@nvidia.com>", "References": "<20231227090731.2569427-1-bingz@nvidia.com>\n <20240220141008.292641-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ5PEPF000001C9:EE_|MN2PR12MB4408:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4d6a108c-bb16-4c0f-a4d6-08dc321dc6a2", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 2hEQN4dssfXjv5AWucG1o7+9e8elCwFFf7n1MbcPqlx+zsOH7FzvnZK22wBwtwr2RRUTF5fW40Ej1Gw6LaecKCOgkFKGDiXGmK+0KmvBpna07yefFcnoSNp3SVe0B06gVFNF5rrRL4y+edi1LeCuVUQgAr8Qj3QFAArqhzuzmR0OQ/PS1m4ESOrqVpvjmHJJmtggyV2H6sFtueUbz1GCdvmhq0joVRTfnc6Aqlq2OCxnL36m9mVt4jSxIbs4Ah63c6H/wqXZbr+shRUpKVYApYMnxEUYwhi/k5W7APEqvNfsYhVNUGqlrlA8f7oKxlBqP/DtCGveRia0zPmQIQX6hmW2NXy+KWBvy/6bXK6NQ3ydzE/VKOsKTt6w1oWT2qNEqmBgd5XV5W0I80AfW5avyvLIAc+iOy4GjC1kwMYNdHk+h/er1UdMODdA3NA9Y42IDnelZrbw8kX0bDBiI82Ma9p8rszGnYl4MifhmYmUasezAZJBpIWjVUB4zUmA4utNi8LN8yaHdTyLwl5v4C0zxBgpKsqsFJe51Ri3W3TzYkFI/Cc11Kih92kJZuSvFx0T+TABmFBTgCIHJfuBhRgBo7PZiw2TlDd10aJbr4JR7AEoDOA/BRZOWcu6vatVDoKQ/4Ple+6ht2wAju2ml/C0a89S6T3mu8Vfo/6PFhPfxLGiyK1yesZhqTvkrW1ZgCnp", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(230273577357003)(36860700004)(40470700004)(46966006)(921011);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Feb 2024 14:11:04.6506 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4d6a108c-bb16-4c0f-a4d6-08dc321dc6a2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SJ5PEPF000001C9.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4408", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The NAT64 DR actions can be shared among the tables. All these\nactions can be created during configuring the flow queues and saved\nfor the future usage.\n\nEven the actions can be shared now, inside per each flow rule, the\nactual hardware resources are unique.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n doc/guides/nics/features/mlx5.ini | 1 +\n doc/guides/nics/mlx5.rst | 10 ++++\n doc/guides/rel_notes/release_24_03.rst | 7 +++\n drivers/net/mlx5/mlx5.h | 6 +++\n drivers/net/mlx5/mlx5_flow.h | 11 +++++\n drivers/net/mlx5/mlx5_flow_dv.c | 4 +-\n drivers/net/mlx5/mlx5_flow_hw.c | 65 ++++++++++++++++++++++++++\n 7 files changed, 103 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini\nindex 30027f2ba1..81a7067cc3 100644\n--- a/doc/guides/nics/features/mlx5.ini\n+++ b/doc/guides/nics/features/mlx5.ini\n@@ -117,6 +117,7 @@ mark = Y\n meter = Y\n meter_mark = Y\n modify_field = Y\n+nat64 = Y\n nvgre_decap = Y\n nvgre_encap = Y\n of_pop_vlan = Y\ndiff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex fa013b03bb..248e4e41fa 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -168,6 +168,7 @@ Features\n - Matching on represented port.\n - Matching on aggregated affinity.\n - Matching on random value.\n+- NAT64.\n \n \n Limitations\n@@ -824,6 +825,15 @@ Limitations\n - Only match with compare result between packet fields is supported.\n \n \n+- NAT64 action:\n+ - Supported only with HW Steering enabled (``dv_flow_en`` = 2).\n+ - FW version: at least ``XX.39.1002``.\n+ - Supported only on non-root table.\n+ - Actions order limitation should follow the modify fields action.\n+ - The last 2 TAG registers will be used implicitly in address backup mode.\n+ - Even if the action can be shared, new steering entries will be created per flow rule. It is recommended a single rule with NAT64 should be shared to reduce the duplication of entries. The default address and other fields covertion will be handled with NAT64 action. To support other address, new rule(s) with modify fields on the IP addresses should be created.\n+ - TOS / Traffic Class is not supported now.\n+\n Statistics\n ----------\n \ndiff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 619459baae..492c77ff4f 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -102,6 +102,11 @@ New Features\n * ``rte_flow_template_table_resize_complete()``.\n Complete table resize.\n \n+* **Added a flow action type for NAT64.**\n+\n+ Added ``RTE_FLOW_ACTION_TYPE_NAT64`` to support offloading of header conversion\n+ between IPv4 and IPv6.\n+\n * **Updated Atomic Rules' Arkville PMD.**\n \n * Added support for Atomic Rules' TK242 packet-capture family of devices\n@@ -133,6 +138,8 @@ New Features\n * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SEQ_NUM`` flow action.\n * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_PROTO`` flow action.\n \n+ * Added support for ``RTE_FLOW_ACTION_TYPE_NAT64`` flow action in HW Steering flow engine.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 544cf35069..1ad40e38e1 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1986,6 +1986,12 @@ struct mlx5_priv {\n \tstruct mlx5_aso_mtr_pool *hws_mpool; /* HW steering's Meter pool. */\n \tstruct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;\n \t/**< HW steering templates used to create control flow rules. */\n+\t/*\n+\t * The NAT64 action can be shared among matchers per domain.\n+\t * [0]: RTE_FLOW_NAT64_6TO4, [1]: RTE_FLOW_NAT64_4TO6\n+\t * Todo: consider to add *_MAX macro.\n+\t */\n+\tstruct mlx5dr_action *action_nat64[MLX5DR_TABLE_TYPE_MAX][2];\n #endif\n \tstruct rte_eth_dev *shared_host; /* Host device for HW steering. */\n \tuint16_t shared_refcnt; /* HW steering host reference counter. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex a4d0ff7b13..da13f1f210 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -159,6 +159,17 @@ struct mlx5_rte_flow_item_sq {\n \tuint32_t queue; /* DevX SQ number */\n };\n \n+/* Map from registers to modify fields. */\n+extern enum mlx5_modification_field reg_to_field[];\n+extern const size_t mlx5_mod_reg_size;\n+\n+static __rte_always_inline enum mlx5_modification_field\n+mlx5_covert_reg_to_field(enum modify_reg reg)\n+{\n+\tMLX5_ASSERT((size_t)reg < mlx5_mod_reg_size);\n+\treturn reg_to_field[reg];\n+}\n+\n /* Feature name to allocate metadata register. */\n enum mlx5_feature_name {\n \tMLX5_HAIRPIN_RX,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 6fded15d91..17c405508d 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -968,7 +968,7 @@ flow_dv_convert_action_modify_tcp_ack\n \t\t\t\t\t MLX5_MODIFICATION_TYPE_ADD, error);\n }\n \n-static enum mlx5_modification_field reg_to_field[] = {\n+enum mlx5_modification_field reg_to_field[] = {\n \t[REG_NON] = MLX5_MODI_OUT_NONE,\n \t[REG_A] = MLX5_MODI_META_DATA_REG_A,\n \t[REG_B] = MLX5_MODI_META_DATA_REG_B,\n@@ -986,6 +986,8 @@ static enum mlx5_modification_field reg_to_field[] = {\n \t[REG_C_11] = MLX5_MODI_META_REG_C_11,\n };\n \n+const size_t mlx5_mod_reg_size = RTE_DIM(reg_to_field);\n+\n /**\n * Convert register set to DV specification.\n *\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 3bb3a9a178..f53df40041 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -7606,6 +7606,66 @@ flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)\n \t}\n }\n \n+static void\n+flow_hw_destroy_nat64_actions(struct mlx5_priv *priv)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {\n+\t\tif (priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]) {\n+\t\t\t(void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]);\n+\t\t\tpriv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = NULL;\n+\t\t}\n+\t\tif (priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]) {\n+\t\t\t(void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]);\n+\t\t\tpriv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = NULL;\n+\t\t}\n+\t}\n+}\n+\n+static int\n+flow_hw_create_nat64_actions(struct mlx5_priv *priv, struct rte_flow_error *error)\n+{\n+\tstruct mlx5dr_action_nat64_attr attr;\n+\tuint8_t regs[MLX5_FLOW_NAT64_REGS_MAX];\n+\tuint32_t i;\n+\tconst uint32_t flags[MLX5DR_TABLE_TYPE_MAX] = {\n+\t\tMLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_SHARED,\n+\t\tMLX5DR_ACTION_FLAG_HWS_TX | MLX5DR_ACTION_FLAG_SHARED,\n+\t\tMLX5DR_ACTION_FLAG_HWS_FDB | MLX5DR_ACTION_FLAG_SHARED,\n+\t};\n+\tstruct mlx5dr_action *act;\n+\n+\tattr.registers = regs;\n+\t/* Try to use 3 registers by default. */\n+\tattr.num_of_registers = MLX5_FLOW_NAT64_REGS_MAX;\n+\tfor (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; i++) {\n+\t\tMLX5_ASSERT(priv->sh->registers.nat64_regs[i] != REG_NON);\n+\t\tregs[i] = mlx5_covert_reg_to_field(priv->sh->registers.nat64_regs[i]);\n+\t}\n+\tfor (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) {\n+\t\tif (i == MLX5DR_TABLE_TYPE_FDB && !priv->sh->config.dv_esw_en)\n+\t\t\tcontinue;\n+\t\tattr.flags = (enum mlx5dr_action_nat64_flags)\n+\t\t\t (MLX5DR_ACTION_NAT64_V6_TO_V4 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);\n+\t\tact = mlx5dr_action_create_nat64(priv->dr_ctx, &attr, flags[i]);\n+\t\tif (!act)\n+\t\t\treturn rte_flow_error_set(error, rte_errno,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\t\t \"Failed to create v6 to v4 action.\");\n+\t\tpriv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = act;\n+\t\tattr.flags = (enum mlx5dr_action_nat64_flags)\n+\t\t\t (MLX5DR_ACTION_NAT64_V4_TO_V6 | MLX5DR_ACTION_NAT64_BACKUP_ADDR);\n+\t\tact = mlx5dr_action_create_nat64(priv->dr_ctx, &attr, flags[i]);\n+\t\tif (!act)\n+\t\t\treturn rte_flow_error_set(error, rte_errno,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\t\t \"Failed to create v4 to v6 action.\");\n+\t\tpriv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = act;\n+\t}\n+\treturn 0;\n+}\n+\n /**\n * Create an egress pattern template matching on source SQ.\n *\n@@ -9732,6 +9792,9 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\t\t NULL, \"Failed to VLAN actions.\");\n \t\tgoto err;\n \t}\n+\tif (flow_hw_create_nat64_actions(priv, error))\n+\t\tDRV_LOG(WARNING, \"Cannot create NAT64 action on port %u, \"\n+\t\t\t\"please check the FW version\", dev->data->port_id);\n \tif (_queue_attr)\n \t\tmlx5_free(_queue_attr);\n \tif (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE)\n@@ -9764,6 +9827,7 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t}\n \tif (priv->hw_def_miss)\n \t\tmlx5dr_action_destroy(priv->hw_def_miss);\n+\tflow_hw_destroy_nat64_actions(priv);\n \tflow_hw_destroy_vlan(dev);\n \tif (dr_ctx)\n \t\tclaim_zero(mlx5dr_context_close(dr_ctx));\n@@ -9844,6 +9908,7 @@ flow_hw_resource_release(struct rte_eth_dev *dev)\n \t}\n \tif (priv->hw_def_miss)\n \t\tmlx5dr_action_destroy(priv->hw_def_miss);\n+\tflow_hw_destroy_nat64_actions(priv);\n \tflow_hw_destroy_vlan(dev);\n \tflow_hw_destroy_send_to_kernel_action(priv);\n \tflow_hw_free_vport_actions(priv);\n", "prefixes": [ "v2", "3/5" ] }