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GET /api/patches/136926/?format=api
{ "id": 136926, "url": "http://patches.dpdk.org/api/patches/136926/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240220141008.292641-3-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240220141008.292641-3-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240220141008.292641-3-bingz@nvidia.com", "date": "2024-02-20T14:10:05", "name": "[v2,2/5] net/mlx5: fetch the available registers for NAT64", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c37565ee85c02e10f40575cb843752cf601fa7df", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240220141008.292641-3-bingz@nvidia.com/mbox/", "series": [ { "id": 31154, "url": "http://patches.dpdk.org/api/series/31154/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31154", "date": "2024-02-20T14:10:03", "name": "NAT64 support in mlx5 PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/31154/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136926/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/136926/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E0D1A43B54;\n\tTue, 20 Feb 2024 15:11:09 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D1996406BC;\n\tTue, 20 Feb 2024 15:11:09 +0100 (CET)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam02on2069.outbound.protection.outlook.com [40.107.95.69])\n by mails.dpdk.org (Postfix) with ESMTP id A588B409FA\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<orika@nvidia.com>, <aman.deep.singh@intel.com>, <dsosnowski@nvidia.com>,\n <viacheslavo@nvidia.com>, <suanmingm@nvidia.com>, <matan@nvidia.com>,\n <thomas@monjalon.net>, <ferruh.yigit@amd.com>,\n <andrew.rybchenko@oktetlabs.ru>, <dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v2 2/5] net/mlx5: fetch the available registers for NAT64", "Date": "Tue, 20 Feb 2024 16:10:05 +0200", "Message-ID": "<20240220141008.292641-3-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240220141008.292641-1-bingz@nvidia.com>", "References": "<20231227090731.2569427-1-bingz@nvidia.com>\n <20240220141008.292641-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF000042AB:EE_|IA1PR12MB8334:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0093d7db-752d-42dd-2119-08dc321dc73a", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n M6L9UVRlbWgmT49q84jIiA0pZrmtdTOGfBwuPiqXD182/jejMGl/x/Mqrh452uvl2l2nhOakYVtCCo5fyMUyG0vywnsCRK9pEDjqMJAOe9AZWInNjgNQIHBwMXB1ToY5Up8l1wA7NPc977k7CsnlKNUg0LP4yNbkk1OKObp4HCjxTzUy3WbiHKmPoUzQkw5WKFKDzrns67QL2T4PPglxgnCyAl/BWHrPbu+LKUYvwhKBPhYeBXZmIEG+Y7vSn8bgkh8D0S6uRQgiW4eDwy6wIGo8j1POmfToXvQ2LWduU1pql4LCSqBM2eUNgNg5i4q9+yfQ4XOvf9qL7S4/aoVww+vXttDLuM1GsWyHnffY5YjR/7toKvCof+J+OM18ZNuZrEAVPR4gDJ9Ra1wICQxGXjZrs00VZAkfV1jBhZtcsPV9wwdz6DvsNCmmcvsjF+co8nwEFVULcWoHx40R591wu2s9yXtTan3rKGWYgFdvkwWcaMl6k7UPyBrGBZbL4Pl2QFR23eqS1EWGr5oAlXMQe4As4C8iG/XL6+Wq5NM3Nk7cvTEskm44zifEkclnvh06pdrTet6/ipl7APRSgPIVXIto5i0pYOx6V8E4d/An3jYvvjRNHnkhip1RWJknKZrF6Hrcv2jTBPGTaSl8TxrxWDbXFK+iVgZsbSYkhFqn4Dw=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(36860700004)(46966006)(40470700004)(921011); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Feb 2024 14:11:05.6277 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0093d7db-752d-42dd-2119-08dc321dc73a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF000042AB.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB8334", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "REG_C_6 is used as the 1st one and since it is reserved internally\nby default, there is no impact.\n\nThe remaining 2 registers will be fetched from the available TAGs\narray from right to left. They will not be masked in the array due\nto the fact that not all the rules will use NAT64 action.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 9 +++++++++\n drivers/net/mlx5/mlx5.h | 2 ++\n 2 files changed, 11 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 881c42a97a..9c3b9946e3 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1644,6 +1644,15 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)\n \t\tif (!!((1 << i) & masks))\n \t\t\treg->hw_avl_tags[j++] = mlx5_regc_value(i);\n \t}\n+\t/*\n+\t * Set the registers for NAT64 usage internally. REG_C_6 is always used.\n+\t * The other 2 registers will be fetched from right to left, at least 2\n+\t * tag registers should be available.\n+\t */\n+\tMLX5_ASSERT(j >= (MLX5_FLOW_NAT64_REGS_MAX - 1));\n+\treg->nat64_regs[0] = REG_C_6;\n+\treg->nat64_regs[1] = reg->hw_avl_tags[j - 2];\n+\treg->nat64_regs[2] = reg->hw_avl_tags[j - 1];\n }\n \n static void\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 5265d1aa1f..544cf35069 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1407,10 +1407,12 @@ struct mlx5_hws_cnt_svc_mng {\n };\n \n #define MLX5_FLOW_HW_TAGS_MAX 12\n+#define MLX5_FLOW_NAT64_REGS_MAX 3\n \n struct mlx5_dev_registers {\n \tenum modify_reg aso_reg;\n \tenum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX];\n+\tenum modify_reg nat64_regs[MLX5_FLOW_NAT64_REGS_MAX];\n };\n \n #if defined(HAVE_MLX5DV_DR) && \\\n", "prefixes": [ "v2", "2/5" ] }