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GET /api/patches/13690/?format=api
{ "id": 13690, "url": "http://patches.dpdk.org/api/patches/13690/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1465931200-23912-15-git-send-email-jerin.jacob@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1465931200-23912-15-git-send-email-jerin.jacob@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1465931200-23912-15-git-send-email-jerin.jacob@caviumnetworks.com", "date": "2016-06-14T19:06:29", "name": "[dpdk-dev,v5,14/25] net/thunderx: add Tx queue setup and release support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "d38d682ddbba9fc67ce7e10fc54444270b2273ba", "submitter": { "id": 305, "url": "http://patches.dpdk.org/api/people/305/?format=api", "name": "Jerin Jacob", "email": "jerin.jacob@caviumnetworks.com" }, "delegate": { "id": 10, "url": "http://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1465931200-23912-15-git-send-email-jerin.jacob@caviumnetworks.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/13690/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/13690/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id B9E9D9AF6;\n\tTue, 14 Jun 2016 21:08:06 +0200 (CEST)", "from na01-by2-obe.outbound.protection.outlook.com\n\t(mail-by2on0095.outbound.protection.outlook.com [207.46.100.95])\n\tby dpdk.org (Postfix) with ESMTP id 3E8E9AA39\n\tfor <dev@dpdk.org>; Tue, 14 Jun 2016 21:08:04 +0200 (CEST)", "from localhost.caveonetworks.com (111.93.218.67) by\n\tBY1PR0701MB1723.namprd07.prod.outlook.com (10.162.111.142) with\n\tMicrosoft\n\tSMTP Server (TLS) id 15.1.511.8; Tue, 14 Jun 2016 19:08:00 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=OAaxJOaQNI5cBnt51x/tx8lQkD8elwGsTY7DkheJMtw=;\n\tb=io7QDKyZez46WHrrPh7oRT/bZfDDc5GtoOiSuCnEuQAE7E27c76tDqHUOQZtYFcZbzmDOWIVGbVb09Ahziy7dNPZyWR3gNfAWfD8URd8gMS9Yh9dOxg1nxeoEE4FFv9w0kdTXyF3fNQk7mVEbHEUDMBosLqPsN7Sc8nOpPVafo4=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Jerin.Jacob@cavium.com; ", "From": "Jerin Jacob <jerin.jacob@caviumnetworks.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,\n\t<ferruh.yigit@intel.com>, Jerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tMaciej Czekaj <maciej.czekaj@caviumnetworks.com>, Kamil Rytarowski\n\t<Kamil.Rytarowski@caviumnetworks.com>,\n\tZyta Szpak <zyta.szpak@semihalf.com>, \n\tSlawomir Rosek <slawomir.rosek@semihalf.com>, Radoslaw Biernacki\n\t<rad@semihalf.com>", "Date": "Wed, 15 Jun 2016 00:36:29 +0530", "Message-ID": "<1465931200-23912-15-git-send-email-jerin.jacob@caviumnetworks.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1465931200-23912-1-git-send-email-jerin.jacob@caviumnetworks.com>", "References": "<1465826143-22159-1-git-send-email-jerin.jacob@caviumnetworks.com>\n\t<1465931200-23912-1-git-send-email-jerin.jacob@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[111.93.218.67]", "X-ClientProxiedBy": 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"X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY1PR0701MB1723", "Subject": "[dpdk-dev] [PATCH v5 14/25] net/thunderx: add Tx queue setup and\n\trelease support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>\nSigned-off-by: Maciej Czekaj <maciej.czekaj@caviumnetworks.com>\nSigned-off-by: Kamil Rytarowski <Kamil.Rytarowski@caviumnetworks.com>\nSigned-off-by: Zyta Szpak <zyta.szpak@semihalf.com>\nSigned-off-by: Slawomir Rosek <slawomir.rosek@semihalf.com>\nSigned-off-by: Radoslaw Biernacki <rad@semihalf.com>\n---\n drivers/net/thunderx/nicvf_ethdev.c | 175 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 175 insertions(+)", "diff": "diff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c\nindex 4652438..167149e 100644\n--- a/drivers/net/thunderx/nicvf_ethdev.c\n+++ b/drivers/net/thunderx/nicvf_ethdev.c\n@@ -191,6 +191,179 @@ nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,\n \treturn 0;\n }\n \n+static int\n+nicvf_qset_sq_alloc(struct nicvf *nic, struct nicvf_txq *sq, uint16_t qidx,\n+\t\t uint32_t desc_cnt)\n+{\n+\tconst struct rte_memzone *rz;\n+\tuint32_t ring_size = desc_cnt * sizeof(union sq_entry_t);\n+\n+\trz = rte_eth_dma_zone_reserve(nic->eth_dev, \"sq\", qidx, ring_size,\n+\t\t\t\tNICVF_SQ_BASE_ALIGN_BYTES, nic->node);\n+\tif (rz == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed allocate mem for sq hw ring\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tmemset(rz->addr, 0, ring_size);\n+\n+\tsq->phys = rz->phys_addr;\n+\tsq->desc = rz->addr;\n+\tsq->qlen_mask = desc_cnt - 1;\n+\n+\treturn 0;\n+}\n+\n+static inline void\n+nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)\n+{\n+\tuint32_t head;\n+\n+\thead = txq->head;\n+\twhile (head != txq->tail) {\n+\t\tif (txq->txbuffs[head]) {\n+\t\t\trte_pktmbuf_free_seg(txq->txbuffs[head]);\n+\t\t\ttxq->txbuffs[head] = NULL;\n+\t\t}\n+\t\thead++;\n+\t\thead = head & txq->qlen_mask;\n+\t}\n+}\n+\n+static void\n+nicvf_tx_queue_reset(struct nicvf_txq *txq)\n+{\n+\tuint32_t txq_desc_cnt = txq->qlen_mask + 1;\n+\n+\tmemset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);\n+\tmemset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);\n+\ttxq->tail = 0;\n+\ttxq->head = 0;\n+\ttxq->xmit_bufs = 0;\n+}\n+\n+static void\n+nicvf_dev_tx_queue_release(void *sq)\n+{\n+\tstruct nicvf_txq *txq;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxq = (struct nicvf_txq *)sq;\n+\tif (txq) {\n+\t\tif (txq->txbuffs != NULL) {\n+\t\t\tnicvf_tx_queue_release_mbufs(txq);\n+\t\t\trte_free(txq->txbuffs);\n+\t\t\ttxq->txbuffs = NULL;\n+\t\t}\n+\t\trte_free(txq);\n+\t}\n+}\n+\n+static int\n+nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,\n+\t\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t\t const struct rte_eth_txconf *tx_conf)\n+{\n+\tuint16_t tx_free_thresh;\n+\tuint8_t is_single_pool;\n+\tstruct nicvf_txq *txq;\n+\tstruct nicvf *nic = nicvf_pmd_priv(dev);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Socket id check */\n+\tif (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)\n+\t\tPMD_DRV_LOG(WARNING, \"socket_id expected %d, configured %d\",\n+\t\tsocket_id, nic->node);\n+\n+\t/* Tx deferred start is not supported */\n+\tif (tx_conf->tx_deferred_start) {\n+\t\tPMD_INIT_LOG(ERR, \"Tx deferred start not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Roundup nb_desc to available qsize and validate max number of desc */\n+\tnb_desc = nicvf_qsize_sq_roundup(nb_desc);\n+\tif (nb_desc == 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Value of nb_desc beyond available sq qsize\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Validate tx_free_thresh */\n+\ttx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?\n+\t\t\t\ttx_conf->tx_free_thresh :\n+\t\t\t\tNICVF_DEFAULT_TX_FREE_THRESH);\n+\n+\tif (tx_free_thresh > (nb_desc) ||\n+\t\ttx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\"tx_free_thresh must be less than the number of TX \"\n+\t\t\t\"descriptors. (tx_free_thresh=%u port=%d \"\n+\t\t\t\"queue=%d)\", (unsigned int)tx_free_thresh,\n+\t\t\t(int)dev->data->port_id, (int)qidx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Free memory prior to re-allocation if needed. */\n+\tif (dev->data->tx_queues[qidx] != NULL) {\n+\t\tPMD_TX_LOG(DEBUG, \"Freeing memory prior to re-allocation %d\",\n+\t\t\t\tqidx);\n+\t\tnicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]);\n+\t\tdev->data->tx_queues[qidx] = NULL;\n+\t}\n+\n+\t/* Allocating tx queue data structure */\n+\ttxq = rte_zmalloc_socket(\"ethdev TX queue\", sizeof(struct nicvf_txq),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE, nic->node);\n+\tif (txq == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate txq=%d\", qidx);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ttxq->nic = nic;\n+\ttxq->queue_id = qidx;\n+\ttxq->tx_free_thresh = tx_free_thresh;\n+\ttxq->txq_flags = tx_conf->txq_flags;\n+\ttxq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;\n+\ttxq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;\n+\tis_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&\n+\t\t\t\ttxq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);\n+\n+\t/* Choose optimum free threshold value for multipool case */\n+\tif (!is_single_pool) {\n+\t\ttxq->tx_free_thresh = (uint16_t)\n+\t\t(tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?\n+\t\t\t\tNICVF_TX_FREE_MPOOL_THRESH :\n+\t\t\t\ttx_conf->tx_free_thresh);\n+\t}\n+\n+\t/* Allocate software ring */\n+\ttxq->txbuffs = rte_zmalloc_socket(\"txq->txbuffs\",\n+\t\t\t\tnb_desc * sizeof(struct rte_mbuf *),\n+\t\t\t\tRTE_CACHE_LINE_SIZE, nic->node);\n+\n+\tif (txq->txbuffs == NULL) {\n+\t\tnicvf_dev_tx_queue_release(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (nicvf_qset_sq_alloc(nic, txq, qidx, nb_desc)) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate mem for sq %d\", qidx);\n+\t\tnicvf_dev_tx_queue_release(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tnicvf_tx_queue_reset(txq);\n+\n+\tPMD_TX_LOG(DEBUG, \"[%d] txq=%p nb_desc=%d desc=%p phys=0x%\" PRIx64,\n+\t\t\tqidx, txq, nb_desc, txq->desc, txq->phys);\n+\n+\tdev->data->tx_queues[qidx] = txq;\n+\tdev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\treturn 0;\n+}\n+\n static void\n nicvf_rx_queue_reset(struct nicvf_rxq *rxq)\n {\n@@ -430,6 +603,8 @@ static const struct eth_dev_ops nicvf_eth_dev_ops = {\n \t.dev_infos_get = nicvf_dev_info_get,\n \t.rx_queue_setup = nicvf_dev_rx_queue_setup,\n \t.rx_queue_release = nicvf_dev_rx_queue_release,\n+\t.tx_queue_setup = nicvf_dev_tx_queue_setup,\n+\t.tx_queue_release = nicvf_dev_tx_queue_release,\n \t.get_reg_length = nicvf_dev_get_reg_length,\n \t.get_reg = nicvf_dev_get_regs,\n };\n", "prefixes": [ "dpdk-dev", "v5", "14/25" ] }