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GET /api/patches/136449/?format=api
{ "id": 136449, "url": "http://patches.dpdk.org/api/patches/136449/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240207021849.52988-7-andrew.boyer@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240207021849.52988-7-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240207021849.52988-7-andrew.boyer@amd.com", "date": "2024-02-07T02:18:42", "name": "[v2,06/13] net/ionic: memcpy descriptors when using Q-in-CMB", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e4832df4a0bf80e9fee443054e545bb5e986398b", "submitter": { "id": 2861, "url": "http://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240207021849.52988-7-andrew.boyer@amd.com/mbox/", "series": [ { "id": 31023, "url": "http://patches.dpdk.org/api/series/31023/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31023", "date": "2024-02-07T02:18:42", "name": null, "version": 2, "mbox": "http://patches.dpdk.org/series/31023/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136449/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/136449/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C109843A1B;\n\tWed, 7 Feb 2024 03:20:18 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4AE7242D90;\n\tWed, 7 Feb 2024 03:19:51 +0100 (CET)", "from NAM04-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam04on2074.outbound.protection.outlook.com [40.107.100.74])\n by mails.dpdk.org (Postfix) with ESMTP id BE1E742DA1\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Neel Patel <neel.patel@amd.com>, Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH v2 06/13] net/ionic: memcpy descriptors when using Q-in-CMB", "Date": "Tue, 6 Feb 2024 18:18:42 -0800", "Message-ID": "<20240207021849.52988-7-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240202193238.62669-1-andrew.boyer@amd.com>", "References": "<20240202193238.62669-1-andrew.boyer@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SA2PEPF000015CC:EE_|SN7PR12MB7912:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0a821d82-17b0-4783-6147-08dc278340ac", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n zfryJ3pqTG7tfplnm4eS/qPW54waG6I3qAJ3B2IZyaYdZphQL8jrt0cqhDCrrWXY2Z9MXnvQ8HfEvbz8Mr53REg2jJel9cTMRs8bv89vDdYvoLs8+h8WS5JyfSVRYmNeodfXpW2tWQCGxxhGUe6m4xyLdOPXLboo6MKf6+pWYqR92GpDJrSq3wFfCa6UxmX+obSya/wnzdsBJJhXA5hdM4imuQKBFGzl9CDPeJNKJGlssqL7RyTfCsKNISA8JayvjbxwWgsMtXgXTbgzuyvXstaIB8vug4WSB7QBKhsc8R+/+zaBKIHjR1+r57kG9dndhGWZnZr0gqBpt3vF2er8HfhQbnbHOKWBdeCFmo7iHOmXNGZAYRLk57BjcNRDQIi80/7Yb2ExkAiIpdZfCkdnfGatFu/fNMah/tAblanJ4sgu9PvH9TqCPPt1Hv7E4cRnHD7kct4Gd1lHp+Gj/bNim/dpBSiBzaavc6Z4CtvXfQ8CNgfI4upw6NMWlj3PP+9+r6/0dp2PqU5hgmikqlmrdQl1cHg+MvPYxivjylM8J4CnSqBm2rgoJOldAkyWKGoIRIeQoO25mjohgIzYkWBlTsdBLoMpzjDfhhQpbmUP3rABagE59DPDkH/Vwbohi1IRYNOK8iWf4/Ou3Uef2KmyWNSX9cfj4abD2wE9EYGAWgpzfeIPyfuC6kp1e93GZkCrxwDyypsA3OSvkPDFIOY0qDjrUUKZfCA4yNhN/lNyLitHgM9hVOGOKjkKjhghxScte3LOajITnIQbBIRuOAKlZw==", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF000015CC.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB7912", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Neel Patel <neel.patel@amd.com>\n\nThey can be batched together this way, reducing the number\nof PCIe transactions. This improves transmit PPS by up to 50% in\nsome configurations.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\nSigned-off-by: Neel Patel <neel.patel@amd.com>\n---\n drivers/net/ionic/ionic_dev.c | 9 +++--\n drivers/net/ionic/ionic_dev.h | 6 ++-\n drivers/net/ionic/ionic_lif.c | 26 +++++++++----\n drivers/net/ionic/ionic_rxtx.h | 56 +++++++++++++++++++++++++++\n drivers/net/ionic/ionic_rxtx_sg.c | 18 ++++-----\n drivers/net/ionic/ionic_rxtx_simple.c | 18 ++++-----\n 6 files changed, 101 insertions(+), 32 deletions(-)", "diff": "diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c\nindex 70c14882ed..7f15914f74 100644\n--- a/drivers/net/ionic/ionic_dev.c\n+++ b/drivers/net/ionic/ionic_dev.c\n@@ -369,17 +369,19 @@ ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs)\n \tq->index = index;\n \tq->num_descs = num_descs;\n \tq->size_mask = num_descs - 1;\n-\tq->head_idx = 0;\n-\tq->tail_idx = 0;\n+\tionic_q_reset(q);\n \n \treturn 0;\n }\n \n void\n-ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)\n+ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa,\n+\t\t\tvoid *cmb_base, rte_iova_t cmb_base_pa)\n {\n \tq->base = base;\n \tq->base_pa = base_pa;\n+\tq->cmb_base = cmb_base;\n+\tq->cmb_base_pa = cmb_base_pa;\n }\n \n void\n@@ -393,5 +395,6 @@ void\n ionic_q_reset(struct ionic_queue *q)\n {\n \tq->head_idx = 0;\n+\tq->cmb_head_idx = 0;\n \tq->tail_idx = 0;\n }\ndiff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h\nindex 971c261b27..3a366247f1 100644\n--- a/drivers/net/ionic/ionic_dev.h\n+++ b/drivers/net/ionic/ionic_dev.h\n@@ -145,11 +145,13 @@ struct ionic_queue {\n \tuint16_t num_descs;\n \tuint16_t num_segs;\n \tuint16_t head_idx;\n+\tuint16_t cmb_head_idx;\n \tuint16_t tail_idx;\n \tuint16_t size_mask;\n \tuint8_t type;\n \tuint8_t hw_type;\n \tvoid *base;\n+\tvoid *cmb_base;\n \tvoid *sg_base;\n \tstruct ionic_doorbell __iomem *db;\n \tvoid **info;\n@@ -158,6 +160,7 @@ struct ionic_queue {\n \tuint32_t hw_index;\n \trte_iova_t base_pa;\n \trte_iova_t sg_base_pa;\n+\trte_iova_t cmb_base_pa;\n };\n \n #define IONIC_INTR_NONE\t\t(-1)\n@@ -244,7 +247,8 @@ uint32_t ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,\n \n int ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs);\n void ionic_q_reset(struct ionic_queue *q);\n-void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa);\n+void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa,\n+\t\t\t\t void *cmb_base, rte_iova_t cmb_base_pa);\n void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa);\n \n static inline uint16_t\ndiff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex fe2112c057..2713f8aa24 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -572,10 +572,11 @@ ionic_qcq_alloc(struct ionic_lif *lif,\n {\n \tstruct ionic_qcq *new;\n \tuint32_t q_size, cq_size, sg_size, total_size;\n-\tvoid *q_base, *cq_base, *sg_base;\n+\tvoid *q_base, *cmb_q_base, *cq_base, *sg_base;\n \trte_iova_t q_base_pa = 0;\n \trte_iova_t cq_base_pa = 0;\n \trte_iova_t sg_base_pa = 0;\n+\trte_iova_t cmb_q_base_pa = 0;\n \tsize_t page_size = rte_mem_page_size();\n \tint err;\n \n@@ -666,19 +667,22 @@ ionic_qcq_alloc(struct ionic_lif *lif,\n \t\t\tIONIC_PRINT(ERR, \"Cannot reserve queue from NIC mem\");\n \t\t\treturn -ENOMEM;\n \t\t}\n-\t\tq_base = (void *)\n+\t\tcmb_q_base = (void *)\n \t\t\t((uintptr_t)lif->adapter->bars.bar[2].vaddr +\n \t\t\t (uintptr_t)lif->adapter->cmb_offset);\n \t\t/* CMB PA is a relative address */\n-\t\tq_base_pa = lif->adapter->cmb_offset;\n+\t\tcmb_q_base_pa = lif->adapter->cmb_offset;\n \t\tlif->adapter->cmb_offset += q_size;\n+\t} else {\n+\t\tcmb_q_base = NULL;\n+\t\tcmb_q_base_pa = 0;\n \t}\n \n \tIONIC_PRINT(DEBUG, \"Q-Base-PA = %#jx CQ-Base-PA = %#jx \"\n \t\t\"SG-base-PA = %#jx\",\n \t\tq_base_pa, cq_base_pa, sg_base_pa);\n \n-\tionic_q_map(&new->q, q_base, q_base_pa);\n+\tionic_q_map(&new->q, q_base, q_base_pa, cmb_q_base, cmb_q_base_pa);\n \tionic_cq_map(&new->cq, cq_base, cq_base_pa);\n \n \t*qcq = new;\n@@ -1583,7 +1587,6 @@ ionic_lif_txq_init(struct ionic_tx_qcq *txq)\n \t\t\t.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA),\n \t\t\t.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),\n \t\t\t.ring_size = rte_log2_u32(q->num_descs),\n-\t\t\t.ring_base = rte_cpu_to_le_64(q->base_pa),\n \t\t\t.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),\n \t\t\t.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),\n \t\t},\n@@ -1592,8 +1595,12 @@ ionic_lif_txq_init(struct ionic_tx_qcq *txq)\n \n \tif (txq->flags & IONIC_QCQ_F_SG)\n \t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n-\tif (txq->flags & IONIC_QCQ_F_CMB)\n+\tif (txq->flags & IONIC_QCQ_F_CMB) {\n \t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n+\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n+\t} else {\n+\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n+\t}\n \n \tIONIC_PRINT(DEBUG, \"txq_init.index %d\", q->index);\n \tIONIC_PRINT(DEBUG, \"txq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n@@ -1638,7 +1645,6 @@ ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)\n \t\t\t.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA),\n \t\t\t.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),\n \t\t\t.ring_size = rte_log2_u32(q->num_descs),\n-\t\t\t.ring_base = rte_cpu_to_le_64(q->base_pa),\n \t\t\t.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),\n \t\t\t.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),\n \t\t},\n@@ -1647,8 +1653,12 @@ ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)\n \n \tif (rxq->flags & IONIC_QCQ_F_SG)\n \t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_SG);\n-\tif (rxq->flags & IONIC_QCQ_F_CMB)\n+\tif (rxq->flags & IONIC_QCQ_F_CMB) {\n \t\tctx.cmd.q_init.flags |= rte_cpu_to_le_16(IONIC_QINIT_F_CMB);\n+\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->cmb_base_pa);\n+\t} else {\n+\t\tctx.cmd.q_init.ring_base = rte_cpu_to_le_64(q->base_pa);\n+\t}\n \n \tIONIC_PRINT(DEBUG, \"rxq_init.index %d\", q->index);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\ndiff --git a/drivers/net/ionic/ionic_rxtx.h b/drivers/net/ionic/ionic_rxtx.h\nindex 8537141597..5348395956 100644\n--- a/drivers/net/ionic/ionic_rxtx.h\n+++ b/drivers/net/ionic/ionic_rxtx.h\n@@ -77,4 +77,60 @@ uint16_t ionic_xmit_pkts_sg(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n int ionic_rx_fill_sg(struct ionic_rx_qcq *rxq);\n \n+static inline void\n+ionic_rxq_flush(struct ionic_queue *q)\n+{\n+\tstruct ionic_rxq_desc *desc_base = q->base;\n+\tstruct ionic_rxq_desc *cmb_desc_base = q->cmb_base;\n+\n+\tif (q->cmb_base) {\n+\t\tif (q->head_idx < q->cmb_head_idx) {\n+\t\t\t/* copy [cmb_head, num_descs) */\n+\t\t\trte_memcpy((void *)&cmb_desc_base[q->cmb_head_idx],\n+\t\t\t\t(void *)&desc_base[q->cmb_head_idx],\n+\t\t\t\t(q->num_descs - q->cmb_head_idx) * sizeof(*desc_base));\n+\t\t\t/* copy [0, head) */\n+\t\t\trte_memcpy((void *)&cmb_desc_base[0],\n+\t\t\t\t(void *)&desc_base[0],\n+\t\t\t\tq->head_idx * sizeof(*desc_base));\n+\t\t} else {\n+\t\t\t/* copy [cmb_head, head) */\n+\t\t\trte_memcpy((void *)&cmb_desc_base[q->cmb_head_idx],\n+\t\t\t\t(void *)&desc_base[q->cmb_head_idx],\n+\t\t\t\t(q->head_idx - q->cmb_head_idx) * sizeof(*desc_base));\n+\t\t}\n+\t\tq->cmb_head_idx = q->head_idx;\n+\t}\n+\n+\tionic_q_flush(q);\n+}\n+\n+static inline void\n+ionic_txq_flush(struct ionic_queue *q)\n+{\n+\tstruct ionic_txq_desc *desc_base = q->base;\n+\tstruct ionic_txq_desc *cmb_desc_base = q->cmb_base;\n+\n+\tif (q->cmb_base) {\n+\t\tif (q->head_idx < q->cmb_head_idx) {\n+\t\t\t/* copy [cmb_head, num_descs) */\n+\t\t\trte_memcpy((void *)&cmb_desc_base[q->cmb_head_idx],\n+\t\t\t\t(void *)&desc_base[q->cmb_head_idx],\n+\t\t\t\t(q->num_descs - q->cmb_head_idx) * sizeof(*desc_base));\n+\t\t\t/* copy [0, head) */\n+\t\t\trte_memcpy((void *)&cmb_desc_base[0],\n+\t\t\t\t(void *)&desc_base[0],\n+\t\t\t\tq->head_idx * sizeof(*desc_base));\n+\t\t} else {\n+\t\t\t/* copy [cmb_head, head) */\n+\t\t\trte_memcpy((void *)&cmb_desc_base[q->cmb_head_idx],\n+\t\t\t\t(void *)&desc_base[q->cmb_head_idx],\n+\t\t\t\t(q->head_idx - q->cmb_head_idx) * sizeof(*desc_base));\n+\t\t}\n+\t\tq->cmb_head_idx = q->head_idx;\n+\t}\n+\n+\tionic_q_flush(q);\n+}\n+\n #endif /* _IONIC_RXTX_H_ */\ndiff --git a/drivers/net/ionic/ionic_rxtx_sg.c b/drivers/net/ionic/ionic_rxtx_sg.c\nindex 1392342463..92e1d6e259 100644\n--- a/drivers/net/ionic/ionic_rxtx_sg.c\n+++ b/drivers/net/ionic/ionic_rxtx_sg.c\n@@ -166,6 +166,7 @@ ionic_xmit_pkts_sg(void *tx_queue, struct rte_mbuf **tx_pkts,\n {\n \tstruct ionic_tx_qcq *txq = tx_queue;\n \tstruct ionic_queue *q = &txq->qcq.q;\n+\tstruct ionic_txq_desc *desc_base = q->base;\n \tstruct ionic_tx_stats *stats = &txq->stats;\n \tstruct rte_mbuf *mbuf;\n \tuint32_t bytes_tx = 0;\n@@ -173,9 +174,7 @@ ionic_xmit_pkts_sg(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint64_t then, now, hz, delta;\n \tint err;\n \n-\tstruct ionic_txq_desc *desc_base = q->base;\n-\tif (!(txq->flags & IONIC_QCQ_F_CMB))\n-\t\trte_prefetch0(&desc_base[q->head_idx]);\n+\trte_prefetch0(&desc_base[q->head_idx]);\n \trte_prefetch0(IONIC_INFO_PTR(q, q->head_idx));\n \n \tif (nb_pkts) {\n@@ -196,8 +195,7 @@ ionic_xmit_pkts_sg(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \twhile (nb_tx < nb_pkts) {\n \t\tuint16_t next_idx = Q_NEXT_TO_POST(q, 1);\n-\t\tif (!(txq->flags & IONIC_QCQ_F_CMB))\n-\t\t\trte_prefetch0(&desc_base[next_idx]);\n+\t\trte_prefetch0(&desc_base[next_idx]);\n \t\trte_prefetch0(IONIC_INFO_PTR(q, next_idx));\n \n \t\tif (nb_tx + 1 < nb_pkts) {\n@@ -222,7 +220,7 @@ ionic_xmit_pkts_sg(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \tif (nb_tx > 0) {\n \t\trte_wmb();\n-\t\tionic_q_flush(q);\n+\t\tionic_txq_flush(q);\n \n \t\ttxq->last_wdog_cycles = rte_get_timer_cycles();\n \n@@ -458,8 +456,7 @@ ionic_rxq_service_sg(struct ionic_rx_qcq *rxq, uint32_t work_to_do,\n \t\t/* Prefetch 4 x 16B comp */\n \t\trte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]);\n \t\t/* Prefetch 4 x 16B descriptors */\n-\t\tif (!(rxq->flags & IONIC_QCQ_F_CMB))\n-\t\t\trte_prefetch0(&q_desc_base[Q_NEXT_TO_POST(q, 4)]);\n+\t\trte_prefetch0(&q_desc_base[Q_NEXT_TO_POST(q, 4)]);\n \n \t\t/* Clean one descriptor */\n \t\tionic_rx_clean_one_sg(rxq, cq_desc, rx_svc);\n@@ -478,7 +475,8 @@ ionic_rxq_service_sg(struct ionic_rx_qcq *rxq, uint32_t work_to_do,\n \n \t/* Update the queue indices and ring the doorbell */\n \tif (work_done) {\n-\t\tionic_q_flush(q);\n+\t\tionic_rxq_flush(q);\n+\n \t\trxq->last_wdog_cycles = rte_get_timer_cycles();\n \t\trxq->wdog_ms = IONIC_Q_WDOG_MS;\n \t} else {\n@@ -542,7 +540,7 @@ ionic_rx_fill_sg(struct ionic_rx_qcq *rxq)\n \t\tq->head_idx = Q_NEXT_TO_POST(q, 1);\n \t}\n \n-\tionic_q_flush(q);\n+\tionic_rxq_flush(q);\n \n \treturn err;\n }\ndiff --git a/drivers/net/ionic/ionic_rxtx_simple.c b/drivers/net/ionic/ionic_rxtx_simple.c\nindex 00152c885a..f12f66f40c 100644\n--- a/drivers/net/ionic/ionic_rxtx_simple.c\n+++ b/drivers/net/ionic/ionic_rxtx_simple.c\n@@ -139,6 +139,7 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n {\n \tstruct ionic_tx_qcq *txq = tx_queue;\n \tstruct ionic_queue *q = &txq->qcq.q;\n+\tstruct ionic_txq_desc *desc_base = q->base;\n \tstruct ionic_tx_stats *stats = &txq->stats;\n \tstruct rte_mbuf *mbuf;\n \tuint32_t bytes_tx = 0;\n@@ -146,9 +147,7 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint64_t then, now, hz, delta;\n \tint err;\n \n-\tstruct ionic_txq_desc *desc_base = q->base;\n-\tif (!(txq->flags & IONIC_QCQ_F_CMB))\n-\t\trte_prefetch0(&desc_base[q->head_idx]);\n+\trte_prefetch0(&desc_base[q->head_idx]);\n \trte_prefetch0(&q->info[q->head_idx]);\n \n \tif (nb_pkts) {\n@@ -169,8 +168,7 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \twhile (nb_tx < nb_pkts) {\n \t\tuint16_t next_idx = Q_NEXT_TO_POST(q, 1);\n-\t\tif (!(txq->flags & IONIC_QCQ_F_CMB))\n-\t\t\trte_prefetch0(&desc_base[next_idx]);\n+\t\trte_prefetch0(&desc_base[next_idx]);\n \t\trte_prefetch0(&q->info[next_idx]);\n \n \t\tif (nb_tx + 1 < nb_pkts) {\n@@ -195,7 +193,7 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \tif (nb_tx > 0) {\n \t\trte_wmb();\n-\t\tionic_q_flush(q);\n+\t\tionic_txq_flush(q);\n \n \t\ttxq->last_wdog_cycles = rte_get_timer_cycles();\n \n@@ -379,8 +377,7 @@ ionic_rxq_service(struct ionic_rx_qcq *rxq, uint32_t work_to_do,\n \t\t/* Prefetch 4 x 16B comp */\n \t\trte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]);\n \t\t/* Prefetch 4 x 16B descriptors */\n-\t\tif (!(rxq->flags & IONIC_QCQ_F_CMB))\n-\t\t\trte_prefetch0(&q_desc_base[Q_NEXT_TO_POST(q, 4)]);\n+\t\trte_prefetch0(&q_desc_base[Q_NEXT_TO_POST(q, 4)]);\n \n \t\t/* Clean one descriptor */\n \t\tionic_rx_clean_one(rxq, cq_desc, rx_svc);\n@@ -399,7 +396,8 @@ ionic_rxq_service(struct ionic_rx_qcq *rxq, uint32_t work_to_do,\n \n \t/* Update the queue indices and ring the doorbell */\n \tif (work_done) {\n-\t\tionic_q_flush(q);\n+\t\tionic_rxq_flush(q);\n+\n \t\trxq->last_wdog_cycles = rte_get_timer_cycles();\n \t\trxq->wdog_ms = IONIC_Q_WDOG_MS;\n \t} else {\n@@ -463,7 +461,7 @@ ionic_rx_fill(struct ionic_rx_qcq *rxq)\n \t\tq->head_idx = Q_NEXT_TO_POST(q, 1);\n \t}\n \n-\tionic_q_flush(q);\n+\tionic_rxq_flush(q);\n \n \treturn err;\n }\n", "prefixes": [ "v2", "06/13" ] }