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GET /api/patches/136268/?format=api
{ "id": 136268, "url": "http://patches.dpdk.org/api/patches/136268/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240201130754.194352-10-hkalra@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240201130754.194352-10-hkalra@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240201130754.194352-10-hkalra@marvell.com", "date": "2024-02-01T13:07:40", "name": "[v3,09/23] net/cnxk: eswitch fastpath routines", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "8df2f8086de773e9f5f8f13290b7763d90dbb5b7", "submitter": { "id": 1182, "url": "http://patches.dpdk.org/api/people/1182/?format=api", "name": "Harman Kalra", "email": "hkalra@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240201130754.194352-10-hkalra@marvell.com/mbox/", "series": [ { "id": 30966, "url": "http://patches.dpdk.org/api/series/30966/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30966", "date": "2024-02-01T13:07:31", "name": "net/cnxk: support for port representors", "version": 3, "mbox": "http://patches.dpdk.org/series/30966/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136268/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/136268/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BE18843A3A;\n\tThu, 1 Feb 2024 14:09:41 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C35EA42E42;\n\tThu, 1 Feb 2024 14:08:48 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 390EC42E40\n for <dev@dpdk.org>; Thu, 1 Feb 2024 14:08:47 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 4119u9ei001853 for <dev@dpdk.org>; Thu, 1 Feb 2024 05:08:46 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3w0937ghc8-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Feb 2024 05:08:46 -0800 (PST)", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Thu, 1 Feb 2024 05:08:44 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Thu, 1 Feb 2024 05:08:44 -0800", "from localhost.localdomain (unknown [10.29.52.211])\n by maili.marvell.com (Postfix) with ESMTP id 3324E3F706A;\n Thu, 1 Feb 2024 05:08:41 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-type; s=pfpt0220; bh=+WlWTcfMGW/zWv758/Dky\n GbNh4XxjIjYFZlVqjzC7MA=; b=Og9epW48gp1r9W35bW7476iO+GCmpeig1Xsuv\n Axl3+iuFnARzyzGYafNu6if+WF4cggAHup3fkDiHHrhgvOYPYEYNyuN+xU2Fnzad\n 3yMr1lqtTSz8JTRgNZPxNg3vUtFB3pM80kqyyi4lW12ZCbz68ZiF6lt6MFrg/47i\n sWRdlatrMjoY6ePFAJKw0DKaHSLhe0mbYMrSPIaFDRUvleGL1OR0fOGFoGKeioc2\n tbqrZ9vn7VJkJHE9HcANfJVYfnum9YwKbuTrygOav4xFdPCBb0B3GUeEuxwbPbqH\n 1xLXDfIXaSV2RxnpSEVUAo2ivV4ue9Ly6nsBJPCVXSQIEHtvA==", "From": "Harman Kalra <hkalra@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Harman Kalra <hkalra@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v3 09/23] net/cnxk: eswitch fastpath routines", "Date": "Thu, 1 Feb 2024 18:37:40 +0530", "Message-ID": "<20240201130754.194352-10-hkalra@marvell.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<20240201130754.194352-1-hkalra@marvell.com>", "References": "<20230811163419.165790-1-hkalra@marvell.com>\n <20240201130754.194352-1-hkalra@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "h-KER0ohuZ1tO08X1YYimqKjhF2ZRhdc", "X-Proofpoint-GUID": "h-KER0ohuZ1tO08X1YYimqKjhF2ZRhdc", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-02-01_02,2024-01-31_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Implementing fastpath RX and TX fast path routines which can be\ninvoked from respective representors rx burst and tx burst\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/net/cnxk/cnxk_eswitch.h | 5 +\n drivers/net/cnxk/cnxk_eswitch_rxtx.c | 211 +++++++++++++++++++++++++++\n drivers/net/cnxk/meson.build | 1 +\n 3 files changed, 217 insertions(+)\n create mode 100644 drivers/net/cnxk/cnxk_eswitch_rxtx.c", "diff": "diff --git a/drivers/net/cnxk/cnxk_eswitch.h b/drivers/net/cnxk/cnxk_eswitch.h\nindex 5b4e1b0a71..4edfa91bdc 100644\n--- a/drivers/net/cnxk/cnxk_eswitch.h\n+++ b/drivers/net/cnxk/cnxk_eswitch.h\n@@ -177,4 +177,9 @@ int cnxk_eswitch_pfvf_flow_rules_install(struct cnxk_eswitch_dev *eswitch_dev, b\n int cnxk_eswitch_flow_rule_shift(uint16_t hw_func, uint16_t *new_entry);\n int cnxk_eswitch_flow_rules_remove_list(struct cnxk_eswitch_dev *eswitch_dev,\n \t\t\t\t\tstruct flow_list *list, uint16_t hw_func);\n+/* RX TX fastpath routines */\n+uint16_t cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,\n+\t\t\t\t struct rte_mbuf **pkts, uint16_t nb_tx, const uint16_t flags);\n+uint16_t cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,\n+\t\t\t\t struct rte_mbuf **pkts, uint16_t nb_pkts);\n #endif /* __CNXK_ESWITCH_H__ */\ndiff --git a/drivers/net/cnxk/cnxk_eswitch_rxtx.c b/drivers/net/cnxk/cnxk_eswitch_rxtx.c\nnew file mode 100644\nindex 0000000000..d57e32b091\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_eswitch_rxtx.c\n@@ -0,0 +1,211 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2024 Marvell.\n+ */\n+\n+#include <cnxk_eswitch.h>\n+\n+static __rte_always_inline struct rte_mbuf *\n+eswitch_nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)\n+{\n+\trte_iova_t buff;\n+\n+\t/* Skip CQE, NIX_RX_PARSE_S and SG HDR(9 DWORDs) and peek buff addr */\n+\tbuff = *((rte_iova_t *)((uint64_t *)cq + 9));\n+\treturn (struct rte_mbuf *)(buff - data_off);\n+}\n+\n+static inline uint64_t\n+eswitch_nix_rx_nb_pkts(struct roc_nix_cq *cq, const uint64_t wdata, const uint32_t qmask)\n+{\n+\tuint64_t reg, head, tail;\n+\tuint32_t available;\n+\n+\t/* Update the available count if cached value is not enough */\n+\n+\t/* Use LDADDA version to avoid reorder */\n+\treg = roc_atomic64_add_sync(wdata, cq->status);\n+\t/* CQ_OP_STATUS operation error */\n+\tif (reg & BIT_ULL(NIX_CQ_OP_STAT_OP_ERR) || reg & BIT_ULL(NIX_CQ_OP_STAT_CQ_ERR))\n+\t\treturn 0;\n+\n+\ttail = reg & 0xFFFFF;\n+\thead = (reg >> 20) & 0xFFFFF;\n+\tif (tail < head)\n+\t\tavailable = tail - head + qmask + 1;\n+\telse\n+\t\tavailable = tail - head;\n+\n+\treturn available;\n+}\n+\n+static inline void\n+nix_cn9k_xmit_one(uint64_t *cmd, void *lmt_addr, const plt_iova_t io_addr)\n+{\n+\tuint64_t lmt_status;\n+\n+\tdo {\n+\t\troc_lmt_mov(lmt_addr, cmd, 0);\n+\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t} while (lmt_status == 0);\n+}\n+\n+uint16_t\n+cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,\n+\t\t\t struct rte_mbuf **pkts, uint16_t nb_xmit, const uint16_t flags)\n+{\n+\tstruct roc_nix_sq *sq = &eswitch_dev->txq[qid].sqs;\n+\tstruct roc_nix_rq *rq = &eswitch_dev->rxq[qid].rqs;\n+\tuint64_t aura_handle, cmd[6], data = 0;\n+\tuint16_t lmt_id, pkt = 0, nb_tx = 0;\n+\tstruct nix_send_ext_s *send_hdr_ext;\n+\tstruct nix_send_hdr_s *send_hdr;\n+\tuint16_t vlan_tci = qid;\n+\tunion nix_send_sg_s *sg;\n+\tuintptr_t lmt_base, pa;\n+\tint64_t fc_pkts, dw_m1;\n+\trte_iova_t io_addr;\n+\n+\tif (unlikely(eswitch_dev->txq[qid].state != CNXK_ESWITCH_QUEUE_STATE_STARTED))\n+\t\treturn 0;\n+\n+\tlmt_base = sq->roc_nix->lmt_base;\n+\tio_addr = sq->io_addr;\n+\taura_handle = rq->aura_handle;\n+\t/* Get LMT base address and LMT ID as per thread ID */\n+\tlmt_id = roc_plt_control_lmt_id_get();\n+\tlmt_base += ((uint64_t)lmt_id << ROC_LMT_LINE_SIZE_LOG2);\n+\t/* Double word minus 1: LMTST size-1 in units of 128 bits */\n+\t/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */\n+\tdw_m1 = cn10k_nix_tx_ext_subs(flags) + 1;\n+\n+\tmemset(cmd, 0, sizeof(cmd));\n+\tsend_hdr = (struct nix_send_hdr_s *)&cmd[0];\n+\tsend_hdr->w0.sizem1 = dw_m1;\n+\tsend_hdr->w0.sq = sq->qid;\n+\n+\tif (dw_m1 >= 2) {\n+\t\tsend_hdr_ext = (struct nix_send_ext_s *)&cmd[2];\n+\t\tsend_hdr_ext->w0.subdc = NIX_SUBDC_EXT;\n+\t\tif (flags & NIX_TX_OFFLOAD_VLAN_QINQ_F) {\n+\t\t\tsend_hdr_ext->w1.vlan0_ins_ena = true;\n+\t\t\t/* 2B before end of l2 header */\n+\t\t\tsend_hdr_ext->w1.vlan0_ins_ptr = 12;\n+\t\t\tsend_hdr_ext->w1.vlan0_ins_tci = 0;\n+\t\t}\n+\t\tsg = (union nix_send_sg_s *)&cmd[4];\n+\t} else {\n+\t\tsg = (union nix_send_sg_s *)&cmd[2];\n+\t}\n+\n+\tsg->subdc = NIX_SUBDC_SG;\n+\tsg->segs = 1;\n+\tsg->ld_type = NIX_SENDLDTYPE_LDD;\n+\n+\t/* Tx */\n+\tfc_pkts = ((int64_t)sq->nb_sqb_bufs_adj - *((uint64_t *)sq->fc)) << sq->sqes_per_sqb_log2;\n+\n+\tif (fc_pkts < 0)\n+\t\tnb_tx = 0;\n+\telse\n+\t\tnb_tx = PLT_MIN(nb_xmit, (uint64_t)fc_pkts);\n+\n+\tfor (pkt = 0; pkt < nb_tx; pkt++) {\n+\t\tsend_hdr->w0.total = pkts[pkt]->pkt_len;\n+\t\tif (pkts[pkt]->pool) {\n+\t\t\taura_handle = pkts[pkt]->pool->pool_id;\n+\t\t\tsend_hdr->w0.aura = roc_npa_aura_handle_to_aura(aura_handle);\n+\t\t} else {\n+\t\t\tsend_hdr->w0.df = 1;\n+\t\t}\n+\t\tif (dw_m1 >= 2 && flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)\n+\t\t\tsend_hdr_ext->w1.vlan0_ins_tci = vlan_tci;\n+\t\tsg->seg1_size = pkts[pkt]->pkt_len;\n+\t\t*(plt_iova_t *)(sg + 1) = rte_mbuf_data_iova(pkts[pkt]);\n+\n+\t\tplt_esw_dbg(\"Transmitting pkt %d (%p) vlan tci %x on sq %d esw qid %d\", pkt,\n+\t\t\t pkts[pkt], vlan_tci, sq->qid, qid);\n+\t\tif (roc_model_is_cn9k()) {\n+\t\t\tnix_cn9k_xmit_one(cmd, sq->lmt_addr, sq->io_addr);\n+\t\t} else {\n+\t\t\tcn10k_nix_xmit_mv_lmt_base(lmt_base, cmd, flags);\n+\t\t\t/* PA<6:4> = LMTST size-1 in units of 128 bits. Size of the first LMTST in\n+\t\t\t * burst.\n+\t\t\t */\n+\t\t\tpa = io_addr | (dw_m1 << 4);\n+\t\t\tdata &= ~0x7ULL;\n+\t\t\t/*<15:12> = CNTM1: Count minus one of LMTSTs in the burst */\n+\t\t\tdata = (0ULL << 12);\n+\t\t\t/* *<10:0> = LMT_ID: Identifies which LMT line is used for the first LMTST\n+\t\t\t */\n+\t\t\tdata |= (uint64_t)lmt_id;\n+\n+\t\t\t/* STEOR0 */\n+\t\t\troc_lmt_submit_steorl(data, pa);\n+\t\t\trte_io_wmb();\n+\t\t}\n+\t}\n+\n+\treturn nb_tx;\n+}\n+\n+uint16_t\n+cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,\n+\t\t\t struct rte_mbuf **pkts, uint16_t nb_pkts)\n+{\n+\tstruct roc_nix_rq *rq = &eswitch_dev->rxq[qid].rqs;\n+\tstruct roc_nix_cq *cq = &eswitch_dev->cxq[qid].cqs;\n+\tconst union nix_rx_parse_u *rx;\n+\tstruct nix_cqe_hdr_s *cqe;\n+\tuint64_t pkt = 0, nb_rx;\n+\tstruct rte_mbuf *mbuf;\n+\tuint64_t wdata;\n+\tuint32_t qmask;\n+\tuintptr_t desc;\n+\tuint32_t head;\n+\n+\tif (unlikely(eswitch_dev->rxq[qid].state != CNXK_ESWITCH_QUEUE_STATE_STARTED))\n+\t\treturn 0;\n+\n+\twdata = cq->wdata;\n+\tqmask = cq->qmask;\n+\tdesc = (uintptr_t)cq->desc_base;\n+\tnb_rx = eswitch_nix_rx_nb_pkts(cq, wdata, qmask);\n+\tnb_rx = RTE_MIN(nb_rx, nb_pkts);\n+\thead = cq->head;\n+\n+\t/* Nothing to receive */\n+\tif (!nb_rx)\n+\t\treturn 0;\n+\n+\t/* Rx */\n+\tfor (pkt = 0; pkt < nb_rx; pkt++) {\n+\t\t/* Prefetch N desc ahead */\n+\t\trte_prefetch_non_temporal((void *)(desc + (CQE_SZ((head + 2) & qmask))));\n+\t\tcqe = (struct nix_cqe_hdr_s *)(desc + CQE_SZ(head));\n+\t\trx = (const union nix_rx_parse_u *)((const uint64_t *)cqe + 1);\n+\n+\t\t/* Skip\tQE, NIX_RX_PARSE_S and SG HDR(9 DWORDs) and peek buff addr */\n+\t\tmbuf = eswitch_nix_get_mbuf_from_cqe(cqe, rq->first_skip);\n+\t\tmbuf->pkt_len = rx->pkt_lenm1 + 1;\n+\t\tmbuf->data_len = rx->pkt_lenm1 + 1;\n+\t\tmbuf->data_off = 128;\n+\t\t/* Rx parse to capture vlan info */\n+\t\tif (rx->vtag0_valid)\n+\t\t\tmbuf->vlan_tci = rx->vtag0_tci;\n+\t\t/* Populate RSS hash */\n+\t\tmbuf->hash.rss = cqe->tag;\n+\t\tmbuf->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;\n+\t\tpkts[pkt] = mbuf;\n+\t\troc_prefetch_store_keep(mbuf);\n+\t\tplt_esw_dbg(\"Packet %d rec on queue %d esw qid %d hash %x mbuf %p vlan tci %d\",\n+\t\t\t (uint32_t)pkt, rq->qid, qid, mbuf->hash.rss, mbuf, mbuf->vlan_tci);\n+\t\thead++;\n+\t\thead &= qmask;\n+\t}\n+\n+\t/* Free all the CQs that we've processed */\n+\trte_write64_relaxed((wdata | nb_rx), (void *)cq->door);\n+\tcq->head = head;\n+\n+\treturn nb_rx;\n+}\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 488e89253d..7121845dc6 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -31,6 +31,7 @@ sources = files(\n 'cnxk_eswitch.c',\n 'cnxk_eswitch_devargs.c',\n 'cnxk_eswitch_flow.c',\n+ 'cnxk_eswitch_rxtx.c',\n 'cnxk_link.c',\n 'cnxk_lookup.c',\n 'cnxk_ptp.c',\n", "prefixes": [ "v3", "09/23" ] }