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GET /api/patches/136163/?format=api
{ "id": 136163, "url": "http://patches.dpdk.org/api/patches/136163/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240125133043.575860-19-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240125133043.575860-19-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240125133043.575860-19-michaelba@nvidia.com", "date": "2024-01-25T13:30:38", "name": "[v2,18/23] net/mlx5/hws: support GENEVE options header", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5a29d4d2a74aecbcd914b3f636e28703cd7bf4f4", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240125133043.575860-19-michaelba@nvidia.com/mbox/", "series": [ { "id": 30916, "url": "http://patches.dpdk.org/api/series/30916/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30916", "date": "2024-01-25T13:30:20", "name": "net/mlx5: support Geneve and options for HWS", "version": 2, "mbox": "http://patches.dpdk.org/series/30916/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/136163/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/136163/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E246D439C1;\n\tThu, 25 Jan 2024 14:33:44 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 18C4142E8F;\n\tThu, 25 Jan 2024 14:31:51 +0100 (CET)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam02on2051.outbound.protection.outlook.com [40.107.212.51])\n by mails.dpdk.org (Postfix) with ESMTP id 4369F42E7F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>, Alex Vesker <valex@nvidia.com>", "Subject": "[PATCH v2 18/23] net/mlx5/hws: support GENEVE options header", "Date": "Thu, 25 Jan 2024 15:30:38 +0200", "Message-ID": "<20240125133043.575860-19-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240125133043.575860-1-michaelba@nvidia.com>", "References": "<20231203112543.844014-1-michaelba@nvidia.com>\n <20240125133043.575860-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EDD7:EE_|PH7PR12MB9066:EE_", "X-MS-Office365-Filtering-Correlation-Id": "61b6b559-e7c9-4673-5f28-08dc1da9f80e", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n aMmxZUTVn0lVfwpeywXDLDADmgQ4Uib83+65BeN/XKWNQin0zjpV3Tuqt+CpWKEQumBqwvxqui5wBd8sLPF7fuQHjx2jdclUhLkqQ8F2agJCKi24DmJxokhmwsqlG+x+j46Z1yN3NwZgzFUIDgOvmdX7qw3YkRW2jpoHril+uS+G4MLrDTOSXzOpmIrfetdRAv44kD4jSNmASd5S8OQj8rEDuWNzSyEPb6JdU8qOwWwz/O7O7t6v3UA4OrNwnPj5kUeO23aBjGj2PJKKcrpm8BOGaR+SaUrZch7Is3Bfgbld9RCCbPfUkvGtldig5Jmgba90NXH7eTN3gbFWRMkSCkwM07N3nxjgW/nM28c6rYUnEkZYsOK4KG4QloeGIcGZgLrgwv9xZOdz9GgH8nAyNAn+voQWHtlndfRNkCBkusrurNqBk2tJwWmUaV23EK5v1ZO8JLEIynBuVowo8PNWTYcuGk5kiyAoYSIXyeywYiyt5K0vGPgeYymUUZ8UICC5B3sncv7JcgXiZiGhmJa/b9MEVpzPm/1ekfiyEvLt+ofMqnW1jCX/twQbCLUoSRDXT7N/u+Bj4+ZdxqTzqI2p191S5XzbVLrnDGD/t1JjzbWvP5vp81sEz+P1x7z4BVU/mUYHkqG+aBRKZo4GpDEztEKafpmoVRZGbYgSy2+GEZB1SUAXJ9DshZhA0yJXsVyDLciGcxZ2/nbJmaRifHSObTMEkCj61PMSwvFa03pKIhw=", "X-Forefront-Antispam-Report": "CIP:216.228.118.233; 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Ip=[216.228.118.233];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EDD7.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB9066", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Alex Vesker <valex@nvidia.com>\n\nAdd support for matching multiple GENEVE options. Options\nheader introduces new complexities since there can be more\nthan one GENEVE option. This requires us to track the total\nDWs used for matching. Current code supports 8DWs for data\nincluding type, class, length. There is also an optimization\nto use a special OK bit to reduce the use of limited data DWs.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 147 ++++++++++++++++++++++++--\n drivers/net/mlx5/hws/mlx5dr_definer.h | 24 +++++\n 2 files changed, 165 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 7c0ce805f1..79d98bbf78 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -118,6 +118,8 @@ struct mlx5dr_definer_conv_data {\n \tuint8_t relaxed;\n \tuint8_t tunnel;\n \tuint8_t mpls_idx;\n+\tuint8_t geneve_opt_ok_idx;\n+\tuint8_t geneve_opt_data_idx;\n \tenum rte_flow_item_type last_item;\n };\n \n@@ -702,6 +704,29 @@ mlx5dr_definer_geneve_vni_set(struct mlx5dr_definer_fc *fc,\n \tmemcpy(tag + fc->byte_off, v->vni, sizeof(v->vni));\n }\n \n+static void\n+mlx5dr_definer_geneve_opt_ctrl_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t const void *item_spec,\n+\t\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_geneve_opt *v = item_spec;\n+\tuint32_t dw0 = 0;\n+\n+\tdw0 |= v->option_type << __mlx5_dw_bit_off(header_geneve_opt, type);\n+\tdw0 |= rte_cpu_to_be_16(v->option_class) << __mlx5_dw_bit_off(header_geneve_opt, class);\n+\tDR_SET(tag, dw0, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n+static void\n+mlx5dr_definer_geneve_opt_data_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t const void *item_spec,\n+\t\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_geneve_opt *v = item_spec;\n+\n+\tDR_SET_BE32(tag, v->data[fc->extra_data], fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n static void\n mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc,\n \t\t\t const void *item_spec,\n@@ -1356,7 +1381,6 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd,\n \tstruct mlx5dr_cmd_query_caps *caps = cd->ctx->caps;\n \tconst struct rte_flow_item_ethdev *m = item->mask;\n \tstruct mlx5dr_definer_fc *fc;\n-\tuint8_t bit_offset = 0;\n \n \tif (m->port_id) {\n \t\tif (!caps->wire_regc_mask) {\n@@ -1365,16 +1389,13 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd,\n \t\t\treturn rte_errno;\n \t\t}\n \n-\t\twhile (!(caps->wire_regc_mask & (1 << bit_offset)))\n-\t\t\tbit_offset++;\n-\n \t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VPORT_REG_C_0];\n \t\tfc->item_idx = item_idx;\n \t\tfc->tag_set = &mlx5dr_definer_vport_set;\n \t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n \t\tDR_CALC_SET_HDR(fc, registers, register_c_0);\n-\t\tfc->bit_off = bit_offset;\n-\t\tfc->bit_mask = caps->wire_regc_mask >> bit_offset;\n+\t\tfc->bit_off = __builtin_ctz(caps->wire_regc_mask);\n+\t\tfc->bit_mask = caps->wire_regc_mask >> fc->bit_off;\n \t} else {\n \t\tDR_LOG(ERR, \"Pord ID item mask must specify ID mask\");\n \t\trte_errno = EINVAL;\n@@ -2314,6 +2335,116 @@ mlx5dr_definer_conv_item_geneve(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_geneve_opt(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t\t struct rte_flow_item *item,\n+\t\t\t\t int item_idx)\n+{\n+\tconst struct rte_flow_item_geneve_opt *m = item->mask;\n+\tconst struct rte_flow_item_geneve_opt *v = item->spec;\n+\tstruct mlx5_hl_data *hl_ok_bit, *hl_dws;\n+\tstruct mlx5dr_definer_fc *fc;\n+\tuint8_t num_of_dws, i;\n+\tbool ok_bit_on_class;\n+\tint ret;\n+\n+\tif (!m || !(m->option_class || m->option_type || m->data))\n+\t\treturn 0;\n+\n+\tif (!v || m->option_type != 0xff) {\n+\t\tDR_LOG(ERR, \"Cannot match geneve opt without valid opt type\");\n+\t\tgoto out_not_supp;\n+\t}\n+\n+\tif (m->option_class && m->option_class != RTE_BE16(UINT16_MAX)) {\n+\t\tDR_LOG(ERR, \"Geneve option class has invalid mask\");\n+\t\tgoto out_not_supp;\n+\t}\n+\n+\tret = mlx5_get_geneve_hl_data(cd->ctx,\n+\t\t\t\t v->option_type,\n+\t\t\t\t v->option_class,\n+\t\t\t\t &hl_ok_bit,\n+\t\t\t\t &num_of_dws,\n+\t\t\t\t &hl_dws,\n+\t\t\t\t &ok_bit_on_class);\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Geneve opt type and class %d not supported\", v->option_type);\n+\t\tgoto out_not_supp;\n+\t}\n+\n+\tif (!ok_bit_on_class && m->option_class) {\n+\t\t/* DW0 is used, we will match type, class */\n+\t\tif (!num_of_dws || hl_dws[0].dw_mask != UINT32_MAX) {\n+\t\t\tDR_LOG(ERR, \"Geneve opt type %d DW0 not supported\", v->option_type);\n+\t\t\tgoto out_not_supp;\n+\t\t}\n+\n+\t\tif (MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_0 + cd->geneve_opt_data_idx >\n+\t\t MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_7) {\n+\t\t\tDR_LOG(ERR, \"Max match geneve opt DWs reached\");\n+\t\t\tgoto out_not_supp;\n+\t\t}\n+\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_0 + cd->geneve_opt_data_idx++];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_geneve_opt_ctrl_set;\n+\t\tfc->byte_off = hl_dws[0].dw_offset * DW_SIZE;\n+\t\tfc->bit_mask = UINT32_MAX;\n+\t} else {\n+\t\t/* DW0 is not used, we must verify geneve opt type exists in packet */\n+\t\tif (!hl_ok_bit->dw_mask) {\n+\t\t\tDR_LOG(ERR, \"Geneve opt OK bits not supported\");\n+\t\t\tgoto out_not_supp;\n+\t\t}\n+\n+\t\tif (MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_0 + cd->geneve_opt_ok_idx >\n+\t\t MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_7) {\n+\t\t\tDR_LOG(ERR, \"Max match geneve opt reached\");\n+\t\t\tgoto out_not_supp;\n+\t\t}\n+\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_0 + cd->geneve_opt_ok_idx++];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ones_set;\n+\t\tfc->byte_off = hl_ok_bit->dw_offset * DW_SIZE +\n+\t\t\t\t__builtin_clz(hl_ok_bit->dw_mask) / 8;\n+\t\tfc->bit_off = __builtin_ctz(hl_ok_bit->dw_mask);\n+\t\tfc->bit_mask = 0x1;\n+\t}\n+\n+\tfor (i = 1; i < num_of_dws; i++) {\n+\t\t/* Process each valid geneve option data DW1..N */\n+\t\tif (!m->data[i - 1])\n+\t\t\tcontinue;\n+\n+\t\tif (hl_dws[i].dw_mask != UINT32_MAX) {\n+\t\t\tDR_LOG(ERR, \"Matching Geneve opt data[%d] not supported\", i - 1);\n+\t\t\tgoto out_not_supp;\n+\t\t}\n+\n+\t\tif (MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_0 + cd->geneve_opt_data_idx >\n+\t\t MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_7) {\n+\t\t\tDR_LOG(ERR, \"Max match geneve options DWs reached\");\n+\t\t\tgoto out_not_supp;\n+\t\t}\n+\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_0 + cd->geneve_opt_data_idx++];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_geneve_opt_data_set;\n+\t\tfc->byte_off = hl_dws[i].dw_offset * DW_SIZE;\n+\t\tfc->bit_mask = m->data[i - 1];\n+\t\t/* Use extra_data for data[] set offset */\n+\t\tfc->extra_data = i - 1;\n+\t}\n+\n+\treturn 0;\n+\n+out_not_supp:\n+\trte_errno = ENOTSUP;\n+\treturn rte_errno;\n+}\n+\n static int\n mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,\n \t\t\t struct mlx5dr_definer_fc *fc,\n@@ -2756,6 +2887,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\tret = mlx5dr_definer_conv_item_geneve(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_LAYER_GENEVE;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GENEVE_OPT:\n+\t\t\tret = mlx5dr_definer_conv_item_geneve_opt(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_LAYER_GENEVE_OPT;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n \t\t\tret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_ITEM_IB_BTH;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex eb70dcd39d..ced9d9da13 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -146,6 +146,22 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS2_I,\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS3_I,\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS4_I,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_0,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_1,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_2,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_3,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_4,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_5,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_6,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_7,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_0,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_1,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_2,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_3,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_4,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_5,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_6,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_7,\n \tMLX5DR_DEFINER_FNAME_IB_L4_OPCODE,\n \tMLX5DR_DEFINER_FNAME_IB_L4_QPN,\n \tMLX5DR_DEFINER_FNAME_IB_L4_A,\n@@ -171,6 +187,7 @@ enum mlx5dr_definer_type {\n struct mlx5dr_definer_fc {\n \tuint8_t item_idx;\n \tuint8_t is_range;\n+\tuint16_t extra_data;\n \tuint32_t byte_off;\n \tint bit_off;\n \tuint32_t bit_mask;\n@@ -646,6 +663,13 @@ struct mlx5_ifc_header_geneve_bits {\n \tu8 reserved_at_38[0x8];\n };\n \n+struct mlx5_ifc_header_geneve_opt_bits {\n+\tu8 class[0x10];\n+\tu8 type[0x8];\n+\tu8 reserved[0x3];\n+\tu8 len[0x5];\n+};\n+\n struct mlx5_ifc_header_icmp_bits {\n \tunion {\n \t\tu8 icmp_dw1[0x20];\n", "prefixes": [ "v2", "18/23" ] }