Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/135834/?format=api
{ "id": 135834, "url": "http://patches.dpdk.org/api/patches/135834/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240110222822.832395-2-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240110222822.832395-2-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240110222822.832395-2-nicolas.chautru@intel.com", "date": "2024-01-10T22:28:22", "name": "[v1,1/1] baseband/acc: refactor of DMA response", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2e5a22ca7dac96abbbec3d013a404312c1986945", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240110222822.832395-2-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 30779, "url": "http://patches.dpdk.org/api/series/30779/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30779", "date": "2024-01-10T22:28:21", "name": "baseband/acc: refactor of DMA response", "version": 1, "mbox": "http://patches.dpdk.org/series/30779/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135834/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/135834/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4BDEC43887;\n\tWed, 10 Jan 2024 23:35:50 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 38E9A402EB;\n\tWed, 10 Jan 2024 23:35:45 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [198.175.65.13])\n by mails.dpdk.org (Postfix) with ESMTP id 02C4340276\n for <dev@dpdk.org>; Wed, 10 Jan 2024 23:35:42 +0100 (CET)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 10 Jan 2024 14:35:41 -0800", "from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..)\n ([10.233.181.123])\n by FMSMGA003.fm.intel.com with ESMTP; 10 Jan 2024 14:35:41 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1704926143; x=1736462143;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=GHQQJNfdMXR0PshN1y5UU7rfvxXQyNkLUtpCtOuQtdE=;\n b=HJZnvTIeG5vzHc9TnAQbeNPobkyvqqFjt9FkO+3L0Kq6rXgURRdQBV3y\n jZK1bMlYxN2qLEdj08ix3wQqJ53ZMLzsrxTGC5re6qbfX6gK9ex2hdqaR\n fFKSX5LvHi+vLzPNzWKGoTtigJDnTYUe8BwZRVonTRBB5C/FVOSOhpdb2\n Oe0NnbJpHpLNfY1z32djAsLYBBRhcgCvm94I6yU6byHhoH1j3CeZe5iTS\n wy9rfUK54vOGyD2LYLkJvFNBlHfmBFEkHC70ZabfIijmVSy9wFwWRlY3a\n bI5LVdp+06iBWqUJXMhadOAnFMV3QXLn45ajdgQXFweK5xuKy7SbNVTw5 w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10949\"; a=\"5755279\"", "E=Sophos;i=\"6.04,184,1695711600\";\n d=\"scan'208\";a=\"5755279\"", "E=McAfee;i=\"6600,9927,10949\"; a=\"872809912\"", "E=Sophos;i=\"6.04,184,1695711600\"; d=\"scan'208\";a=\"872809912\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tmaxime.coquelin@redhat.com", "Cc": "hernan.vargas@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v1 1/1] baseband/acc: refactor of DMA response", "Date": "Wed, 10 Jan 2024 22:28:22 +0000", "Message-Id": "<20240110222822.832395-2-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240110222822.832395-1-nicolas.chautru@intel.com>", "References": "<20240110222822.832395-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Using common code for the status update\nduring dequeue operation in the VRB PMD.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/acc/rte_vrb_pmd.c | 139 +++++++++--------------------\n 1 file changed, 40 insertions(+), 99 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c\nindex 686e086a5c..06d8645d20 100644\n--- a/drivers/baseband/acc/rte_vrb_pmd.c\n+++ b/drivers/baseband/acc/rte_vrb_pmd.c\n@@ -3076,6 +3076,33 @@ vrb_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,\n \t\treturn vrb_enqueue_ldpc_dec_cb(q_data, ops, num);\n }\n \n+/* Update the operation status when dequeuing for any operation type. */\n+static inline void\n+vrb_update_dequeued_operation(union acc_dma_desc *desc, union acc_dma_rsp_desc rsp, int *op_status,\n+\tuint32_t *aq_dequeued, bool clear_rsp, bool clear_opstatus)\n+{\n+\trte_bbdev_log_debug(\"Resp. desc %p: %x\", desc, rsp.val);\n+\n+\t/* Set status based on DMA response. */\n+\tif (clear_opstatus)\n+\t\t*op_status = 0;\n+\t*op_status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);\n+\t*op_status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n+\t*op_status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n+\t*op_status |= ((rsp.engine_hung) ? (1 << RTE_BBDEV_ENGINE_ERROR) : 0);\n+\n+\tif (desc->req.last_desc_in_batch) {\n+\t\t(*aq_dequeued)++;\n+\t\tdesc->req.last_desc_in_batch = 0;\n+\t}\n+\n+\tif (clear_rsp) {\n+\t\t/* Clear response explictly. */\n+\t\tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n+\t\tdesc->rsp.add_info_0 = 0; /* Reserved bits. */\n+\t\tdesc->rsp.add_info_1 = 0; /* Reserved bits. */\n+\t}\n+}\n \n /* Dequeue one encode operations from device in CB mode. */\n static inline int\n@@ -3102,25 +3129,11 @@ vrb_dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,\n \t\treturn -1;\n \n \trsp.val = atom_desc.rsp.val;\n-\trte_bbdev_log_debug(\"Resp. desc %p: %x\", desc, rsp.val);\n \n \t/* Dequeue. */\n \top = desc->req.op_addr;\n \n-\t/* Clearing status, it will be set based on response. */\n-\top->status = 0;\n-\top->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);\n-\top->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n-\top->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n-\top->status |= ((rsp.engine_hung) ? (1 << RTE_BBDEV_ENGINE_ERROR) : 0);\n-\n-\tif (desc->req.last_desc_in_batch) {\n-\t\t(*aq_dequeued)++;\n-\t\tdesc->req.last_desc_in_batch = 0;\n-\t}\n-\tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n-\tdesc->rsp.add_info_0 = 0; /* Reserved bits. */\n-\tdesc->rsp.add_info_1 = 0; /* Reserved bits. */\n+\tvrb_update_dequeued_operation(desc, rsp, &op->status, aq_dequeued, true, true);\n \n \tref_op[0] = op;\n \tcontext_ptrs = q->companion_ring_addr + desc_idx;\n@@ -3151,25 +3164,11 @@ vrb2_dequeue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **r\n \t\treturn -1;\n \n \trsp.val = atom_desc.rsp.val;\n-\trte_bbdev_log_debug(\"Resp. desc %p: %x\", desc, rsp.val);\n \n \t/* Dequeue. */\n \top = desc->req.op_addr;\n \n-\t/* Clearing status, it will be set based on response. */\n-\top->status = 0;\n-\top->status |= rsp.input_err << RTE_BBDEV_DATA_ERROR;\n-\top->status |= rsp.dma_err << RTE_BBDEV_DRV_ERROR;\n-\top->status |= rsp.fcw_err << RTE_BBDEV_DRV_ERROR;\n-\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n-\n-\tif (desc->req.last_desc_in_batch) {\n-\t\t(*aq_dequeued)++;\n-\t\tdesc->req.last_desc_in_batch = 0;\n-\t}\n-\tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n-\tdesc->rsp.add_info_0 = 0; /* Reserved bits. */\n-\tdesc->rsp.add_info_1 = 0; /* Reserved bits. */\n+\tvrb_update_dequeued_operation(desc, rsp, &op->status, aq_dequeued, true, true);\n \n \t/* One op was successfully dequeued */\n \tref_op[0] = op;\n@@ -3223,20 +3222,9 @@ vrb_dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op,\n \t\tdesc = acc_desc_tail(q, *dequeued_descs);\n \t\tatom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED);\n \t\trsp.val = atom_desc.rsp.val;\n-\t\trte_bbdev_log_debug(\"Resp. desc %p: %x\", desc, rsp.val);\n \n-\t\top->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);\n-\t\top->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n-\t\top->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n-\t\top->status |= ((rsp.engine_hung) ? (1 << RTE_BBDEV_ENGINE_ERROR) : 0);\n+\t\tvrb_update_dequeued_operation(desc, rsp, &op->status, aq_dequeued, true, false);\n \n-\t\tif (desc->req.last_desc_in_batch) {\n-\t\t\t(*aq_dequeued)++;\n-\t\t\tdesc->req.last_desc_in_batch = 0;\n-\t\t}\n-\t\tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n-\t\tdesc->rsp.add_info_0 = 0;\n-\t\tdesc->rsp.add_info_1 = 0;\n \t\t(*dequeued_descs)++;\n \t\tcurrent_dequeued_descs++;\n \t\ti++;\n@@ -3265,17 +3253,11 @@ vrb_dequeue_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,\n \t\treturn -1;\n \n \trsp.val = atom_desc.rsp.val;\n-\trte_bbdev_log_debug(\"Resp. desc %p: %x\\n\", desc, rsp.val);\n \n \t/* Dequeue. */\n \top = desc->req.op_addr;\n \n-\t/* Clearing status, it will be set based on response. */\n-\top->status = 0;\n-\top->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);\n-\top->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n-\top->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n-\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n+\tvrb_update_dequeued_operation(desc, rsp, &op->status, aq_dequeued, false, true);\n \n \tif (op->status != 0) {\n \t\t/* These errors are not expected. */\n@@ -3287,11 +3269,7 @@ vrb_dequeue_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,\n \tif (!op->status)\n \t\top->status |= rsp.crc_status << RTE_BBDEV_CRC_ERROR;\n \top->turbo_dec.iter_count = (uint8_t) rsp.iter_cnt;\n-\t/* Check if this is the last desc in batch (Atomic Queue). */\n-\tif (desc->req.last_desc_in_batch) {\n-\t\t(*aq_dequeued)++;\n-\t\tdesc->req.last_desc_in_batch = 0;\n-\t}\n+\n \tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n \tdesc->rsp.add_info_0 = 0;\n \tdesc->rsp.add_info_1 = 0;\n@@ -3325,12 +3303,9 @@ vrb_dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,\n \t/* Dequeue. */\n \top = desc->req.op_addr;\n \n-\t/* Clearing status, it will be set based on response. */\n-\top->status = 0;\n-\top->status |= rsp.input_err << RTE_BBDEV_DATA_ERROR;\n-\top->status |= rsp.dma_err << RTE_BBDEV_DRV_ERROR;\n-\top->status |= rsp.fcw_err << RTE_BBDEV_DRV_ERROR;\n-\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n+\tvrb_update_dequeued_operation(desc, rsp, &op->status, aq_dequeued, false, true);\n+\n+\t/* Additional op status update for LDPC Decoder. */\n \tif (op->status != 0)\n \t\tq_data->queue_stats.dequeue_err_count++;\n \n@@ -3349,12 +3324,6 @@ vrb_dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,\n \tif (op->status & (1 << RTE_BBDEV_DRV_ERROR))\n \t\tvrb_check_ir(q->d);\n \n-\t/* Check if this is the last desc in batch (Atomic Queue). */\n-\tif (desc->req.last_desc_in_batch) {\n-\t\t(*aq_dequeued)++;\n-\t\tdesc->req.last_desc_in_batch = 0;\n-\t}\n-\n \tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n \tdesc->rsp.add_info_0 = 0;\n \tdesc->rsp.add_info_1 = 0;\n@@ -3409,10 +3378,7 @@ vrb_dequeue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op **ref_op,\n \t\t\t\trsp.val, desc->rsp.add_info_0,\n \t\t\t\tdesc->rsp.add_info_1);\n \n-\t\top->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0);\n-\t\top->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n-\t\top->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0);\n-\t\top->status |= ((rsp.engine_hung) ? (1 << RTE_BBDEV_ENGINE_ERROR) : 0);\n+\t\tvrb_update_dequeued_operation(desc, rsp, &op->status, aq_dequeued, false, false);\n \n \t\tif (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK))\n \t\t\ttb_crc_check ^= desc->rsp.add_info_1;\n@@ -3427,11 +3393,6 @@ vrb_dequeue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op **ref_op,\n \t\t\top->turbo_dec.iter_count = RTE_MAX((uint8_t) rsp.iter_cnt,\n \t\t\t\t\top->turbo_dec.iter_count);\n \n-\t\t/* Check if this is the last desc in batch (Atomic Queue). */\n-\t\tif (desc->req.last_desc_in_batch) {\n-\t\t\t(*aq_dequeued)++;\n-\t\t\tdesc->req.last_desc_in_batch = 0;\n-\t\t}\n \t\tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n \t\tdesc->rsp.add_info_0 = 0;\n \t\tdesc->rsp.add_info_1 = 0;\n@@ -3843,25 +3804,14 @@ vrb_dequeue_fft_one_op(struct rte_bbdev_queue_data *q_data,\n \t/* Dequeue. */\n \top = desc->req.op_addr;\n \n-\t/* Clearing status, it will be set based on response. */\n-\top->status = 0;\n-\top->status |= rsp.input_err << RTE_BBDEV_DATA_ERROR;\n-\top->status |= rsp.dma_err << RTE_BBDEV_DRV_ERROR;\n-\top->status |= rsp.fcw_err << RTE_BBDEV_DRV_ERROR;\n-\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n+\tvrb_update_dequeued_operation(desc, rsp, &op->status, aq_dequeued, true, true);\n+\n \tif (op->status != 0)\n \t\tq_data->queue_stats.dequeue_err_count++;\n \n \tif (op->status & (1 << RTE_BBDEV_DRV_ERROR))\n \t\tvrb_check_ir(q->d);\n \n-\t/* Check if this is the last desc in batch (Atomic Queue). */\n-\tif (desc->req.last_desc_in_batch) {\n-\t\t(*aq_dequeued)++;\n-\t\tdesc->req.last_desc_in_batch = 0;\n-\t}\n-\tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n-\tdesc->rsp.add_info_0 = 0;\n \t*ref_op = op;\n \t/* One CB (op) was successfully dequeued. */\n \treturn 1;\n@@ -4206,10 +4156,8 @@ dequeue_mldts_one_op(struct rte_bbdev_queue_data *q_data,\n \t\tdesc = q->ring_addr + ((q->sw_ring_tail + dequeued_ops + i) & q->sw_ring_wrap_mask);\n \t\tatom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED);\n \t\trsp.val = atom_desc.rsp.val;\n-\t\top->status |= rsp.input_err << RTE_BBDEV_DATA_ERROR;\n-\t\top->status |= rsp.dma_err << RTE_BBDEV_DRV_ERROR;\n-\t\top->status |= rsp.fcw_err << RTE_BBDEV_DRV_ERROR;\n-\t\top->status |= rsp.engine_hung << RTE_BBDEV_ENGINE_ERROR;\n+\n+\t\tvrb_update_dequeued_operation(desc, rsp, &op->status, aq_dequeued, true, false);\n \t}\n \n \tif (op->status != 0)\n@@ -4217,13 +4165,6 @@ dequeue_mldts_one_op(struct rte_bbdev_queue_data *q_data,\n \tif (op->status & (1 << RTE_BBDEV_DRV_ERROR))\n \t\tvrb_check_ir(q->d);\n \n-\t/* Check if this is the last desc in batch (Atomic Queue). */\n-\tif (desc->req.last_desc_in_batch) {\n-\t\t(*aq_dequeued)++;\n-\t\tdesc->req.last_desc_in_batch = 0;\n-\t}\n-\tdesc->rsp.val = ACC_DMA_DESC_TYPE;\n-\tdesc->rsp.add_info_0 = 0;\n \t*ref_op = op;\n \n \treturn descs_in_op;\n", "prefixes": [ "v1", "1/1" ] }