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GET /api/patches/135758/?format=api
{ "id": 135758, "url": "http://patches.dpdk.org/api/patches/135758/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240105211237.394105-2-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240105211237.394105-2-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240105211237.394105-2-qi.z.zhang@intel.com", "date": "2024-01-05T21:12:35", "name": "[v3,1/3] net/ice: hide port and TC layer in Tx sched tree", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "566b2cfd994928c935370d115e6f356d0eddfa7f", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240105211237.394105-2-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 30742, "url": "http://patches.dpdk.org/api/series/30742/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30742", "date": "2024-01-05T21:12:34", "name": "net/ice: simplified to 3 layer Tx scheduler", "version": 3, "mbox": "http://patches.dpdk.org/series/30742/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135758/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/135758/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 07CE74383C;\n\tFri, 5 Jan 2024 13:45:12 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4538A4064E;\n\tFri, 5 Jan 2024 13:45:09 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 8261C402BF\n for <dev@dpdk.org>; Fri, 5 Jan 2024 13:45:05 +0100 (CET)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 Jan 2024 04:45:05 -0800", "from dpdk-qzhan15-test02.sh.intel.com ([10.67.119.16])\n by orsmga003.jf.intel.com with ESMTP; 05 Jan 2024 04:45:03 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1704458705; x=1735994705;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=NFKO0PKD5v1Q+TkpvxCwlMiSCsUuVltlkn957i+iXcw=;\n b=Q6LK2AAmd3xI2sRMDfxoNgWEfCvsbIPdwlsCzZhtbxWnrP4xmvtzW+5t\n wnH4qxmEtDfAMlXUTOuo3mN9G+kUbPL/RQttkUhhZuOKqf9IIj7IR8DHZ\n DVoQ4uRwR60CxhjvUhyk0PVtCNSJosBOlKLeWtTCfP+bp7dade5Yrm+TU\n nveC9v6ECCp79Gazf4YhFt1g1s4mG7e2D9TtASv+S4sgCVoeTUD458gT7\n 3wohHggrqkOEfNwA9qEw35fa2lhfzL9Qe3drRYeEhI3ghRoouKLhomnHI\n JZwgAifUwqqMK0o+ooNEolEsKuB/N79+dUT3JtdMFeWH87cgEAwdGHP08 A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10943\"; a=\"376988422\"", "E=Sophos;i=\"6.04,333,1695711600\"; d=\"scan'208\";a=\"376988422\"", "E=McAfee;i=\"6600,9927,10943\"; a=\"730468550\"", "E=Sophos;i=\"6.04,333,1695711600\"; d=\"scan'208\";a=\"730468550\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com,\n\twenjun1.wu@intel.com", "Cc": "dev@dpdk.org,\n\tQi Zhang <qi.z.zhang@intel.com>", "Subject": "[PATCH v3 1/3] net/ice: hide port and TC layer in Tx sched tree", "Date": "Fri, 5 Jan 2024 16:12:35 -0500", "Message-Id": "<20240105211237.394105-2-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20240105211237.394105-1-qi.z.zhang@intel.com>", "References": "<20240105135906.383394-1-qi.z.zhang@intel.com>\n <20240105211237.394105-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In currently 5 layer tree implementation, the port and tc layer\nis not configurable, so its not necessary to expose them to application.\n\nThe patch hides the top 2 layers and represented the root of the tree at\nVSI layer. From application's point of view, its a 3 layer scheduler tree:\n\nPort -> Queue Group -> Queue.\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Wenjun Wu <wenjun1.wu@intel.com>\n---\n drivers/net/ice/ice_ethdev.h | 7 ----\n drivers/net/ice/ice_tm.c | 79 ++++--------------------------------\n 2 files changed, 7 insertions(+), 79 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h\nindex fa4981ed14..ae22c29ffc 100644\n--- a/drivers/net/ice/ice_ethdev.h\n+++ b/drivers/net/ice/ice_ethdev.h\n@@ -470,7 +470,6 @@ struct ice_tm_shaper_profile {\n struct ice_tm_node {\n \tTAILQ_ENTRY(ice_tm_node) node;\n \tuint32_t id;\n-\tuint32_t tc;\n \tuint32_t priority;\n \tuint32_t weight;\n \tuint32_t reference_count;\n@@ -484,8 +483,6 @@ struct ice_tm_node {\n /* node type of Traffic Manager */\n enum ice_tm_node_type {\n \tICE_TM_NODE_TYPE_PORT,\n-\tICE_TM_NODE_TYPE_TC,\n-\tICE_TM_NODE_TYPE_VSI,\n \tICE_TM_NODE_TYPE_QGROUP,\n \tICE_TM_NODE_TYPE_QUEUE,\n \tICE_TM_NODE_TYPE_MAX,\n@@ -495,12 +492,8 @@ enum ice_tm_node_type {\n struct ice_tm_conf {\n \tstruct ice_shaper_profile_list shaper_profile_list;\n \tstruct ice_tm_node *root; /* root node - port */\n-\tstruct ice_tm_node_list tc_list; /* node list for all the TCs */\n-\tstruct ice_tm_node_list vsi_list; /* node list for all the VSIs */\n \tstruct ice_tm_node_list qgroup_list; /* node list for all the queue groups */\n \tstruct ice_tm_node_list queue_list; /* node list for all the queues */\n-\tuint32_t nb_tc_node;\n-\tuint32_t nb_vsi_node;\n \tuint32_t nb_qgroup_node;\n \tuint32_t nb_queue_node;\n \tbool committed;\ndiff --git a/drivers/net/ice/ice_tm.c b/drivers/net/ice/ice_tm.c\nindex b570798f07..7ae68c683b 100644\n--- a/drivers/net/ice/ice_tm.c\n+++ b/drivers/net/ice/ice_tm.c\n@@ -43,12 +43,8 @@ ice_tm_conf_init(struct rte_eth_dev *dev)\n \t/* initialize node configuration */\n \tTAILQ_INIT(&pf->tm_conf.shaper_profile_list);\n \tpf->tm_conf.root = NULL;\n-\tTAILQ_INIT(&pf->tm_conf.tc_list);\n-\tTAILQ_INIT(&pf->tm_conf.vsi_list);\n \tTAILQ_INIT(&pf->tm_conf.qgroup_list);\n \tTAILQ_INIT(&pf->tm_conf.queue_list);\n-\tpf->tm_conf.nb_tc_node = 0;\n-\tpf->tm_conf.nb_vsi_node = 0;\n \tpf->tm_conf.nb_qgroup_node = 0;\n \tpf->tm_conf.nb_queue_node = 0;\n \tpf->tm_conf.committed = false;\n@@ -72,16 +68,6 @@ ice_tm_conf_uninit(struct rte_eth_dev *dev)\n \t\trte_free(tm_node);\n \t}\n \tpf->tm_conf.nb_qgroup_node = 0;\n-\twhile ((tm_node = TAILQ_FIRST(&pf->tm_conf.vsi_list))) {\n-\t\tTAILQ_REMOVE(&pf->tm_conf.vsi_list, tm_node, node);\n-\t\trte_free(tm_node);\n-\t}\n-\tpf->tm_conf.nb_vsi_node = 0;\n-\twhile ((tm_node = TAILQ_FIRST(&pf->tm_conf.tc_list))) {\n-\t\tTAILQ_REMOVE(&pf->tm_conf.tc_list, tm_node, node);\n-\t\trte_free(tm_node);\n-\t}\n-\tpf->tm_conf.nb_tc_node = 0;\n \tif (pf->tm_conf.root) {\n \t\trte_free(pf->tm_conf.root);\n \t\tpf->tm_conf.root = NULL;\n@@ -93,8 +79,6 @@ ice_tm_node_search(struct rte_eth_dev *dev,\n \t\t uint32_t node_id, enum ice_tm_node_type *node_type)\n {\n \tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n-\tstruct ice_tm_node_list *tc_list = &pf->tm_conf.tc_list;\n-\tstruct ice_tm_node_list *vsi_list = &pf->tm_conf.vsi_list;\n \tstruct ice_tm_node_list *qgroup_list = &pf->tm_conf.qgroup_list;\n \tstruct ice_tm_node_list *queue_list = &pf->tm_conf.queue_list;\n \tstruct ice_tm_node *tm_node;\n@@ -104,20 +88,6 @@ ice_tm_node_search(struct rte_eth_dev *dev,\n \t\treturn pf->tm_conf.root;\n \t}\n \n-\tTAILQ_FOREACH(tm_node, tc_list, node) {\n-\t\tif (tm_node->id == node_id) {\n-\t\t\t*node_type = ICE_TM_NODE_TYPE_TC;\n-\t\t\treturn tm_node;\n-\t\t}\n-\t}\n-\n-\tTAILQ_FOREACH(tm_node, vsi_list, node) {\n-\t\tif (tm_node->id == node_id) {\n-\t\t\t*node_type = ICE_TM_NODE_TYPE_VSI;\n-\t\t\treturn tm_node;\n-\t\t}\n-\t}\n-\n \tTAILQ_FOREACH(tm_node, qgroup_list, node) {\n \t\tif (tm_node->id == node_id) {\n \t\t\t*node_type = ICE_TM_NODE_TYPE_QGROUP;\n@@ -371,6 +341,8 @@ ice_shaper_profile_del(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+#define MAX_QUEUE_PER_GROUP\t8\n+\n static int\n ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t uint32_t parent_node_id, uint32_t priority,\n@@ -384,8 +356,6 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \tstruct ice_tm_shaper_profile *shaper_profile = NULL;\n \tstruct ice_tm_node *tm_node;\n \tstruct ice_tm_node *parent_node;\n-\tuint16_t tc_nb = 1;\n-\tuint16_t vsi_nb = 1;\n \tint ret;\n \n \tif (!params || !error)\n@@ -440,6 +410,7 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t\ttm_node->id = node_id;\n \t\ttm_node->parent = NULL;\n \t\ttm_node->reference_count = 0;\n+\t\ttm_node->shaper_profile = shaper_profile;\n \t\ttm_node->children = (struct ice_tm_node **)\n \t\t\trte_calloc(NULL, 256, (sizeof(struct ice_tm_node *)), 0);\n \t\trte_memcpy(&tm_node->params, params,\n@@ -448,7 +419,6 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t\treturn 0;\n \t}\n \n-\t/* TC or queue node */\n \t/* check the parent node */\n \tparent_node = ice_tm_node_search(dev, parent_node_id,\n \t\t\t\t\t &parent_node_type);\n@@ -458,8 +428,6 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t\treturn -EINVAL;\n \t}\n \tif (parent_node_type != ICE_TM_NODE_TYPE_PORT &&\n-\t parent_node_type != ICE_TM_NODE_TYPE_TC &&\n-\t parent_node_type != ICE_TM_NODE_TYPE_VSI &&\n \t parent_node_type != ICE_TM_NODE_TYPE_QGROUP) {\n \t\terror->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID;\n \t\terror->message = \"parent is not valid\";\n@@ -475,20 +443,6 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \n \t/* check the node number */\n \tif (parent_node_type == ICE_TM_NODE_TYPE_PORT) {\n-\t\t/* check the TC number */\n-\t\tif (pf->tm_conf.nb_tc_node >= tc_nb) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\t\terror->message = \"too many TCs\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t} else if (parent_node_type == ICE_TM_NODE_TYPE_TC) {\n-\t\t/* check the VSI number */\n-\t\tif (pf->tm_conf.nb_vsi_node >= vsi_nb) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\t\terror->message = \"too many VSIs\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t} else if (parent_node_type == ICE_TM_NODE_TYPE_VSI) {\n \t\t/* check the queue group number */\n \t\tif (parent_node->reference_count >= pf->dev_data->nb_tx_queues) {\n \t\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n@@ -497,7 +451,7 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t\t}\n \t} else {\n \t\t/* check the queue number */\n-\t\tif (parent_node->reference_count >= pf->dev_data->nb_tx_queues) {\n+\t\tif (parent_node->reference_count >= MAX_QUEUE_PER_GROUP) {\n \t\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n \t\t\terror->message = \"too many queues\";\n \t\t\treturn -EINVAL;\n@@ -509,7 +463,6 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \t\t}\n \t}\n \n-\t/* add the TC or VSI or queue group or queue node */\n \ttm_node = rte_zmalloc(\"ice_tm_node\",\n \t\t\t sizeof(struct ice_tm_node),\n \t\t\t 0);\n@@ -538,24 +491,12 @@ ice_tm_node_add(struct rte_eth_dev *dev, uint32_t node_id,\n \trte_memcpy(&tm_node->params, params,\n \t\t\t sizeof(struct rte_tm_node_params));\n \tif (parent_node_type == ICE_TM_NODE_TYPE_PORT) {\n-\t\tTAILQ_INSERT_TAIL(&pf->tm_conf.tc_list,\n-\t\t\t\t tm_node, node);\n-\t\ttm_node->tc = pf->tm_conf.nb_tc_node;\n-\t\tpf->tm_conf.nb_tc_node++;\n-\t} else if (parent_node_type == ICE_TM_NODE_TYPE_TC) {\n-\t\tTAILQ_INSERT_TAIL(&pf->tm_conf.vsi_list,\n-\t\t\t\t tm_node, node);\n-\t\ttm_node->tc = parent_node->tc;\n-\t\tpf->tm_conf.nb_vsi_node++;\n-\t} else if (parent_node_type == ICE_TM_NODE_TYPE_VSI) {\n \t\tTAILQ_INSERT_TAIL(&pf->tm_conf.qgroup_list,\n \t\t\t\t tm_node, node);\n-\t\ttm_node->tc = parent_node->parent->tc;\n \t\tpf->tm_conf.nb_qgroup_node++;\n \t} else {\n \t\tTAILQ_INSERT_TAIL(&pf->tm_conf.queue_list,\n \t\t\t\t tm_node, node);\n-\t\ttm_node->tc = parent_node->parent->parent->tc;\n \t\tpf->tm_conf.nb_queue_node++;\n \t}\n \ttm_node->parent->reference_count++;\n@@ -603,15 +544,9 @@ ice_tm_node_delete(struct rte_eth_dev *dev, uint32_t node_id,\n \t\treturn 0;\n \t}\n \n-\t/* TC or VSI or queue group or queue node */\n+\t/* queue group or queue node */\n \ttm_node->parent->reference_count--;\n-\tif (node_type == ICE_TM_NODE_TYPE_TC) {\n-\t\tTAILQ_REMOVE(&pf->tm_conf.tc_list, tm_node, node);\n-\t\tpf->tm_conf.nb_tc_node--;\n-\t} else if (node_type == ICE_TM_NODE_TYPE_VSI) {\n-\t\tTAILQ_REMOVE(&pf->tm_conf.vsi_list, tm_node, node);\n-\t\tpf->tm_conf.nb_vsi_node--;\n-\t} else if (node_type == ICE_TM_NODE_TYPE_QGROUP) {\n+\tif (node_type == ICE_TM_NODE_TYPE_QGROUP) {\n \t\tTAILQ_REMOVE(&pf->tm_conf.qgroup_list, tm_node, node);\n \t\tpf->tm_conf.nb_qgroup_node--;\n \t} else {\n@@ -872,7 +807,7 @@ int ice_do_hierarchy_commit(struct rte_eth_dev *dev,\n \n \t/* config vsi node */\n \tvsi_node = ice_get_vsi_node(hw);\n-\ttm_node = TAILQ_FIRST(&pf->tm_conf.vsi_list);\n+\ttm_node = pf->tm_conf.root;\n \n \tret_val = ice_set_node_rate(hw, tm_node, vsi_node);\n \tif (ret_val) {\n", "prefixes": [ "v3", "1/3" ] }