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GET /api/patches/135665/?format=api
{ "id": 135665, "url": "http://patches.dpdk.org/api/patches/135665/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240102045417.115-19-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240102045417.115-19-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240102045417.115-19-anoobj@marvell.com", "date": "2024-01-02T04:54:11", "name": "[v2,18/24] crypto/cnxk: add PMD APIs for raw submission to CPT", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3c4e7e92d7a3ad3d5fbd3c4fc27b154ff8108ec4", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240102045417.115-19-anoobj@marvell.com/mbox/", "series": [ { "id": 30694, "url": "http://patches.dpdk.org/api/series/30694/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30694", "date": "2024-01-02T04:53:53", "name": "Fixes and improvements in crypto cnxk", "version": 2, "mbox": "http://patches.dpdk.org/series/30694/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135665/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/135665/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1C108437F8;\n\tTue, 2 Jan 2024 05:56:54 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 060B540A81;\n\tTue, 2 Jan 2024 05:56:54 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 2BBAD40A76\n for <dev@dpdk.org>; Tue, 2 Jan 2024 05:56:52 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 401NTTKF002057 for <dev@dpdk.org>; Mon, 1 Jan 2024 20:56:51 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vb5c3469a-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 01 Jan 2024 20:56:51 -0800 (PST)", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Mon, 1 Jan 2024 20:56:34 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Mon, 1 Jan 2024 20:56:34 -0800", "from BG-LT92004.corp.innovium.com (unknown [10.28.163.189])\n by maili.marvell.com (Postfix) with ESMTP id AA7DB3F7081;\n Mon, 1 Jan 2024 20:56:28 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=5++nwSb00/0RNfKLkiDdzuYJ9bDD5h148SozZmooKwY=; b=Ndc\n 8+4+4FMXmRkJjH6pY+8+Ck8lell4yHqIPT+L4dFbSvrjPMF/JIAjVAMTNKZxTjyZ\n HNClR4T5q+sRVm8Y9aIvhIzFfFrsRyIT6M5iMT97w6TBKSl+TYxDmE9G6YUbaZDq\n GGKKHEsNrSbGDIiX/Ld8OTTaz4SiO4AvD52oVAQdLQKpW9ZSj6YhitJ82MZ916Ku\n lNDZJXl60+f29hJBjSNLdocCoc5oJb5WY/QROLBYIWaGewC8BTSw1iMjARBGMRNo\n U1utzs9uTQh1atb3JoN9tOim/tqc2xd+MkAKsMjbdP/Oow9CkILE0K7a/HMpqczZ\n UB32O5x8ZTfHpEB5qHg==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Jerin Jacob <jerinj@marvell.com>, Vidya Sagar Velumuri\n <vvelumuri@marvell.com>,\n Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v2 18/24] crypto/cnxk: add PMD APIs for raw submission to CPT", "Date": "Tue, 2 Jan 2024 10:24:11 +0530", "Message-ID": "<20240102045417.115-19-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240102045417.115-1-anoobj@marvell.com>", "References": "<20231221123545.510-1-anoobj@marvell.com>\n <20240102045417.115-1-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "GJvAgWhZYScdwPqLY1C11X9HxPmoBvEp", "X-Proofpoint-ORIG-GUID": "GJvAgWhZYScdwPqLY1C11X9HxPmoBvEp", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add PMD APIs to allow applications to directly submit CPT instructions\nto hardware.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\n---\n doc/api/doxy-api-index.md | 1 +\n doc/api/doxy-api.conf.in | 1 +\n doc/guides/rel_notes/release_24_03.rst | 1 +\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 75 ++++++++---------\n drivers/crypto/cnxk/cn10k_cryptodev_ops.h | 3 +\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 56 -------------\n drivers/crypto/cnxk/cn9k_cryptodev_ops.h | 62 ++++++++++++++\n drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 99 +++++++++++++++++++++++\n drivers/crypto/cnxk/meson.build | 2 +-\n drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h | 46 +++++++++++\n 10 files changed, 252 insertions(+), 94 deletions(-)\n create mode 100644 drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h", "diff": "diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md\nindex a6a768bd7c..69f1a54511 100644\n--- a/doc/api/doxy-api-index.md\n+++ b/doc/api/doxy-api-index.md\n@@ -49,6 +49,7 @@ The public API headers are grouped by topics:\n [iavf](@ref rte_pmd_iavf.h),\n [bnxt](@ref rte_pmd_bnxt.h),\n [cnxk](@ref rte_pmd_cnxk.h),\n+ [cnxk_crypto](@ref rte_pmd_cnxk_crypto.h),\n [cnxk_eventdev](@ref rte_pmd_cnxk_eventdev.h),\n [cnxk_mempool](@ref rte_pmd_cnxk_mempool.h),\n [dpaa](@ref rte_pmd_dpaa.h),\ndiff --git a/doc/api/doxy-api.conf.in b/doc/api/doxy-api.conf.in\nindex e94c9e4e46..6d11de580e 100644\n--- a/doc/api/doxy-api.conf.in\n+++ b/doc/api/doxy-api.conf.in\n@@ -6,6 +6,7 @@ PROJECT_NUMBER = @VERSION@\n USE_MDFILE_AS_MAINPAGE = @TOPDIR@/doc/api/doxy-api-index.md\n INPUT = @TOPDIR@/doc/api/doxy-api-index.md \\\n @TOPDIR@/drivers/bus/vdev \\\n+ @TOPDIR@/drivers/crypto/cnxk \\\n @TOPDIR@/drivers/crypto/scheduler \\\n @TOPDIR@/drivers/dma/dpaa2 \\\n @TOPDIR@/drivers/event/dlb2 \\\ndiff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 0ebbae9f4e..f5773bab5a 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -60,6 +60,7 @@ New Features\n * Added support for Rx inject in crypto_cn10k.\n * Added support for TLS record processing in crypto_cn10k. Supports TLS 1.2\n and DTLS 1.2.\n+ * Added PMD API to allow raw submission of instructions to CPT.\n \n Removed Items\n -------------\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex 843a111b0e..9f4be20ff5 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -34,13 +34,12 @@\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_se.h\"\n \n-#define PKTS_PER_LOOP\t32\n-#define PKTS_PER_STEORL 16\n+#include \"rte_pmd_cnxk_crypto.h\"\n \n /* Holds information required to send crypto operations in one burst */\n struct ops_burst {\n-\tstruct rte_crypto_op *op[PKTS_PER_LOOP];\n-\tuint64_t w2[PKTS_PER_LOOP];\n+\tstruct rte_crypto_op *op[CN10K_PKTS_PER_LOOP];\n+\tuint64_t w2[CN10K_PKTS_PER_LOOP];\n \tstruct cn10k_sso_hws *ws;\n \tstruct cnxk_cpt_qp *qp;\n \tuint16_t nb_ops;\n@@ -252,7 +251,7 @@ cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops,\n \t\tgoto pend_q_commit;\n \t}\n \n-\tfor (i = 0; i < RTE_MIN(PKTS_PER_LOOP, nb_ops); i++) {\n+\tfor (i = 0; i < RTE_MIN(CN10K_PKTS_PER_LOOP, nb_ops); i++) {\n \t\tinfl_req = &pend_q->req_queue[head];\n \t\tinfl_req->op_flags = 0;\n \n@@ -267,23 +266,21 @@ cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops,\n \t\tpending_queue_advance(&head, pq_mask);\n \t}\n \n-\tif (i > PKTS_PER_STEORL) {\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (PKTS_PER_STEORL - 1) << 12 |\n+\tif (i > CN10K_PKTS_PER_STEORL) {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (CN10K_PKTS_PER_STEORL - 1) << 12 |\n \t\t\t (uint64_t)lmt_id;\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG |\n-\t\t\t (i - PKTS_PER_STEORL - 1) << 12 |\n-\t\t\t (uint64_t)(lmt_id + PKTS_PER_STEORL);\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)(lmt_id + CN10K_PKTS_PER_STEORL);\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n \t} else {\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 |\n-\t\t\t (uint64_t)lmt_id;\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 | (uint64_t)lmt_id;\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n \t}\n \n \trte_io_wmb();\n \n-\tif (nb_ops - i > 0 && i == PKTS_PER_LOOP) {\n+\tif (nb_ops - i > 0 && i == CN10K_PKTS_PER_LOOP) {\n \t\tnb_ops -= i;\n \t\tops += i;\n \t\tcount += i;\n@@ -487,7 +484,7 @@ cn10k_cpt_vec_submit(struct vec_request vec_tbl[], uint16_t vec_tbl_len, struct\n \tinst = (struct cpt_inst_s *)lmt_base;\n \n again:\n-\tburst_size = RTE_MIN(PKTS_PER_STEORL, vec_tbl_len);\n+\tburst_size = RTE_MIN(CN10K_PKTS_PER_STEORL, vec_tbl_len);\n \tfor (i = 0; i < burst_size; i++)\n \t\tcn10k_cpt_vec_inst_fill(&vec_tbl[i], &inst[i * 2], qp, vec_tbl[0].w7);\n \n@@ -516,7 +513,7 @@ static inline int\n ca_lmtst_vec_submit(struct ops_burst *burst, struct vec_request vec_tbl[], uint16_t *vec_tbl_len,\n \t\t const bool is_sg_ver2)\n {\n-\tstruct cpt_inflight_req *infl_reqs[PKTS_PER_LOOP];\n+\tstruct cpt_inflight_req *infl_reqs[CN10K_PKTS_PER_LOOP];\n \tuint64_t lmt_base, lmt_arg, io_addr;\n \tuint16_t lmt_id, len = *vec_tbl_len;\n \tstruct cpt_inst_s *inst, *inst_base;\n@@ -618,11 +615,12 @@ next_op:;\n \tif (CNXK_TT_FROM_TAG(burst->ws->gw_rdata) == SSO_TT_ORDERED)\n \t\troc_sso_hws_head_wait(burst->ws->base);\n \n-\tif (i > PKTS_PER_STEORL) {\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (PKTS_PER_STEORL - 1) << 12 | (uint64_t)lmt_id;\n+\tif (i > CN10K_PKTS_PER_STEORL) {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)lmt_id;\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - PKTS_PER_STEORL - 1) << 12 |\n-\t\t\t (uint64_t)(lmt_id + PKTS_PER_STEORL);\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)(lmt_id + CN10K_PKTS_PER_STEORL);\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n \t} else {\n \t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 | (uint64_t)lmt_id;\n@@ -647,7 +645,7 @@ next_op:;\n static inline uint16_t\n ca_lmtst_burst_submit(struct ops_burst *burst, const bool is_sg_ver2)\n {\n-\tstruct cpt_inflight_req *infl_reqs[PKTS_PER_LOOP];\n+\tstruct cpt_inflight_req *infl_reqs[CN10K_PKTS_PER_LOOP];\n \tuint64_t lmt_base, lmt_arg, io_addr;\n \tstruct cpt_inst_s *inst, *inst_base;\n \tstruct cpt_inflight_req *infl_req;\n@@ -718,11 +716,12 @@ ca_lmtst_burst_submit(struct ops_burst *burst, const bool is_sg_ver2)\n \tif (CNXK_TT_FROM_TAG(burst->ws->gw_rdata) == SSO_TT_ORDERED)\n \t\troc_sso_hws_head_wait(burst->ws->base);\n \n-\tif (i > PKTS_PER_STEORL) {\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (PKTS_PER_STEORL - 1) << 12 | (uint64_t)lmt_id;\n+\tif (i > CN10K_PKTS_PER_STEORL) {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)lmt_id;\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - PKTS_PER_STEORL - 1) << 12 |\n-\t\t\t (uint64_t)(lmt_id + PKTS_PER_STEORL);\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)(lmt_id + CN10K_PKTS_PER_STEORL);\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n \t} else {\n \t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 | (uint64_t)lmt_id;\n@@ -791,7 +790,7 @@ cn10k_cpt_crypto_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_ev\n \t\tburst.op[burst.nb_ops] = op;\n \n \t\t/* Max nb_ops per burst check */\n-\t\tif (++burst.nb_ops == PKTS_PER_LOOP) {\n+\t\tif (++burst.nb_ops == CN10K_PKTS_PER_LOOP) {\n \t\t\tif (is_vector)\n \t\t\t\tsubmitted = ca_lmtst_vec_submit(&burst, vec_tbl, &vec_tbl_len,\n \t\t\t\t\t\t\t\tis_sg_ver2);\n@@ -1146,7 +1145,7 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts,\n \n again:\n \tinst = (struct cpt_inst_s *)lmt_base;\n-\tfor (i = 0; i < RTE_MIN(PKTS_PER_LOOP, nb_pkts); i++) {\n+\tfor (i = 0; i < RTE_MIN(CN10K_PKTS_PER_LOOP, nb_pkts); i++) {\n \n \t\tm = pkts[i];\n \t\tsec_sess = (struct cn10k_sec_session *)sess[i];\n@@ -1193,11 +1192,12 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts,\n \t\tinst += 2;\n \t}\n \n-\tif (i > PKTS_PER_STEORL) {\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (PKTS_PER_STEORL - 1) << 12 | (uint64_t)lmt_id;\n+\tif (i > CN10K_PKTS_PER_STEORL) {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)lmt_id;\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - PKTS_PER_STEORL - 1) << 12 |\n-\t\t\t (uint64_t)(lmt_id + PKTS_PER_STEORL);\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)(lmt_id + CN10K_PKTS_PER_STEORL);\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n \t} else {\n \t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 | (uint64_t)lmt_id;\n@@ -1206,7 +1206,7 @@ cn10k_cryptodev_sec_inb_rx_inject(void *dev, struct rte_mbuf **pkts,\n \n \trte_io_wmb();\n \n-\tif (nb_pkts - i > 0 && i == PKTS_PER_LOOP) {\n+\tif (nb_pkts - i > 0 && i == CN10K_PKTS_PER_LOOP) {\n \t\tnb_pkts -= i;\n \t\tpkts += i;\n \t\tcount += i;\n@@ -1333,7 +1333,7 @@ cn10k_cpt_raw_enqueue_burst(void *qpair, uint8_t *drv_ctx, struct rte_crypto_sym\n \t\tgoto pend_q_commit;\n \t}\n \n-\tfor (i = 0; i < RTE_MIN(PKTS_PER_LOOP, nb_ops); i++) {\n+\tfor (i = 0; i < RTE_MIN(CN10K_PKTS_PER_LOOP, nb_ops); i++) {\n \t\tstruct cnxk_iov iov;\n \n \t\tindex = count + i;\n@@ -1355,11 +1355,12 @@ cn10k_cpt_raw_enqueue_burst(void *qpair, uint8_t *drv_ctx, struct rte_crypto_sym\n \t\tpending_queue_advance(&head, pq_mask);\n \t}\n \n-\tif (i > PKTS_PER_STEORL) {\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (PKTS_PER_STEORL - 1) << 12 | (uint64_t)lmt_id;\n+\tif (i > CN10K_PKTS_PER_STEORL) {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)lmt_id;\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n-\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - PKTS_PER_STEORL - 1) << 12 |\n-\t\t\t (uint64_t)(lmt_id + PKTS_PER_STEORL);\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)(lmt_id + CN10K_PKTS_PER_STEORL);\n \t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n \t} else {\n \t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 | (uint64_t)lmt_id;\n@@ -1368,7 +1369,7 @@ cn10k_cpt_raw_enqueue_burst(void *qpair, uint8_t *drv_ctx, struct rte_crypto_sym\n \n \trte_io_wmb();\n \n-\tif (nb_ops - i > 0 && i == PKTS_PER_LOOP) {\n+\tif (nb_ops - i > 0 && i == CN10K_PKTS_PER_LOOP) {\n \t\tnb_ops -= i;\n \t\tcount += i;\n \t\tgoto again;\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\nindex 34becede3c..406c4abc7f 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\n@@ -12,6 +12,9 @@\n \n #include \"cnxk_cryptodev.h\"\n \n+#define CN10K_PKTS_PER_LOOP 32\n+#define CN10K_PKTS_PER_STEORL 16\n+\n extern struct rte_cryptodev_ops cn10k_cpt_ops;\n \n void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev, struct cnxk_cpt_vf *vf);\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex 442cd8e5a9..ac9393eacf 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -122,62 +122,6 @@ cn9k_cpt_inst_prep(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \treturn ret;\n }\n \n-static inline void\n-cn9k_cpt_inst_submit(struct cpt_inst_s *inst, uint64_t lmtline,\n-\t\t uint64_t io_addr)\n-{\n-\tuint64_t lmt_status;\n-\n-\tdo {\n-\t\t/* Copy CPT command to LMTLINE */\n-\t\troc_lmt_mov64((void *)lmtline, inst);\n-\n-\t\t/*\n-\t\t * Make sure compiler does not reorder memcpy and ldeor.\n-\t\t * LMTST transactions are always flushed from the write\n-\t\t * buffer immediately, a DMB is not required to push out\n-\t\t * LMTSTs.\n-\t\t */\n-\t\trte_io_wmb();\n-\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n-\t} while (lmt_status == 0);\n-}\n-\n-static __plt_always_inline void\n-cn9k_cpt_inst_submit_dual(struct cpt_inst_s *inst, uint64_t lmtline,\n-\t\t\t uint64_t io_addr)\n-{\n-\tuint64_t lmt_status;\n-\n-\tdo {\n-\t\t/* Copy 2 CPT inst_s to LMTLINE */\n-#if defined(RTE_ARCH_ARM64)\n-\t\tuint64_t *s = (uint64_t *)inst;\n-\t\tuint64_t *d = (uint64_t *)lmtline;\n-\n-\t\tvst1q_u64(&d[0], vld1q_u64(&s[0]));\n-\t\tvst1q_u64(&d[2], vld1q_u64(&s[2]));\n-\t\tvst1q_u64(&d[4], vld1q_u64(&s[4]));\n-\t\tvst1q_u64(&d[6], vld1q_u64(&s[6]));\n-\t\tvst1q_u64(&d[8], vld1q_u64(&s[8]));\n-\t\tvst1q_u64(&d[10], vld1q_u64(&s[10]));\n-\t\tvst1q_u64(&d[12], vld1q_u64(&s[12]));\n-\t\tvst1q_u64(&d[14], vld1q_u64(&s[14]));\n-#else\n-\t\troc_lmt_mov_seg((void *)lmtline, inst, 8);\n-#endif\n-\n-\t\t/*\n-\t\t * Make sure compiler does not reorder memcpy and ldeor.\n-\t\t * LMTST transactions are always flushed from the write\n-\t\t * buffer immediately, a DMB is not required to push out\n-\t\t * LMTSTs.\n-\t\t */\n-\t\trte_io_wmb();\n-\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n-\t} while (lmt_status == 0);\n-}\n-\n static uint16_t\n cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n {\ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h\nindex c6ec96153e..3d667094f3 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h\n@@ -8,8 +8,70 @@\n #include <rte_compat.h>\n #include <cryptodev_pmd.h>\n \n+#include <hw/cpt.h>\n+\n+#if defined(__aarch64__)\n+#include \"roc_io.h\"\n+#else\n+#include \"roc_io_generic.h\"\n+#endif\n+\n extern struct rte_cryptodev_ops cn9k_cpt_ops;\n \n+static inline void\n+cn9k_cpt_inst_submit(struct cpt_inst_s *inst, uint64_t lmtline, uint64_t io_addr)\n+{\n+\tuint64_t lmt_status;\n+\n+\tdo {\n+\t\t/* Copy CPT command to LMTLINE */\n+\t\troc_lmt_mov64((void *)lmtline, inst);\n+\n+\t\t/*\n+\t\t * Make sure compiler does not reorder memcpy and ldeor.\n+\t\t * LMTST transactions are always flushed from the write\n+\t\t * buffer immediately, a DMB is not required to push out\n+\t\t * LMTSTs.\n+\t\t */\n+\t\trte_io_wmb();\n+\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t} while (lmt_status == 0);\n+}\n+\n+static __plt_always_inline void\n+cn9k_cpt_inst_submit_dual(struct cpt_inst_s *inst, uint64_t lmtline, uint64_t io_addr)\n+{\n+\tuint64_t lmt_status;\n+\n+\tdo {\n+\t\t/* Copy 2 CPT inst_s to LMTLINE */\n+#if defined(RTE_ARCH_ARM64)\n+\t\tvolatile const __uint128_t *src128 = (const __uint128_t *)inst;\n+\t\tvolatile __uint128_t *dst128 = (__uint128_t *)lmtline;\n+\n+\t\tdst128[0] = src128[0];\n+\t\tdst128[1] = src128[1];\n+\t\tdst128[2] = src128[2];\n+\t\tdst128[3] = src128[3];\n+\t\tdst128[4] = src128[4];\n+\t\tdst128[5] = src128[5];\n+\t\tdst128[6] = src128[6];\n+\t\tdst128[7] = src128[7];\n+#else\n+\t\troc_lmt_mov_seg((void *)lmtline, inst, 8);\n+#endif\n+\n+\t\t/*\n+\t\t * Make sure compiler does not reorder memcpy and ldeor.\n+\t\t * LMTST transactions are always flushed from the write\n+\t\t * buffer immediately, a DMB is not required to push out\n+\t\t * LMTSTs.\n+\t\t */\n+\t\trte_io_wmb();\n+\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t} while (lmt_status == 0);\n+}\n+\n void cn9k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);\n \n __rte_internal\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\nindex fd44155955..7a37e3e89c 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n@@ -12,6 +12,11 @@\n #include \"roc_errata.h\"\n #include \"roc_idev.h\"\n #include \"roc_ie_on.h\"\n+#if defined(__aarch64__)\n+#include \"roc_io.h\"\n+#else\n+#include \"roc_io_generic.h\"\n+#endif\n \n #include \"cnxk_ae.h\"\n #include \"cnxk_cryptodev.h\"\n@@ -19,6 +24,11 @@\n #include \"cnxk_cryptodev_ops.h\"\n #include \"cnxk_se.h\"\n \n+#include \"cn10k_cryptodev_ops.h\"\n+#include \"cn9k_cryptodev_ops.h\"\n+\n+#include \"rte_pmd_cnxk_crypto.h\"\n+\n #define CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS\t 5\n #define CNXK_CPT_MAX_ASYM_OP_MOD_LEN\t 1024\n #define CNXK_CPT_META_BUF_MAX_CACHE_SIZE 128\n@@ -918,3 +928,92 @@ cnxk_cpt_queue_pair_event_error_query(struct rte_cryptodev *dev, uint16_t qp_id)\n \t}\n \treturn 0;\n }\n+\n+void *\n+rte_pmd_cnxk_crypto_qptr_get(uint8_t dev_id, uint16_t qp_id)\n+{\n+\tconst struct rte_crypto_fp_ops *fp_ops;\n+\tvoid *qptr;\n+\n+\tfp_ops = &rte_crypto_fp_ops[dev_id];\n+\tqptr = fp_ops->qp.data[qp_id];\n+\n+\treturn qptr;\n+}\n+\n+static inline void\n+cnxk_crypto_cn10k_submit(void *qptr, void *inst, uint16_t nb_inst)\n+{\n+\tuint64_t lmt_base, lmt_arg, io_addr;\n+\tstruct cnxk_cpt_qp *qp = qptr;\n+\tuint16_t i, j, lmt_id;\n+\tvoid *lmt_dst;\n+\n+\tlmt_base = qp->lmtline.lmt_base;\n+\tio_addr = qp->lmtline.io_addr;\n+\n+\tROC_LMT_BASE_ID_GET(lmt_base, lmt_id);\n+\n+again:\n+\ti = RTE_MIN(nb_inst, CN10K_PKTS_PER_LOOP);\n+\tlmt_dst = PLT_PTR_CAST(lmt_base);\n+\n+\tfor (j = 0; j < i; j++) {\n+\t\trte_memcpy(lmt_dst, inst, sizeof(struct cpt_inst_s));\n+\t\tinst = RTE_PTR_ADD(inst, sizeof(struct cpt_inst_s));\n+\t\tlmt_dst = RTE_PTR_ADD(lmt_dst, 2 * sizeof(struct cpt_inst_s));\n+\t}\n+\n+\trte_io_wmb();\n+\n+\tif (i > CN10K_PKTS_PER_STEORL) {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)lmt_id;\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - CN10K_PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)(lmt_id + CN10K_PKTS_PER_STEORL);\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t} else {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 | (uint64_t)lmt_id;\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t}\n+\n+\trte_io_wmb();\n+\n+\tif (nb_inst - i > 0) {\n+\t\tnb_inst -= i;\n+\t\tgoto again;\n+\t}\n+}\n+\n+static inline void\n+cnxk_crypto_cn9k_submit(void *qptr, void *inst, uint16_t nb_inst)\n+{\n+\tstruct cnxk_cpt_qp *qp = qptr;\n+\n+\tconst uint64_t lmt_base = qp->lf.lmt_base;\n+\tconst uint64_t io_addr = qp->lf.io_addr;\n+\n+\tif (unlikely(nb_inst & 1)) {\n+\t\tcn9k_cpt_inst_submit(inst, lmt_base, io_addr);\n+\t\tinst = RTE_PTR_ADD(inst, sizeof(struct cpt_inst_s));\n+\t\tnb_inst -= 1;\n+\t}\n+\n+\twhile (nb_inst > 0) {\n+\t\tcn9k_cpt_inst_submit_dual(inst, lmt_base, io_addr);\n+\t\tinst = RTE_PTR_ADD(inst, 2 * sizeof(struct cpt_inst_s));\n+\t\tnb_inst -= 2;\n+\t}\n+}\n+\n+void\n+rte_pmd_cnxk_crypto_submit(void *qptr, void *inst, uint16_t nb_inst)\n+{\n+\tif (roc_model_is_cn10k())\n+\t\treturn cnxk_crypto_cn10k_submit(qptr, inst, nb_inst);\n+\telse if (roc_model_is_cn9k())\n+\t\treturn cnxk_crypto_cn9k_submit(qptr, inst, nb_inst);\n+\n+\tplt_err(\"Invalid cnxk model\");\n+}\ndiff --git a/drivers/crypto/cnxk/meson.build b/drivers/crypto/cnxk/meson.build\nindex ee0c65e32a..aa840fb7bb 100644\n--- a/drivers/crypto/cnxk/meson.build\n+++ b/drivers/crypto/cnxk/meson.build\n@@ -24,8 +24,8 @@ sources = files(\n 'cnxk_cryptodev_sec.c',\n )\n \n+headers = files('rte_pmd_cnxk_crypto.h')\n deps += ['bus_pci', 'common_cnxk', 'security', 'eventdev']\n-\n includes += include_directories('../../../lib/net', '../../event/cnxk')\n \n if get_option('buildtype').contains('debug')\ndiff --git a/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h b/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h\nnew file mode 100644\nindex 0000000000..64978a008b\n--- /dev/null\n+++ b/drivers/crypto/cnxk/rte_pmd_cnxk_crypto.h\n@@ -0,0 +1,46 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+/**\n+ * @file rte_pmd_cnxk_crypto.h\n+ * Marvell CNXK Crypto PMD specific functions.\n+ *\n+ **/\n+\n+#ifndef _PMD_CNXK_CRYPTO_H_\n+#define _PMD_CNXK_CRYPTO_H_\n+\n+#include <stdint.h>\n+\n+/**\n+ * Get queue pointer of a specific queue in a cryptodev.\n+ *\n+ * @param dev_id\n+ * Device identifier of cryptodev device.\n+ * @param qp_id\n+ * Index of the queue pair.\n+ * @return\n+ * Pointer to queue pair structure that would be the input to submit APIs.\n+ */\n+void *rte_pmd_cnxk_crypto_qptr_get(uint8_t dev_id, uint16_t qp_id);\n+\n+/**\n+ * Submit CPT instruction (cpt_inst_s) to hardware (CPT).\n+ *\n+ * The ``qp`` is a pointer obtained from ``rte_pmd_cnxk_crypto_qp_get``. Application should make\n+ * sure it doesn't overflow the internal hardware queues. It may do so by making sure the inflight\n+ * packets are not more than the number of descriptors configured.\n+ *\n+ * This API may be called only after the cryptodev and queue pair is configured and is started.\n+ *\n+ * @param qptr\n+ * Pointer obtained with ``rte_pmd_cnxk_crypto_qptr_get``.\n+ * @param inst\n+ * Pointer to an array of instructions prepared by application.\n+ * @param nb_inst\n+ * Number of instructions.\n+ */\n+void rte_pmd_cnxk_crypto_submit(void *qptr, void *inst, uint16_t nb_inst);\n+\n+#endif /* _PMD_CNXK_CRYPTO_H_ */\n", "prefixes": [ "v2", "18/24" ] }