Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/135663/?format=api
{ "id": 135663, "url": "http://patches.dpdk.org/api/patches/135663/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240102045417.115-17-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240102045417.115-17-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240102045417.115-17-anoobj@marvell.com", "date": "2024-01-02T04:54:09", "name": "[v2,16/24] crypto/cnxk: add TLS record datapath handling", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d9fbe888d6f6e65276ee4603c89d73b30ea1ed6d", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240102045417.115-17-anoobj@marvell.com/mbox/", "series": [ { "id": 30694, "url": "http://patches.dpdk.org/api/series/30694/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30694", "date": "2024-01-02T04:53:53", "name": "Fixes and improvements in crypto cnxk", "version": 2, "mbox": "http://patches.dpdk.org/series/30694/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135663/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/135663/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 28EB5437F8;\n\tTue, 2 Jan 2024 05:56:32 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 56E0340DDA;\n\tTue, 2 Jan 2024 05:56:28 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 7849C40DCE\n for <dev@dpdk.org>; Tue, 2 Jan 2024 05:56:26 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 401NTTKE002057 for <dev@dpdk.org>; Mon, 1 Jan 2024 20:56:25 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vb5c3468x-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 01 Jan 2024 20:56:25 -0800 (PST)", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Mon, 1 Jan 2024 20:56:23 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Mon, 1 Jan 2024 20:56:23 -0800", "from BG-LT92004.corp.innovium.com (unknown [10.28.163.189])\n by maili.marvell.com (Postfix) with ESMTP id 606133F7081;\n Mon, 1 Jan 2024 20:56:19 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=mB+vYAgINv3nRGB9ySmuXW+dzMZ/yVAi02xFuFJVx+w=; b=ht0\n MO/FP1wFYUawysIfTlaYrLnjWPL5f9XL51o9Q04zfTj5hv8YyY6quOoBOxsD1Xdn\n F5ZY+2/nRr8NbgrdB9z+lTBO9irGIkBKXq4yhzCEJEkcipmXh9qmpi9w+GnPkj8c\n ELOcsaaTMKmImfNySJ8IkSSme7QTLr5O0mab4cxfmO9TOb0o7QNjUZO0eHs32w7N\n JwVKmy7Qsp7ygDuF43xV5IqxJIHmqenIc5Enp+x5mLRO+T/ABUFK1TWhysnq2O7i\n S4JWoy0S2Beph3IH8jKcHejurSZKgv7jPYpnWLdfp5UPlfintL5AOrXn4FyoZLDe\n pQ/mj/agVsQ6dXt6X2A==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Vidya Sagar Velumuri <vvelumuri@marvell.com>, Jerin Jacob\n <jerinj@marvell.com>,\n Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v2 16/24] crypto/cnxk: add TLS record datapath handling", "Date": "Tue, 2 Jan 2024 10:24:09 +0530", "Message-ID": "<20240102045417.115-17-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240102045417.115-1-anoobj@marvell.com>", "References": "<20231221123545.510-1-anoobj@marvell.com>\n <20240102045417.115-1-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "IDNyWxJmnkcADsnZ8btaEm7xgjLR899r", "X-Proofpoint-ORIG-GUID": "IDNyWxJmnkcADsnZ8btaEm7xgjLR899r", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n\nAdd support for TLS record handling in datapath.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 57 +++-\n drivers/crypto/cnxk/cn10k_cryptodev_sec.c | 7 +\n drivers/crypto/cnxk/cn10k_tls_ops.h | 322 ++++++++++++++++++++++\n 3 files changed, 380 insertions(+), 6 deletions(-)\n create mode 100644 drivers/crypto/cnxk/cn10k_tls_ops.h", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex 084c8d3a24..843a111b0e 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -20,11 +20,14 @@\n #include \"roc_sso_dp.h\"\n \n #include \"cn10k_cryptodev.h\"\n-#include \"cn10k_cryptodev_ops.h\"\n #include \"cn10k_cryptodev_event_dp.h\"\n+#include \"cn10k_cryptodev_ops.h\"\n+#include \"cn10k_cryptodev_sec.h\"\n #include \"cn10k_eventdev.h\"\n #include \"cn10k_ipsec.h\"\n #include \"cn10k_ipsec_la_ops.h\"\n+#include \"cn10k_tls.h\"\n+#include \"cn10k_tls_ops.h\"\n #include \"cnxk_ae.h\"\n #include \"cnxk_cryptodev.h\"\n #include \"cnxk_cryptodev_ops.h\"\n@@ -101,6 +104,18 @@ cpt_sec_ipsec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n \treturn ret;\n }\n \n+static __rte_always_inline int __rte_hot\n+cpt_sec_tls_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n+\t\t struct cn10k_sec_session *sess, struct cpt_inst_s *inst,\n+\t\t struct cpt_inflight_req *infl_req, const bool is_sg_ver2)\n+{\n+\tif (sess->tls.is_write)\n+\t\treturn process_tls_write(&qp->lf, op, sess, &qp->meta_info, infl_req, inst,\n+\t\t\t\t\t is_sg_ver2);\n+\telse\n+\t\treturn process_tls_read(op, sess, &qp->meta_info, infl_req, inst, is_sg_ver2);\n+}\n+\n static __rte_always_inline int __rte_hot\n cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, struct cn10k_sec_session *sess,\n \t\t struct cpt_inst_s *inst, struct cpt_inflight_req *infl_req, const bool is_sg_ver2)\n@@ -108,6 +123,8 @@ cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, struct cn10k\n \n \tif (sess->proto == RTE_SECURITY_PROTOCOL_IPSEC)\n \t\treturn cpt_sec_ipsec_inst_fill(qp, op, sess, &inst[0], infl_req, is_sg_ver2);\n+\telse if (sess->proto == RTE_SECURITY_PROTOCOL_TLS_RECORD)\n+\t\treturn cpt_sec_tls_inst_fill(qp, op, sess, &inst[0], infl_req, is_sg_ver2);\n \n \treturn 0;\n }\n@@ -812,7 +829,7 @@ cn10k_cpt_sg_ver2_crypto_adapter_enqueue(void *ws, struct rte_event ev[], uint16\n }\n \n static inline void\n-cn10k_cpt_sec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res)\n+cn10k_cpt_ipsec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res)\n {\n \tstruct rte_mbuf *mbuf = cop->sym->m_src;\n \tconst uint16_t m_len = res->rlen;\n@@ -849,10 +866,38 @@ cn10k_cpt_sec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *re\n }\n \n static inline void\n-cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp,\n-\t\t\t struct rte_crypto_op *cop,\n-\t\t\t struct cpt_inflight_req *infl_req,\n-\t\t\t struct cpt_cn10k_res_s *res)\n+cn10k_cpt_tls_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res)\n+{\n+\tstruct rte_mbuf *mbuf = cop->sym->m_src;\n+\tconst uint16_t m_len = res->rlen;\n+\n+\tif (!res->uc_compcode) {\n+\t\tif (mbuf->next == NULL)\n+\t\t\tmbuf->data_len = m_len;\n+\t\tmbuf->pkt_len = m_len;\n+\t} else {\n+\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\tcop->aux_flags = res->uc_compcode;\n+\t\tplt_err(\"crypto op failed with UC compcode: 0x%x\", res->uc_compcode);\n+\t}\n+}\n+\n+static inline void\n+cn10k_cpt_sec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+\tstruct cn10k_sec_session *sess;\n+\n+\tsess = sym_op->session;\n+\tif (sess->proto == RTE_SECURITY_PROTOCOL_IPSEC)\n+\t\tcn10k_cpt_ipsec_post_process(cop, res);\n+\telse if (sess->proto == RTE_SECURITY_PROTOCOL_TLS_RECORD)\n+\t\tcn10k_cpt_tls_post_process(cop, res);\n+}\n+\n+static inline void\n+cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop,\n+\t\t\t struct cpt_inflight_req *infl_req, struct cpt_cn10k_res_s *res)\n {\n \tconst uint8_t uc_compcode = res->uc_compcode;\n \tconst uint8_t compcode = res->compcode;\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_sec.c b/drivers/crypto/cnxk/cn10k_cryptodev_sec.c\nindex 0fd0a5b03c..300a8e4f94 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_sec.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_sec.c\n@@ -32,6 +32,10 @@ cn10k_sec_session_create(void *dev, struct rte_security_session_conf *conf,\n \t\treturn cn10k_ipsec_session_create(vf, qp, &conf->ipsec, conf->crypto_xform, sess);\n \t}\n \n+\tif (conf->protocol == RTE_SECURITY_PROTOCOL_TLS_RECORD)\n+\t\treturn cn10k_tls_record_session_create(vf, qp, &conf->tls_record,\n+\t\t\t\t\t\t conf->crypto_xform, sess);\n+\n \treturn -ENOTSUP;\n }\n \n@@ -54,6 +58,9 @@ cn10k_sec_session_destroy(void *dev, struct rte_security_session *sec_sess)\n \tif (cn10k_sec_sess->proto == RTE_SECURITY_PROTOCOL_IPSEC)\n \t\treturn cn10k_sec_ipsec_session_destroy(qp, cn10k_sec_sess);\n \n+\tif (cn10k_sec_sess->proto == RTE_SECURITY_PROTOCOL_TLS_RECORD)\n+\t\treturn cn10k_sec_tls_session_destroy(qp, cn10k_sec_sess);\n+\n \treturn -EINVAL;\n }\n \ndiff --git a/drivers/crypto/cnxk/cn10k_tls_ops.h b/drivers/crypto/cnxk/cn10k_tls_ops.h\nnew file mode 100644\nindex 0000000000..a5d38bacbb\n--- /dev/null\n+++ b/drivers/crypto/cnxk/cn10k_tls_ops.h\n@@ -0,0 +1,322 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+#ifndef __CN10K_TLS_OPS_H__\n+#define __CN10K_TLS_OPS_H__\n+\n+#include <rte_crypto_sym.h>\n+#include <rte_security.h>\n+\n+#include \"roc_ie.h\"\n+\n+#include \"cn10k_cryptodev.h\"\n+#include \"cn10k_cryptodev_sec.h\"\n+#include \"cnxk_cryptodev.h\"\n+#include \"cnxk_cryptodev_ops.h\"\n+#include \"cnxk_sg.h\"\n+\n+static __rte_always_inline int\n+process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k_sec_session *sess,\n+\t\t struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req,\n+\t\t struct cpt_inst_s *inst, const bool is_sg_ver2)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+#ifdef LA_IPSEC_DEBUG\n+\tstruct roc_ie_ot_tls_write_sa *write_sa;\n+#endif\n+\tstruct rte_mbuf *m_src = sym_op->m_src;\n+\tstruct rte_mbuf *last_seg;\n+\tunion cpt_inst_w4 w4;\n+\tvoid *m_data = NULL;\n+\tuint8_t *in_buffer;\n+\n+#ifdef LA_IPSEC_DEBUG\n+\twrite_sa = &sess->tls_rec.write_sa;\n+\tif (write_sa->w2.s.iv_at_cptr == ROC_IE_OT_TLS_IV_SRC_FROM_SA) {\n+\n+\t\tuint8_t *iv = PLT_PTR_ADD(write_sa->cipher_key, 32);\n+\n+\t\tif (write_sa->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_AES_GCM) {\n+\t\t\tuint32_t *tmp;\n+\n+\t\t\t/* For GCM, the IV and salt format will be like below:\n+\t\t\t * iv[0-3]: lower bytes of IV in BE format.\n+\t\t\t * iv[4-7]: salt / nonce.\n+\t\t\t * iv[12-15]: upper bytes of IV in BE format.\n+\t\t\t */\n+\t\t\tmemcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset), 4);\n+\t\t\ttmp = (uint32_t *)iv;\n+\t\t\t*tmp = rte_be_to_cpu_32(*tmp);\n+\n+\t\t\tmemcpy(iv + 12,\n+\t\t\t rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset + 4), 4);\n+\t\t\ttmp = (uint32_t *)(iv + 12);\n+\t\t\t*tmp = rte_be_to_cpu_32(*tmp);\n+\t\t} else if (write_sa->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_AES_CBC) {\n+\t\t\tuint64_t *tmp;\n+\n+\t\t\tmemcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset), 16);\n+\t\t\ttmp = (uint64_t *)iv;\n+\t\t\t*tmp = rte_be_to_cpu_64(*tmp);\n+\t\t\ttmp = (uint64_t *)(iv + 8);\n+\t\t\t*tmp = rte_be_to_cpu_64(*tmp);\n+\t\t} else if (write_sa->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_3DES) {\n+\t\t\tuint64_t *tmp;\n+\n+\t\t\tmemcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset), 8);\n+\t\t\ttmp = (uint64_t *)iv;\n+\t\t\t*tmp = rte_be_to_cpu_64(*tmp);\n+\t\t}\n+\n+\t\t/* Trigger CTX reload to fetch new data from DRAM */\n+\t\troc_cpt_lf_ctx_reload(lf, write_sa);\n+\t\trte_delay_ms(1);\n+\t}\n+#else\n+\tRTE_SET_USED(lf);\n+#endif\n+\t/* Single buffer direct mode */\n+\tif (likely(m_src->next == NULL)) {\n+\t\tvoid *vaddr;\n+\n+\t\tif (unlikely(rte_pktmbuf_tailroom(m_src) < sess->max_extended_len)) {\n+\t\t\tplt_dp_err(\"Not enough tail room\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tvaddr = rte_pktmbuf_mtod(m_src, void *);\n+\t\tinst->dptr = (uint64_t)vaddr;\n+\t\tinst->rptr = (uint64_t)vaddr;\n+\n+\t\tw4.u64 = sess->inst.w4;\n+\t\tw4.s.param1 = m_src->data_len;\n+\t\tw4.s.dlen = m_src->data_len;\n+\n+\t\tw4.s.param2 = cop->param1.tls_record.content_type;\n+\t\tw4.s.opcode_minor = sess->tls.enable_padding * cop->aux_flags * 8;\n+\n+\t\tinst->w4.u64 = w4.u64;\n+\t} else if (is_sg_ver2 == false) {\n+\t\tstruct roc_sglist_comp *scatter_comp, *gather_comp;\n+\t\tuint32_t g_size_bytes, s_size_bytes;\n+\t\tuint32_t dlen;\n+\t\tint i;\n+\n+\t\tlast_seg = rte_pktmbuf_lastseg(m_src);\n+\n+\t\tif (unlikely(rte_pktmbuf_tailroom(last_seg) < sess->max_extended_len)) {\n+\t\t\tplt_dp_err(\"Not enough tail room (required: %d, available: %d)\",\n+\t\t\t\t sess->max_extended_len, rte_pktmbuf_tailroom(last_seg));\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tm_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);\n+\t\tif (unlikely(m_data == NULL)) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tin_buffer = (uint8_t *)m_data;\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* Input Gather List */\n+\t\ti = 0;\n+\t\tgather_comp = (struct roc_sglist_comp *)((uint8_t *)in_buffer + 8);\n+\n+\t\ti = fill_sg_comp_from_pkt(gather_comp, i, m_src);\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n+\n+\t\ti = 0;\n+\t\tscatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\ti = fill_sg_comp_from_pkt(scatter_comp, i, m_src);\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n+\n+\t\tdlen = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE;\n+\n+\t\tinst->dptr = (uint64_t)in_buffer;\n+\t\tinst->rptr = (uint64_t)in_buffer;\n+\n+\t\tw4.u64 = sess->inst.w4;\n+\t\tw4.s.dlen = dlen;\n+\t\tw4.s.param1 = rte_pktmbuf_pkt_len(m_src);\n+\t\tw4.s.param2 = cop->param1.tls_record.content_type;\n+\t\tw4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;\n+\t\tw4.s.opcode_minor = sess->tls.enable_padding * cop->aux_flags * 8;\n+\n+\t\t/* Output Scatter List */\n+\t\tlast_seg->data_len += sess->max_extended_len;\n+\t\tinst->w4.u64 = w4.u64;\n+\t} else {\n+\t\tstruct roc_sg2list_comp *scatter_comp, *gather_comp;\n+\t\tunion cpt_inst_w5 cpt_inst_w5;\n+\t\tunion cpt_inst_w6 cpt_inst_w6;\n+\t\tuint32_t g_size_bytes;\n+\t\tint i;\n+\n+\t\tlast_seg = rte_pktmbuf_lastseg(m_src);\n+\n+\t\tif (unlikely(rte_pktmbuf_tailroom(last_seg) < sess->max_extended_len)) {\n+\t\t\tplt_dp_err(\"Not enough tail room (required: %d, available: %d)\",\n+\t\t\t\t sess->max_extended_len, rte_pktmbuf_tailroom(last_seg));\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tm_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);\n+\t\tif (unlikely(m_data == NULL)) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tin_buffer = (uint8_t *)m_data;\n+\t\t/* Input Gather List */\n+\t\ti = 0;\n+\t\tgather_comp = (struct roc_sg2list_comp *)((uint8_t *)in_buffer);\n+\t\ti = fill_sg2_comp_from_pkt(gather_comp, i, m_src);\n+\n+\t\tcpt_inst_w5.s.gather_sz = ((i + 2) / 3);\n+\t\tg_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp);\n+\n+\t\ti = 0;\n+\t\tscatter_comp = (struct roc_sg2list_comp *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\ti = fill_sg2_comp_from_pkt(scatter_comp, i, m_src);\n+\n+\t\tcpt_inst_w6.s.scatter_sz = ((i + 2) / 3);\n+\n+\t\tcpt_inst_w5.s.dptr = (uint64_t)gather_comp;\n+\t\tcpt_inst_w6.s.rptr = (uint64_t)scatter_comp;\n+\n+\t\tinst->w5.u64 = cpt_inst_w5.u64;\n+\t\tinst->w6.u64 = cpt_inst_w6.u64;\n+\t\tw4.u64 = sess->inst.w4;\n+\t\tw4.s.dlen = rte_pktmbuf_pkt_len(m_src);\n+\t\tw4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT));\n+\t\tw4.s.opcode_minor = sess->tls.enable_padding * cop->aux_flags * 8;\n+\t\tw4.s.param1 = w4.s.dlen;\n+\t\tw4.s.param2 = cop->param1.tls_record.content_type;\n+\t\t/* Output Scatter List */\n+\t\tlast_seg->data_len += sess->max_extended_len;\n+\t\tinst->w4.u64 = w4.u64;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,\n+\t\t struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req,\n+\t\t struct cpt_inst_s *inst, const bool is_sg_ver2)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n+\tstruct rte_mbuf *m_src = sym_op->m_src;\n+\tunion cpt_inst_w4 w4;\n+\tuint8_t *in_buffer;\n+\tvoid *m_data;\n+\n+\tif (likely(m_src->next == NULL)) {\n+\t\tvoid *vaddr;\n+\n+\t\tvaddr = rte_pktmbuf_mtod(m_src, void *);\n+\n+\t\tinst->dptr = (uint64_t)vaddr;\n+\t\tinst->rptr = (uint64_t)vaddr;\n+\n+\t\tw4.u64 = sess->inst.w4;\n+\t\tw4.s.dlen = m_src->data_len;\n+\t\tw4.s.param1 = m_src->data_len;\n+\t\tinst->w4.u64 = w4.u64;\n+\t} else if (is_sg_ver2 == false) {\n+\t\tstruct roc_sglist_comp *scatter_comp, *gather_comp;\n+\t\tuint32_t g_size_bytes, s_size_bytes;\n+\t\tuint32_t dlen;\n+\t\tint i;\n+\n+\t\tm_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);\n+\t\tif (unlikely(m_data == NULL)) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tin_buffer = (uint8_t *)m_data;\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* Input Gather List */\n+\t\ti = 0;\n+\t\tgather_comp = (struct roc_sglist_comp *)((uint8_t *)in_buffer + 8);\n+\n+\t\ti = fill_sg_comp_from_pkt(gather_comp, i, m_src);\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n+\n+\t\ti = 0;\n+\t\tscatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\ti = fill_sg_comp_from_pkt(scatter_comp, i, m_src);\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n+\n+\t\tdlen = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE;\n+\n+\t\tinst->dptr = (uint64_t)in_buffer;\n+\t\tinst->rptr = (uint64_t)in_buffer;\n+\n+\t\tw4.u64 = sess->inst.w4;\n+\t\tw4.s.dlen = dlen;\n+\t\tw4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;\n+\t\tw4.s.param1 = rte_pktmbuf_pkt_len(m_src);\n+\t\tinst->w4.u64 = w4.u64;\n+\t} else {\n+\t\tstruct roc_sg2list_comp *scatter_comp, *gather_comp;\n+\t\tunion cpt_inst_w5 cpt_inst_w5;\n+\t\tunion cpt_inst_w6 cpt_inst_w6;\n+\t\tuint32_t g_size_bytes;\n+\t\tint i;\n+\n+\t\tm_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);\n+\t\tif (unlikely(m_data == NULL)) {\n+\t\t\tplt_dp_err(\"Error allocating meta buffer for request\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tin_buffer = (uint8_t *)m_data;\n+\t\t/* Input Gather List */\n+\t\ti = 0;\n+\n+\t\tgather_comp = (struct roc_sg2list_comp *)((uint8_t *)in_buffer);\n+\t\ti = fill_sg2_comp_from_pkt(gather_comp, i, m_src);\n+\n+\t\tcpt_inst_w5.s.gather_sz = ((i + 2) / 3);\n+\t\tg_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp);\n+\n+\t\ti = 0;\n+\t\tscatter_comp = (struct roc_sg2list_comp *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\ti = fill_sg2_comp_from_pkt(scatter_comp, i, m_src);\n+\n+\t\tcpt_inst_w6.s.scatter_sz = ((i + 2) / 3);\n+\n+\t\tcpt_inst_w5.s.dptr = (uint64_t)gather_comp;\n+\t\tcpt_inst_w6.s.rptr = (uint64_t)scatter_comp;\n+\n+\t\tinst->w5.u64 = cpt_inst_w5.u64;\n+\t\tinst->w6.u64 = cpt_inst_w6.u64;\n+\t\tw4.u64 = sess->inst.w4;\n+\t\tw4.s.dlen = rte_pktmbuf_pkt_len(m_src);\n+\t\tw4.s.param1 = w4.s.dlen;\n+\t\tw4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT));\n+\t\tinst->w4.u64 = w4.u64;\n+\t}\n+\n+\treturn 0;\n+}\n+#endif /* __CN10K_TLS_OPS_H__ */\n", "prefixes": [ "v2", "16/24" ] }