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GET /api/patches/135602/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 135602,
    "url": "http://patches.dpdk.org/api/patches/135602/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231227042119.72469-15-ajit.khaparde@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20231227042119.72469-15-ajit.khaparde@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20231227042119.72469-15-ajit.khaparde@broadcom.com",
    "date": "2023-12-27T04:21:15",
    "name": "[v3,14/18] net/bnxt: add tunnel TPA support",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "5e5ab9bd0e172bf4cce18564821fd649505cc368",
    "submitter": {
        "id": 501,
        "url": "http://patches.dpdk.org/api/people/501/?format=api",
        "name": "Ajit Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231227042119.72469-15-ajit.khaparde@broadcom.com/mbox/",
    "series": [
        {
            "id": 30672,
            "url": "http://patches.dpdk.org/api/series/30672/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30672",
            "date": "2023-12-27T04:21:01",
            "name": "bnxt patchset",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/30672/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/135602/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/135602/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
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            "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 20ACC40E68;\n\tWed, 27 Dec 2023 05:21:51 +0100 (CET)",
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            "from localhost.localdomain\n ([2605:a601:a780:1400:c066:75e3:74c8:50e6])\n by smtp.gmail.com with ESMTPSA id\n bt7-20020ac86907000000b00427e120889bsm1415488qtb.91.2023.12.26.20.21.43\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 26 Dec 2023 20:21:43 -0800 (PST)"
        ],
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        "X-Google-Smtp-Source": "\n AGHT+IFkEZV0gO9PR+P8xfc+Ky7MumgBnTIW8gV3DES9eH9MB4R/YQAUTjMpzkg1E+7ffF8Tm4wxZQ==",
        "X-Received": "by 2002:a05:622a:15c5:b0:427:88c0:14f7 with SMTP id\n d5-20020a05622a15c500b0042788c014f7mr10416878qty.77.1703650904573;\n Tue, 26 Dec 2023 20:21:44 -0800 (PST)",
        "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>",
        "Subject": "[PATCH v3 14/18] net/bnxt: add tunnel TPA support",
        "Date": "Tue, 26 Dec 2023 20:21:15 -0800",
        "Message-Id": "<20231227042119.72469-15-ajit.khaparde@broadcom.com>",
        "X-Mailer": "git-send-email 2.39.2 (Apple Git-143)",
        "In-Reply-To": "<20231227042119.72469-1-ajit.khaparde@broadcom.com>",
        "References": "<20231227042119.72469-1-ajit.khaparde@broadcom.com>",
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        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
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        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>\n\nThis patch adds support for tunnel TPA type.\nThe tunnel TPA support is brought in by the updated bit_field\ntnl_tpa_en(4) in hwrm_vnic_tpa_cfg_input->enables,\nwhich is used by the firmware to indicate the capability\nof the underlying hardware.\n\nThis patch updates hwrm HWRM_VNIC_TPA_CFG request\nfor vxlan, geneve and default tunnel type bit_fields.\n\nThe patch also updates to use the V3 TPA completion which\nthe P7 devices support.\n\nSigned-off-by: Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h      |  4 ++\n drivers/net/bnxt/bnxt_hwrm.c | 74 ++++++++++++++++++++++++++++++++++++\n drivers/net/bnxt/bnxt_rxr.c  |  9 +++--\n drivers/net/bnxt/bnxt_vnic.c | 16 ++++++++\n 4 files changed, 100 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex 576688bbff..2357e9f747 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -18,6 +18,7 @@\n #include <rte_lcore.h>\n #include <rte_spinlock.h>\n #include <rte_time.h>\n+#include <rte_eal_paging.h>\n \n #include \"bnxt_cpr.h\"\n #include \"bnxt_util.h\"\n@@ -119,6 +120,8 @@\n \t(BNXT_CHIP_P5_P7(bp) ? TPA_MAX_SEGS_TH : \\\n \t\t\t      TPA_MAX_SEGS)\n \n+#define BNXT_TPA_MAX_PAGES\t65536\n+\n /*\n  * Define the number of async completion rings to be used. Set to zero for\n  * configurations in which the maximum number of packet completion rings\n@@ -815,6 +818,7 @@ struct bnxt {\n #define BNXT_VNIC_CAP_ESP_SPI6_CAP\tBIT(12)\n #define BNXT_VNIC_CAP_AH_SPI_CAP\t(BNXT_VNIC_CAP_AH_SPI4_CAP | BNXT_VNIC_CAP_AH_SPI6_CAP)\n #define BNXT_VNIC_CAP_ESP_SPI_CAP\t(BNXT_VNIC_CAP_ESP_SPI4_CAP | BNXT_VNIC_CAP_ESP_SPI6_CAP)\n+#define BNXT_VNIC_CAP_VNIC_TUNNEL_TPA\tBIT(13)\n \n \tunsigned int\t\trx_nr_rings;\n \tunsigned int\t\trx_cp_nr_rings;\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 3c16abea69..f896a41653 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -1046,6 +1046,9 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)\n \tif (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP)\n \t\tbp->vnic_cap_flags |= BNXT_VNIC_CAP_ESP_SPI6_CAP;\n \n+\tif (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_HW_TUNNEL_TPA_CAP)\n+\t\tbp->vnic_cap_flags |= BNXT_VNIC_CAP_VNIC_TUNNEL_TPA;\n+\n \tbp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);\n \n \tHWRM_UNLOCK();\n@@ -2666,6 +2669,30 @@ int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,\n \treturn rc;\n }\n \n+#define BNXT_DFLT_TUNL_TPA_BMAP\t\t\t\t\t\\\n+\t(HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE |\t\\\n+\t HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV4 |\t\\\n+\t HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV6)\n+\n+static void bnxt_vnic_update_tunl_tpa_bmap(struct bnxt *bp,\n+\t\t\t\t\t   struct hwrm_vnic_tpa_cfg_input *req)\n+{\n+\tuint32_t tunl_tpa_bmap = BNXT_DFLT_TUNL_TPA_BMAP;\n+\n+\tif (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_VNIC_TUNNEL_TPA))\n+\t\treturn;\n+\n+\tif (bp->vxlan_port_cnt)\n+\t\ttunl_tpa_bmap |= HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN |\n+\t\t\tHWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE;\n+\n+\tif (bp->geneve_port_cnt)\n+\t\ttunl_tpa_bmap |= HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GENEVE;\n+\n+\treq->enables |= rte_cpu_to_le_32(HWRM_VNIC_TPA_CFG_INPUT_ENABLES_TNL_TPA_EN);\n+\treq->tnl_tpa_en_bitmap = rte_cpu_to_le_32(tunl_tpa_bmap);\n+}\n+\n int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,\n \t\t\tstruct bnxt_vnic_info *vnic, bool enable)\n {\n@@ -2714,6 +2741,29 @@ int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,\n \n \t\tif (BNXT_CHIP_P5_P7(bp))\n \t\t\treq.max_aggs = rte_cpu_to_le_16(bp->max_tpa_v2);\n+\n+\t\t/* For tpa v2 handle as per spec mss and log2 units */\n+\t\tif (BNXT_CHIP_P7(bp)) {\n+\t\t\tuint32_t nsegs, n, segs = 0;\n+\t\t\tuint16_t mss = bp->eth_dev->data->mtu - 40;\n+\t\t\tsize_t page_size = rte_mem_page_size();\n+\t\t\tuint32_t max_mbuf_frags =\n+\t\t\t\tBNXT_TPA_MAX_PAGES / (rte_mem_page_size() + 1);\n+\n+\t\t\t/* Calculate the number of segs based on mss */\n+\t\t\tif (mss <= page_size) {\n+\t\t\t\tn = page_size / mss;\n+\t\t\t\tnsegs = (max_mbuf_frags - 1) * n;\n+\t\t\t} else {\n+\t\t\t\tn = mss / page_size;\n+\t\t\t\tif (mss & (page_size - 1))\n+\t\t\t\t\tn++;\n+\t\t\t\tnsegs = (max_mbuf_frags - n) / n;\n+\t\t\t}\n+\t\t\tsegs = rte_log2_u32(nsegs);\n+\t\t\treq.max_agg_segs = rte_cpu_to_le_16(segs);\n+\t\t}\n+\t\tbnxt_vnic_update_tunl_tpa_bmap(bp, &req);\n \t}\n \treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n \n@@ -4242,6 +4292,27 @@ int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)\n \treturn rc;\n }\n \n+static int bnxt_hwrm_set_tpa(struct bnxt *bp)\n+{\n+\tstruct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;\n+\tuint64_t rx_offloads = dev_conf->rxmode.offloads;\n+\tbool tpa_flags = 0;\n+\tint rc, i;\n+\n+\ttpa_flags = (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ?  true : false;\n+\tfor (i = 0; i < bp->max_vnics; i++) {\n+\t\tstruct bnxt_vnic_info *vnic = &bp->vnic_info[i];\n+\n+\t\tif (vnic->fw_vnic_id == INVALID_HW_RING_ID)\n+\t\t\tcontinue;\n+\n+\t\trc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, tpa_flags);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\treturn 0;\n+}\n+\n int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,\n \t\t\t\tuint8_t tunnel_type)\n {\n@@ -4278,6 +4349,8 @@ int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,\n \n \tHWRM_UNLOCK();\n \n+\tbnxt_hwrm_set_tpa(bp);\n+\n \treturn rc;\n }\n \n@@ -4346,6 +4419,7 @@ int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,\n \t\tbp->ecpri_port_cnt = 0;\n \t}\n \n+\tbnxt_hwrm_set_tpa(bp);\n \treturn rc;\n }\n \ndiff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c\nindex d0706874a6..3542975600 100644\n--- a/drivers/net/bnxt/bnxt_rxr.c\n+++ b/drivers/net/bnxt/bnxt_rxr.c\n@@ -153,7 +153,8 @@ static void bnxt_rx_ring_reset(void *arg)\n \t\trxr = rxq->rx_ring;\n \t\t/* Disable and flush TPA before resetting the RX ring */\n \t\tif (rxr->tpa_info)\n-\t\t\tbnxt_hwrm_vnic_tpa_cfg(bp, rxq->vnic, false);\n+\t\t\tbnxt_vnic_tpa_cfg(bp, rxq->queue_id, false);\n+\n \t\trc = bnxt_hwrm_rx_ring_reset(bp, i);\n \t\tif (rc) {\n \t\t\tPMD_DRV_LOG(ERR, \"Rx ring%d reset failed\\n\", i);\n@@ -163,12 +164,13 @@ static void bnxt_rx_ring_reset(void *arg)\n \t\tbnxt_rx_queue_release_mbufs(rxq);\n \t\trxr->rx_raw_prod = 0;\n \t\trxr->ag_raw_prod = 0;\n+\t\trxr->ag_cons = 0;\n \t\trxr->rx_next_cons = 0;\n \t\tbnxt_init_one_rx_ring(rxq);\n \t\tbnxt_db_write(&rxr->rx_db, rxr->rx_raw_prod);\n \t\tbnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod);\n \t\tif (rxr->tpa_info)\n-\t\t\tbnxt_hwrm_vnic_tpa_cfg(bp, rxq->vnic, true);\n+\t\t\tbnxt_vnic_tpa_cfg(bp, rxq->queue_id, true);\n \n \t\trxq->in_reset = 0;\n \t}\n@@ -1151,7 +1153,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,\n \t\treturn -EBUSY;\n \n \tif (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START ||\n-\t    cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2) {\n+\t    cmp_type == RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 ||\n+\t    cmp_type == RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3) {\n \t\tbnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp,\n \t\t\t       (struct rx_tpa_start_cmpl_hi *)rxcmp1);\n \t\trc = -EINVAL; /* Continue w/o new mbuf */\ndiff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c\nindex 5ea34f7cb6..5092a7d774 100644\n--- a/drivers/net/bnxt/bnxt_vnic.c\n+++ b/drivers/net/bnxt/bnxt_vnic.c\n@@ -464,7 +464,9 @@ bnxt_vnic_queue_delete(struct bnxt *bp, uint16_t vnic_idx)\n static struct bnxt_vnic_info*\n bnxt_vnic_queue_create(struct bnxt *bp, int32_t vnic_id, uint16_t q_index)\n {\n+\tstruct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;\n \tuint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;\n+\tuint64_t rx_offloads = dev_conf->rxmode.offloads;\n \tstruct bnxt_vnic_info *vnic;\n \tstruct bnxt_rx_queue *rxq = NULL;\n \tint32_t rc = -EINVAL;\n@@ -523,6 +525,12 @@ bnxt_vnic_queue_create(struct bnxt *bp, int32_t vnic_id, uint16_t q_index)\n \t\tgoto cleanup;\n \t}\n \n+\trc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,\n+\t\t\t\t   (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ?\n+\t\t\t\t    true : false);\n+\tif (rc)\n+\t\tPMD_DRV_LOG(DEBUG, \"Failed to configure TPA on this vnic %d\\n\", q_index);\n+\n \trc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);\n \tif (rc) {\n \t\tPMD_DRV_LOG(DEBUG, \"Failed to configure vnic plcmode %d\\n\",\n@@ -658,7 +666,9 @@ bnxt_vnic_rss_create(struct bnxt *bp,\n \t\t     struct bnxt_vnic_rss_info *rss_info,\n \t\t     uint16_t vnic_id)\n {\n+\tstruct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;\n \tuint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;\n+\tuint64_t rx_offloads = dev_conf->rxmode.offloads;\n \tstruct bnxt_vnic_info *vnic;\n \tstruct bnxt_rx_queue *rxq = NULL;\n \tuint32_t idx, nr_ctxs, config_rss = 0;\n@@ -741,6 +751,12 @@ bnxt_vnic_rss_create(struct bnxt *bp,\n \t\tgoto fail_cleanup;\n \t}\n \n+\trc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,\n+\t\t\t\t   (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ?\n+\t\t\t\t    true : false);\n+\tif (rc)\n+\t\tPMD_DRV_LOG(DEBUG, \"Failed to configure TPA on this vnic %d\\n\", idx);\n+\n \trc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);\n \tif (rc) {\n \t\tPMD_DRV_LOG(ERR, \"Failed to configure vnic plcmode %d\\n\",\n",
    "prefixes": [
        "v3",
        "14/18"
    ]
}