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GET /api/patches/135493/?format=api
{ "id": 135493, "url": "http://patches.dpdk.org/api/patches/135493/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231221180529.18687-19-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231221180529.18687-19-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231221180529.18687-19-ajit.khaparde@broadcom.com", "date": "2023-12-21T18:05:29", "name": "[18/18] net/bnxt: enable SSE mode for compressed CQE", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d1aa76bd3512f4a1fe6f429cd35759c2f845aacb", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231221180529.18687-19-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 30650, "url": "http://patches.dpdk.org/api/series/30650/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30650", "date": "2023-12-21T18:05:11", "name": "bnxt patchset", "version": 1, "mbox": "http://patches.dpdk.org/series/30650/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135493/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/135493/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 23F4343752;\n\tThu, 21 Dec 2023 19:08:04 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 89B7142F1F;\n\tThu, 21 Dec 2023 19:06:03 +0100 (CET)", "from mail-pl1-f172.google.com (mail-pl1-f172.google.com\n [209.85.214.172])\n by mails.dpdk.org (Postfix) with ESMTP id 8E17E42EE6\n for <dev@dpdk.org>; Thu, 21 Dec 2023 19:06:00 +0100 (CET)", "by mail-pl1-f172.google.com with SMTP id\n d9443c01a7336-1d04c097e34so8037025ad.0\n for <dev@dpdk.org>; Thu, 21 Dec 2023 10:06:00 -0800 (PST)", "from C02GC2QQMD6T.wifi.broadcom.net ([192.19.223.252])\n by smtp.gmail.com with ESMTPSA id\n j17-20020a170902da9100b001d3b3ac2d7bsm1916379plx.245.2023.12.21.10.05.58\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 21 Dec 2023 10:05:58 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=broadcom.com; s=google; t=1703181959; x=1703786759; darn=dpdk.org;\n h=mime-version:references:in-reply-to:message-id:date:subject:cc:to\n :from:from:to:cc:subject:date:message-id:reply-to;\n bh=xjhLpkkohEHkP5/0ByOkgCHxIfzP7MAhfNDIm1eSfbs=;\n b=ftAkTwaCN1Iq3N+d7V+frco59I9NgpIfnj+LpOP7K+i9TmT7FVIxdfAL1at93JNg3E\n mngFSd45MhQ2XJplhX0+nRbSLccVodLzi7nzq2OSOxloUR84e+SW0KvoQljNvNMb/wqv\n L3+3NLXySHhiIxpWa+yI19VN0j+tIN1gMmit0=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1703181959; x=1703786759;\n h=mime-version:references:in-reply-to:message-id:date:subject:cc:to\n :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to;\n bh=xjhLpkkohEHkP5/0ByOkgCHxIfzP7MAhfNDIm1eSfbs=;\n b=jpAm11PMptf2L/a6Hbnqw4d+XiWzo/mCi1AVbrS1BS/yoluBfYnbqmOreU5KUZUxv9\n qd/TrPa94kouaUYXZmyd78ey4pXluYs8uYkcp2EnR/I7L0z9Vvg1DN89A4745rHbgUGX\n MJAMsnYdb/yQXek9VSSOnSbWopj2uKDU3a0tkah5TdZ7ldGWzjC/YhtqDtxuIXOyNW3Z\n eQh8ynEx3LM45SU8ZY1wOWb5VxuTFHdnpzmQxRUfBKGUmQd5MWbqF5zt2WuH101Vi4rv\n n6UO+psK1QMSd/NIEL8Rgg+5ydrenSfVl4K7uBDf9S762LC+qexMaTgNDN1SrzYy+Ixj\n XbXw==", "X-Gm-Message-State": "AOJu0Yyzg5DpcPILZY1VCO2Ql4LD/WZutTLJ2KYVpJ1HhLpsgnohP+hf\n Car1Hamr0YZHcmgX2YPiyoKP0IGP7D/6+sDtb/fyNZKN9bfIi7eWpVbPTPzI6Nu5x3UECxsENCN\n /0wuClhIwqrmQ1BZdVp2hfixjCmVct/ApUdN1w1FxuQiW6qTVwqokjxx/3gkJTcIrWjsPwQngvs\n k=", "X-Google-Smtp-Source": "\n AGHT+IFnn17JSjacH+vVqMZYkmQd3Bz9/aLBm41usU2EUNrH385LR326lbxabYM0j0p0YlUCFAGcOg==", "X-Received": "by 2002:a17:902:6507:b0:1d3:b609:eb0b with SMTP id\n b7-20020a170902650700b001d3b609eb0bmr102410plk.27.1703181959332;\n Thu, 21 Dec 2023 10:05:59 -0800 (PST)", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>", "Subject": "[PATCH 18/18] net/bnxt: enable SSE mode for compressed CQE", "Date": "Thu, 21 Dec 2023 10:05:29 -0800", "Message-Id": "<20231221180529.18687-19-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.39.2 (Apple Git-143)", "In-Reply-To": "<20231221180529.18687-1-ajit.khaparde@broadcom.com>", "References": "<20231221180529.18687-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "multipart/signed; protocol=\"application/pkcs7-signature\";\n micalg=sha-256; boundary=\"000000000000b433dd060d08f3a7\"", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "P7 device family supports 16 byte Rx completions.\nEnable SSE vector mode for compressed Rx CQE processing.\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>\n---\n drivers/net/bnxt/bnxt_ethdev.c | 16 ++-\n drivers/net/bnxt/bnxt_rxr.h | 2 +\n drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 167 +++++++++++++++++++++++++--\n 3 files changed, 173 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex bd8c7557dd..f9cd234bb6 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -1377,7 +1377,8 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)\n \t * asynchronous completions and receive completions can be placed in\n \t * the same completion ring.\n \t */\n-\tif (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))\n+\tif ((BNXT_TRUFLOW_EN(bp) && !BNXT_CHIP_P7(bp)) ||\n+\t !BNXT_NUM_ASYNC_CPR(bp))\n \t\tgoto use_scalar_rx;\n \n \t/*\n@@ -1410,12 +1411,19 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)\n \t\t\treturn bnxt_crx_pkts_vec_avx2;\n \t\treturn bnxt_recv_pkts_vec_avx2;\n \t}\n- #endif\n+#endif\n \tif (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {\n \t\tPMD_DRV_LOG(INFO,\n \t\t\t \"Using SSE vector mode receive for port %d\\n\",\n \t\t\t eth_dev->data->port_id);\n \t\tbp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;\n+\t\tif (bnxt_compressed_rx_cqe_mode_enabled(bp)) {\n+#if defined(RTE_ARCH_ARM64)\n+\t\t\tgoto use_scalar_rx;\n+#else\n+\t\t\treturn bnxt_crx_pkts_vec;\n+#endif\n+\t\t}\n \t\treturn bnxt_recv_pkts_vec;\n \t}\n \n@@ -1445,7 +1453,8 @@ bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)\n \t */\n \tif (eth_dev->data->scattered_rx ||\n \t (offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) ||\n-\t BNXT_TRUFLOW_EN(bp) || bp->ieee_1588)\n+\t (BNXT_TRUFLOW_EN(bp) && !BNXT_CHIP_P7(bp)) ||\n+\t bp->ieee_1588)\n \t\tgoto use_scalar_tx;\n \n #if defined(RTE_ARCH_X86)\n@@ -3125,6 +3134,7 @@ static const struct {\n } bnxt_rx_burst_info[] = {\n \t{bnxt_recv_pkts,\t\t\"Scalar\"},\n #if defined(RTE_ARCH_X86)\n+\t{bnxt_crx_pkts_vec,\t\t\"Vector SSE\"},\n \t{bnxt_recv_pkts_vec,\t\t\"Vector SSE\"},\n #endif\n #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)\ndiff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h\nindex a474a69ae3..d36cbded1d 100644\n--- a/drivers/net/bnxt/bnxt_rxr.h\n+++ b/drivers/net/bnxt/bnxt_rxr.h\n@@ -156,6 +156,8 @@ int bnxt_flush_rx_cmp(struct bnxt_cp_ring_info *cpr);\n #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)\n uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t uint16_t nb_pkts);\n+uint16_t bnxt_crx_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t uint16_t nb_pkts);\n int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);\n #endif\n \ndiff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c\nindex e99a547f58..c04b33a382 100644\n--- a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c\n+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c\n@@ -54,15 +54,9 @@\n \n static inline void\n descs_to_mbufs(__m128i mm_rxcmp[4], __m128i mm_rxcmp1[4],\n-\t __m128i mbuf_init, struct rte_mbuf **mbuf,\n-\t struct bnxt_rx_ring_info *rxr)\n+\t __m128i mbuf_init, const __m128i shuf_msk,\n+\t struct rte_mbuf **mbuf, struct bnxt_rx_ring_info *rxr)\n {\n-\tconst __m128i shuf_msk =\n-\t\t_mm_set_epi8(15, 14, 13, 12, /* rss */\n-\t\t\t 0xFF, 0xFF, /* vlan_tci (zeroes) */\n-\t\t\t 3, 2, /* data_len */\n-\t\t\t 0xFF, 0xFF, 3, 2, /* pkt_len */\n-\t\t\t 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */\n \tconst __m128i flags_type_mask =\n \t\t_mm_set1_epi32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);\n \tconst __m128i flags2_mask1 =\n@@ -166,6 +160,12 @@ recv_burst_vec_sse(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \tint nb_rx_pkts = 0;\n \tconst __m128i valid_target =\n \t\t_mm_set1_epi32(!!(raw_cons & cp_ring_size));\n+\tconst __m128i shuf_msk =\n+\t\t_mm_set_epi8(15, 14, 13, 12, /* rss */\n+\t\t\t 0xFF, 0xFF, /* vlan_tci (zeroes) */\n+\t\t\t 3, 2, /* data_len */\n+\t\t\t 0xFF, 0xFF, 3, 2, /* pkt_len */\n+\t\t\t 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */\n \tint i;\n \n \t/* If Rx Q was stopped return */\n@@ -264,7 +264,7 @@ recv_burst_vec_sse(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\tif (num_valid == 0)\n \t\t\tbreak;\n \n-\t\tdescs_to_mbufs(rxcmp, rxcmp1, mbuf_init, &rx_pkts[nb_rx_pkts],\n+\t\tdescs_to_mbufs(rxcmp, rxcmp1, mbuf_init, shuf_msk, &rx_pkts[nb_rx_pkts],\n \t\t\t rxr);\n \t\tnb_rx_pkts += num_valid;\n \n@@ -283,6 +283,134 @@ recv_burst_vec_sse(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \treturn nb_rx_pkts;\n }\n \n+static uint16_t\n+crx_burst_vec_sse(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct bnxt_rx_queue *rxq = rx_queue;\n+\tconst __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);\n+\tstruct bnxt_cp_ring_info *cpr = rxq->cp_ring;\n+\tstruct bnxt_rx_ring_info *rxr = rxq->rx_ring;\n+\tuint16_t cp_ring_size = cpr->cp_ring_struct->ring_size;\n+\tuint16_t rx_ring_size = rxr->rx_ring_struct->ring_size;\n+\tstruct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;\n+\tuint64_t valid, desc_valid_mask = ~0ULL;\n+\tconst __m128i info3_v_mask = _mm_set1_epi32(CMPL_BASE_V);\n+\tuint32_t raw_cons = cpr->cp_raw_cons;\n+\tuint32_t cons, mbcons;\n+\tint nb_rx_pkts = 0;\n+\tconst __m128i valid_target =\n+\t\t_mm_set1_epi32(!!(raw_cons & cp_ring_size));\n+\tconst __m128i shuf_msk =\n+\t\t_mm_set_epi8(7, 6, 5, 4, /* rss */\n+\t\t\t 0xFF, 0xFF, /* vlan_tci (zeroes) */\n+\t\t\t 3, 2, /* data_len */\n+\t\t\t 0xFF, 0xFF, 3, 2, /* pkt_len */\n+\t\t\t 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */\n+\tint i;\n+\n+\t/* If Rx Q was stopped return */\n+\tif (unlikely(!rxq->rx_started))\n+\t\treturn 0;\n+\n+\tif (rxq->rxrearm_nb >= rxq->rx_free_thresh)\n+\t\tbnxt_rxq_rearm(rxq, rxr);\n+\n+\tcons = raw_cons & (cp_ring_size - 1);\n+\tmbcons = raw_cons & (rx_ring_size - 1);\n+\n+\t/* Prefetch first four descriptor pairs. */\n+\trte_prefetch0(&cp_desc_ring[cons]);\n+\n+\t/* Ensure that we do not go past the ends of the rings. */\n+\tnb_pkts = RTE_MIN(nb_pkts, RTE_MIN(rx_ring_size - mbcons,\n+\t\t\t\t\t cp_ring_size - cons));\n+\t/*\n+\t * If we are at the end of the ring, ensure that descriptors after the\n+\t * last valid entry are not treated as valid. Otherwise, force the\n+\t * maximum number of packets to receive to be a multiple of the per-\n+\t * loop count.\n+\t */\n+\tif (nb_pkts < BNXT_RX_DESCS_PER_LOOP_VEC128) {\n+\t\tdesc_valid_mask >>=\n+\t\t\t16 * (BNXT_RX_DESCS_PER_LOOP_VEC128 - nb_pkts);\n+\t} else {\n+\t\tnb_pkts =\n+\t\t\tRTE_ALIGN_FLOOR(nb_pkts, BNXT_RX_DESCS_PER_LOOP_VEC128);\n+\t}\n+\n+\t/* Handle RX burst request */\n+\tfor (i = 0; i < nb_pkts; i += BNXT_RX_DESCS_PER_LOOP_VEC128,\n+\t\t\t\t cons += BNXT_RX_DESCS_PER_LOOP_VEC128,\n+\t\t\t\t mbcons += BNXT_RX_DESCS_PER_LOOP_VEC128) {\n+\t\t__m128i rxcmp1[BNXT_RX_DESCS_PER_LOOP_VEC128];\n+\t\t__m128i rxcmp[BNXT_RX_DESCS_PER_LOOP_VEC128];\n+\t\t__m128i tmp0, tmp1, info3_v;\n+\t\tuint32_t num_valid;\n+\n+\t\t/* Copy four mbuf pointers to output array. */\n+\t\ttmp0 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons]);\n+#ifdef RTE_ARCH_X86_64\n+\t\ttmp1 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons + 2]);\n+#endif\n+\t\t_mm_storeu_si128((void *)&rx_pkts[i], tmp0);\n+#ifdef RTE_ARCH_X86_64\n+\t\t_mm_storeu_si128((void *)&rx_pkts[i + 2], tmp1);\n+#endif\n+\n+\t\t/* Prefetch four descriptor pairs for next iteration. */\n+\t\tif (i + BNXT_RX_DESCS_PER_LOOP_VEC128 < nb_pkts)\n+\t\t\trte_prefetch0(&cp_desc_ring[cons + 4]);\n+\n+\t\t/*\n+\t\t * Load the four current descriptors into SSE registers in\n+\t\t * reverse order to ensure consistent state.\n+\t\t */\n+\t\trxcmp[3] = _mm_load_si128((void *)&cp_desc_ring[cons + 3]);\n+\t\trte_compiler_barrier();\n+\t\trxcmp[2] = _mm_load_si128((void *)&cp_desc_ring[cons + 2]);\n+\t\trte_compiler_barrier();\n+\t\trxcmp[1] = _mm_load_si128((void *)&cp_desc_ring[cons + 1]);\n+\t\trte_compiler_barrier();\n+\t\trxcmp[0] = _mm_load_si128((void *)&cp_desc_ring[cons + 0]);\n+\n+\t\ttmp1 = _mm_unpackhi_epi32(rxcmp[2], rxcmp[3]);\n+\t\ttmp0 = _mm_unpackhi_epi32(rxcmp[0], rxcmp[1]);\n+\n+\t\t/* Isolate descriptor valid flags. */\n+\t\tinfo3_v = _mm_and_si128(_mm_unpacklo_epi64(tmp0, tmp1),\n+\t\t\t\t\tinfo3_v_mask);\n+\t\tinfo3_v = _mm_xor_si128(info3_v, valid_target);\n+\n+\t\t/*\n+\t\t * Pack the 128-bit array of valid descriptor flags into 64\n+\t\t * bits and count the number of set bits in order to determine\n+\t\t * the number of valid descriptors.\n+\t\t */\n+\t\tvalid = _mm_cvtsi128_si64(_mm_packs_epi32(info3_v, info3_v));\n+\t\tnum_valid = __builtin_popcountll(valid & desc_valid_mask);\n+\n+\t\tif (num_valid == 0)\n+\t\t\tbreak;\n+\n+\t\tdescs_to_mbufs(rxcmp, rxcmp1, mbuf_init, shuf_msk, &rx_pkts[nb_rx_pkts],\n+\t\t\t rxr);\n+\t\tnb_rx_pkts += num_valid;\n+\n+\t\tif (num_valid < BNXT_RX_DESCS_PER_LOOP_VEC128)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (nb_rx_pkts) {\n+\t\trxr->rx_raw_prod = RING_ADV(rxr->rx_raw_prod, nb_rx_pkts);\n+\n+\t\trxq->rxrearm_nb += nb_rx_pkts;\n+\t\tcpr->cp_raw_cons += nb_rx_pkts;\n+\t\tbnxt_db_cq(cpr);\n+\t}\n+\n+\treturn nb_rx_pkts;\n+}\n+\n uint16_t\n bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n {\n@@ -304,6 +432,27 @@ bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \treturn cnt + recv_burst_vec_sse(rx_queue, rx_pkts + cnt, nb_pkts);\n }\n \n+uint16_t\n+bnxt_crx_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tuint16_t cnt = 0;\n+\n+\twhile (nb_pkts > RTE_BNXT_MAX_RX_BURST) {\n+\t\tuint16_t burst;\n+\n+\t\tburst = crx_burst_vec_sse(rx_queue, rx_pkts + cnt,\n+\t\t\t\t\t RTE_BNXT_MAX_RX_BURST);\n+\n+\t\tcnt += burst;\n+\t\tnb_pkts -= burst;\n+\n+\t\tif (burst < RTE_BNXT_MAX_RX_BURST)\n+\t\t\treturn cnt;\n+\t}\n+\n+\treturn cnt + crx_burst_vec_sse(rx_queue, rx_pkts + cnt, nb_pkts);\n+}\n+\n static void\n bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)\n {\n", "prefixes": [ "18/18" ] }