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GET /api/patches/135477/?format=api
{ "id": 135477, "url": "http://patches.dpdk.org/api/patches/135477/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231221180529.18687-3-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231221180529.18687-3-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231221180529.18687-3-ajit.khaparde@broadcom.com", "date": "2023-12-21T18:05:13", "name": "[02/18] net/bnxt: add support for compressed Rx CQE", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3f9603d4f613c1349e153959115443618fc4256a", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231221180529.18687-3-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 30650, "url": "http://patches.dpdk.org/api/series/30650/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30650", "date": "2023-12-21T18:05:11", "name": "bnxt patchset", "version": 1, "mbox": "http://patches.dpdk.org/series/30650/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135477/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/135477/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DECCD43752;\n\tThu, 21 Dec 2023 19:05:51 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7655242E63;\n\tThu, 21 Dec 2023 19:05:40 +0100 (CET)", "from mail-pl1-f178.google.com (mail-pl1-f178.google.com\n [209.85.214.178])\n by mails.dpdk.org (Postfix) with ESMTP id D270842E58\n for <dev@dpdk.org>; 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s=20230601; t=1703181937; x=1703786737;\n h=mime-version:references:in-reply-to:message-id:date:subject:cc:to\n :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to;\n bh=o0lnBioD/i6gIqyXJtqjBkJn2/jtoDGszqKFjzXAM84=;\n b=S2fNaVb/4gW3pxhAhjskAHvAXiX+g/nKOK6J2hdOJQPwM+UiXOKN5EKpZ7bwGwterr\n 7WBplNMWcvDo7LVUm81ZDOuXP4Lz+uwztBM09frAIMjkz452qmjXdEVWKbpLy4TSAYVg\n VHHVb518ffjR0OnibKKdZdUVcurM+NKdw8PdQu/HRmm5n4oD95heKp8FiGyxLsIVINcF\n h6swRtvl+YhoU66P9R9H+/ROsqpqaYATNtBd2L55O06EkZAh5en2pNL/TazjS7hAfBUA\n T04gwegrqGSo7CFyN6NhzRme6SS9/JlVWbBgIEb0ljOLq3sITAxFOyeNo7KXWfRBgGRW\n 9wZQ==", "X-Gm-Message-State": "AOJu0Yy7keFjTJO5N+AQu5qmyJ3F/Za/Oa+KVVPgS0UnilvT+UgIhKDL\n Y6A4r6dSu2BUVyJqFIlD0BqGeoNgF5rOtkBb2HPAcFkEDAQwdTaQ6Of//ih9Fy9AHsp9IHucpaN\n VrX/vTfoDz2Gqg1BYSuNgfltWt5Vu7ycUv8ptkQ4cb9VJnR/jeBRQTyugkNHrXR+5Y9BdSiPrOB\n o=", "X-Google-Smtp-Source": "\n AGHT+IHwP13se/Otu5R0UwgzzQzhQ0QuBASlyNqhC5T/+WOqoop36iLx/+LNYRjnlCwAUSZnwBFPMQ==", "X-Received": "by 2002:a17:903:41ce:b0:1d0:b503:1e8e with SMTP id\n u14-20020a17090341ce00b001d0b5031e8emr7077ple.109.1703181937084;\n Thu, 21 Dec 2023 10:05:37 -0800 (PST)", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Somnath Kotur <somnath.kotur@broadcom.com>,\n Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>", "Subject": "[PATCH 02/18] net/bnxt: add support for compressed Rx CQE", "Date": "Thu, 21 Dec 2023 10:05:13 -0800", "Message-Id": "<20231221180529.18687-3-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.39.2 (Apple Git-143)", "In-Reply-To": "<20231221180529.18687-1-ajit.khaparde@broadcom.com>", "References": "<20231221180529.18687-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "multipart/signed; protocol=\"application/pkcs7-signature\";\n micalg=sha-256; boundary=\"0000000000006466cd060d08f22c\"", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Thor2 supports compressed Rx completions instead of the\nfull featured 32-byte Rx completions.\nAdd support for these compressed CQEs in scalar mode.\nUnlike in the typical Rx completions, the hardware does\nnot provide the opaque field to index into the aggregator\ndescriptor ring. So maintain the consumer index for the\naggregation ring in the driver.\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>\nReviewed-by: Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h | 17 +++\n drivers/net/bnxt/bnxt_ethdev.c | 51 +++++++++\n drivers/net/bnxt/bnxt_hwrm.c | 16 +++\n drivers/net/bnxt/bnxt_ring.c | 13 ++-\n drivers/net/bnxt/bnxt_rxr.c | 201 +++++++++++++++++++++++++++++++++\n drivers/net/bnxt/bnxt_rxr.h | 55 +++++++++\n 6 files changed, 352 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex 4b5c2c4b8f..cfdbfd3f54 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -782,6 +782,7 @@ struct bnxt {\n #define\tBNXT_MULTIROOT_EN(bp)\t\t\t\\\n \t((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN)\n \n+#define\tBNXT_FLAGS2_COMPRESSED_RX_CQE\t\tBIT(5)\n \tuint32_t\t\tfw_cap;\n #define BNXT_FW_CAP_HOT_RESET\t\tBIT(0)\n #define BNXT_FW_CAP_IF_CHANGE\t\tBIT(1)\n@@ -814,6 +815,7 @@ struct bnxt {\n #define BNXT_VNIC_CAP_VLAN_RX_STRIP\tBIT(3)\n #define BNXT_RX_VLAN_STRIP_EN(bp)\t((bp)->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)\n #define BNXT_VNIC_CAP_OUTER_RSS_TRUSTED_VF\tBIT(4)\n+#define BNXT_VNIC_CAP_L2_CQE_MODE\t\tBIT(8)\n \tunsigned int\t\trx_nr_rings;\n \tunsigned int\t\trx_cp_nr_rings;\n \tunsigned int\t\trx_num_qs_per_vnic;\n@@ -1013,6 +1015,21 @@ inline uint16_t bnxt_max_rings(struct bnxt *bp)\n \treturn max_rings;\n }\n \n+static inline bool\n+bnxt_compressed_rx_cqe_mode_enabled(struct bnxt *bp)\n+{\n+\tuint64_t rx_offloads = bp->eth_dev->data->dev_conf.rxmode.offloads;\n+\n+\tif (bp->vnic_cap_flags & BNXT_VNIC_CAP_L2_CQE_MODE &&\n+\t\tbp->flags2 & BNXT_FLAGS2_COMPRESSED_RX_CQE &&\n+\t\t!(rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) &&\n+\t\t!(rx_offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) &&\n+\t\t!bp->num_reps && !bp->ieee_1588)\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n #define BNXT_FC_TIMER\t1 /* Timer freq in Sec Flow Counters */\n \n /**\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex 75e968394f..0f1c4326c4 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -103,6 +103,7 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {\n #define BNXT_DEVARG_REP_FC_F2R \"rep-fc-f2r\"\n #define BNXT_DEVARG_APP_ID\t\"app-id\"\n #define BNXT_DEVARG_IEEE_1588\t\"ieee-1588\"\n+#define BNXT_DEVARG_CQE_MODE\t\"cqe-mode\"\n \n static const char *const bnxt_dev_args[] = {\n \tBNXT_DEVARG_REPRESENTOR,\n@@ -116,9 +117,15 @@ static const char *const bnxt_dev_args[] = {\n \tBNXT_DEVARG_REP_FC_F2R,\n \tBNXT_DEVARG_APP_ID,\n \tBNXT_DEVARG_IEEE_1588,\n+\tBNXT_DEVARG_CQE_MODE,\n \tNULL\n };\n \n+/*\n+ * cqe-mode = an non-negative 8-bit number\n+ */\n+#define BNXT_DEVARG_CQE_MODE_INVALID(val)\t\t((val) > 1)\n+\n /*\n * app-id = an non-negative 8-bit number\n */\n@@ -5706,6 +5713,43 @@ bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,\n \treturn 0;\n }\n \n+static int\n+bnxt_parse_devarg_cqe_mode(__rte_unused const char *key,\n+\t\t\t const char *value, void *opaque_arg)\n+{\n+\tstruct bnxt *bp = opaque_arg;\n+\tunsigned long cqe_mode;\n+\tchar *end = NULL;\n+\n+\tif (!value || !opaque_arg) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t \"Invalid parameter passed to cqe-mode \"\n+\t\t\t \"devargs.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tcqe_mode = strtoul(value, &end, 10);\n+\tif (end == NULL || *end != '\\0' ||\n+\t (cqe_mode == ULONG_MAX && errno == ERANGE)) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t \"Invalid parameter passed to cqe-mode \"\n+\t\t\t \"devargs.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (BNXT_DEVARG_CQE_MODE_INVALID(cqe_mode)) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid cqe-mode(%d) devargs.\\n\",\n+\t\t\t (uint16_t)cqe_mode);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (cqe_mode == 1)\n+\t\tbp->flags2 |= BNXT_FLAGS2_COMPRESSED_RX_CQE;\n+\tPMD_DRV_LOG(INFO, \"cqe-mode=%d feature enabled.\\n\", (uint8_t)cqe_mode);\n+\n+\treturn 0;\n+}\n+\n static int\n bnxt_parse_devarg_app_id(__rte_unused const char *key,\n \t\t\t\t const char *value, void *opaque_arg)\n@@ -6047,6 +6091,13 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)\n \trte_kvargs_process(kvlist, BNXT_DEVARG_IEEE_1588,\n \t\t\t bnxt_parse_devarg_ieee_1588, bp);\n \n+\t/*\n+\t * Handler for \"cqe-mode\" devarg.\n+\t * Invoked as for ex: \"-a 000:00:0d.0,cqe-mode=1\"\n+\t */\n+\trte_kvargs_process(kvlist, BNXT_DEVARG_CQE_MODE,\n+\t\t\t bnxt_parse_devarg_cqe_mode, bp);\n+\n \trte_kvargs_free(kvlist);\n \treturn ret;\n }\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 37cf179938..378be997d3 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -2228,6 +2228,12 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \treq.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);\n \n config_mru:\n+\tif (bnxt_compressed_rx_cqe_mode_enabled(bp)) {\n+\t\treq.l2_cqe_mode = HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_COMPRESSED;\n+\t\tenables |= HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE;\n+\t\tPMD_DRV_LOG(DEBUG, \"Enabling compressed Rx CQE\\n\");\n+\t}\n+\n \treq.enables = rte_cpu_to_le_32(enables);\n \treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n \treq.mru = rte_cpu_to_le_16(vnic->mru);\n@@ -2604,6 +2610,16 @@ int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,\n \tstruct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };\n \tstruct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n \n+\tif (bnxt_compressed_rx_cqe_mode_enabled(bp)) {\n+\t\t/* Don't worry if disabling TPA */\n+\t\tif (!enable)\n+\t\t\treturn 0;\n+\n+\t\t/* Return an error if enabling TPA w/ compressed Rx CQE. */\n+\t\tPMD_DRV_LOG(ERR, \"No HW support for LRO with compressed Rx\\n\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n \tif ((BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp)) && !bp->max_tpa_v2) {\n \t\tif (enable)\n \t\t\tPMD_DRV_LOG(ERR, \"No HW support for LRO\\n\");\ndiff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c\nindex 90cad6c9c6..4bf0b9c6ed 100644\n--- a/drivers/net/bnxt/bnxt_ring.c\n+++ b/drivers/net/bnxt/bnxt_ring.c\n@@ -573,6 +573,7 @@ static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index)\n \t\treturn rc;\n \n \trxr->ag_raw_prod = 0;\n+\trxr->ag_cons = 0;\n \tif (BNXT_HAS_RING_GRPS(bp))\n \t\tbp->grp_info[queue_index].ag_fw_ring_id = ring->fw_ring_id;\n \tbnxt_set_db(bp, &rxr->ag_db, ring_type, map_idx, ring->fw_ring_id,\n@@ -595,7 +596,17 @@ int bnxt_alloc_hwrm_rx_ring(struct bnxt *bp, int queue_index)\n \t * Storage for the cp ring is allocated based on worst-case\n \t * usage, the actual size to be used by hw is computed here.\n \t */\n-\tcp_ring->ring_size = rxr->rx_ring_struct->ring_size * 2;\n+\tif (bnxt_compressed_rx_cqe_mode_enabled(bp)) {\n+\t\tif (bnxt_need_agg_ring(bp->eth_dev))\n+\t\t\t/* Worst case scenario, needed to accommodate Rx flush\n+\t\t\t * completion during RING_FREE.\n+\t\t\t */\n+\t\t\tcp_ring->ring_size = rxr->rx_ring_struct->ring_size * 2;\n+\t\telse\n+\t\t\tcp_ring->ring_size = rxr->rx_ring_struct->ring_size;\n+\t} else {\n+\t\tcp_ring->ring_size = rxr->rx_ring_struct->ring_size * 2;\n+\t}\n \n \tif (bnxt_need_agg_ring(bp->eth_dev))\n \t\tcp_ring->ring_size *= AGG_RING_SIZE_FACTOR;\ndiff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c\nindex 59ea0121de..b919922a64 100644\n--- a/drivers/net/bnxt/bnxt_rxr.c\n+++ b/drivers/net/bnxt/bnxt_rxr.c\n@@ -907,6 +907,203 @@ void bnxt_set_mark_in_mbuf(struct bnxt *bp,\n \tmbuf->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;\n }\n \n+static void\n+bnxt_set_ol_flags_crx(struct bnxt_rx_ring_info *rxr,\n+\t\t struct rx_pkt_compress_cmpl *rxcmp,\n+\t\t struct rte_mbuf *mbuf)\n+{\n+\tuint16_t flags_type, errors, flags;\n+\tuint16_t cserr, tmp;\n+\tuint64_t ol_flags;\n+\n+\tflags_type = rte_le_to_cpu_16(rxcmp->flags_type);\n+\n+\tcserr = rte_le_to_cpu_16(rxcmp->metadata1_cs_error_calc_v1) &\n+\t\t(RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_MASK |\n+\t\t BNXT_RXC_METADATA1_VLAN_VALID);\n+\n+\tflags = cserr & BNXT_CRX_CQE_CSUM_CALC_MASK;\n+\ttmp = flags;\n+\n+\t/* Set tunnel frame indicator.\n+\t * This is to correctly index into the flags_err table.\n+\t */\n+\tflags |= (flags & BNXT_CRX_TUN_CS_CALC) ? BNXT_PKT_CMPL_T_IP_CS_CALC << 3 : 0;\n+\n+\tflags = flags >> BNXT_CRX_CQE_CSUM_CALC_SFT;\n+\n+\terrors = cserr & BNXT_CRX_CQE_CSUM_ERROR_MASK;\n+\terrors = (errors >> RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_SFT) & flags;\n+\n+\tol_flags = rxr->ol_flags_table[flags & ~errors];\n+\n+\tif (unlikely(errors)) {\n+\t\t/* Set tunnel frame indicator.\n+\t\t * This is to correctly index into the flags_err table.\n+\t\t */\n+\t\terrors |= (tmp & BNXT_CRX_TUN_CS_CALC) ? BNXT_PKT_CMPL_T_IP_CS_CALC << 2 : 0;\n+\t\tol_flags |= rxr->ol_flags_err_table[errors];\n+\t}\n+\n+\tif (flags_type & RX_PKT_COMPRESS_CMPL_FLAGS_RSS_VALID) {\n+\t\tmbuf->hash.rss = rte_le_to_cpu_32(rxcmp->rss_hash);\n+\t\tol_flags |= RTE_MBUF_F_RX_RSS_HASH;\n+\t}\n+\n+#ifdef RTE_LIBRTE_IEEE1588\n+\t/* TODO: TIMESTAMP flags need to be parsed and set. */\n+#endif\n+\n+\tmbuf->ol_flags = ol_flags;\n+}\n+\n+static uint32_t\n+bnxt_parse_pkt_type_crx(struct rx_pkt_compress_cmpl *rxcmp)\n+{\n+\tuint16_t flags_type, meta_cs;\n+\tuint8_t index;\n+\n+\tflags_type = rte_le_to_cpu_16(rxcmp->flags_type);\n+\tmeta_cs = rte_le_to_cpu_16(rxcmp->metadata1_cs_error_calc_v1);\n+\n+\t/* Validate ptype table indexing at build time. */\n+\t/* TODO */\n+\t/* bnxt_check_ptype_constants(); */\n+\n+\t/*\n+\t * Index format:\n+\t * bit 0: Set if IP tunnel encapsulated packet.\n+\t * bit 1: Set if IPv6 packet, clear if IPv4.\n+\t * bit 2: Set if VLAN tag present.\n+\t * bits 3-6: Four-bit hardware packet type field.\n+\t */\n+\tindex = BNXT_CMPL_ITYPE_TO_IDX(flags_type) |\n+\t\tBNXT_CMPL_VLAN_TUN_TO_IDX_CRX(meta_cs) |\n+\t\tBNXT_CMPL_IP_VER_TO_IDX(flags_type);\n+\n+\treturn bnxt_ptype_table[index];\n+}\n+\n+static int bnxt_rx_pages_crx(struct bnxt_rx_queue *rxq, struct rte_mbuf *mbuf,\n+\t\t\t uint32_t *tmp_raw_cons, uint8_t agg_buf)\n+{\n+\tstruct bnxt_cp_ring_info *cpr = rxq->cp_ring;\n+\tstruct bnxt_rx_ring_info *rxr = rxq->rx_ring;\n+\tint i;\n+\tuint16_t cp_cons, ag_cons;\n+\tstruct rx_pkt_compress_cmpl *rxcmp;\n+\tstruct rte_mbuf *last = mbuf;\n+\n+\tfor (i = 0; i < agg_buf; i++) {\n+\t\tstruct rte_mbuf **ag_buf;\n+\t\tstruct rte_mbuf *ag_mbuf;\n+\n+\t\t*tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons);\n+\t\tcp_cons = RING_CMP(cpr->cp_ring_struct, *tmp_raw_cons);\n+\t\trxcmp = (struct rx_pkt_compress_cmpl *)&cpr->cp_desc_ring[cp_cons];\n+\n+#ifdef BNXT_DEBUG\n+\t\tbnxt_dump_cmpl(cp_cons, rxcmp);\n+#endif\n+\n+\t\t/*\n+\t\t * The consumer index aka the opaque field for the agg buffers\n+\t\t * is not * available in errors_agg_bufs_opaque. So maintain it\n+\t\t * in driver itself.\n+\t\t */\n+\t\tag_cons = rxr->ag_cons;\n+\t\tag_buf = &rxr->ag_buf_ring[ag_cons];\n+\t\tag_mbuf = *ag_buf;\n+\n+\t\tag_mbuf->data_len = rte_le_to_cpu_16(rxcmp->len);\n+\n+\t\tmbuf->nb_segs++;\n+\t\tmbuf->pkt_len += ag_mbuf->data_len;\n+\n+\t\tlast->next = ag_mbuf;\n+\t\tlast = ag_mbuf;\n+\n+\t\t*ag_buf = NULL;\n+\t\t/*\n+\t\t * As aggregation buffer consumed out of order in TPA module,\n+\t\t * use bitmap to track freed slots to be allocated and notified\n+\t\t * to NIC. TODO: Is this needed. Most likely not.\n+\t\t */\n+\t\trte_bitmap_set(rxr->ag_bitmap, ag_cons);\n+\t\trxr->ag_cons = RING_IDX(rxr->ag_ring_struct, RING_NEXT(ag_cons));\n+\t}\n+\tlast->next = NULL;\n+\tbnxt_prod_ag_mbuf(rxq);\n+\treturn 0;\n+}\n+\n+static int bnxt_crx_pkt(struct rte_mbuf **rx_pkt,\n+\t\t\t\tstruct bnxt_rx_queue *rxq,\n+\t\t\t\tstruct rx_pkt_compress_cmpl *rxcmp,\n+\t\t\t\tuint32_t *raw_cons)\n+{\n+\tstruct bnxt_cp_ring_info *cpr = rxq->cp_ring;\n+\tstruct bnxt_rx_ring_info *rxr = rxq->rx_ring;\n+\tuint32_t tmp_raw_cons = *raw_cons;\n+\tuint16_t cons, raw_prod;\n+\tstruct rte_mbuf *mbuf;\n+\tint rc = 0;\n+\tuint8_t agg_buf = 0;\n+\n+\tagg_buf = BNXT_CRX_CQE_AGG_BUFS(rxcmp);\n+\t/*\n+\t * Since size of rx_pkt_cmpl is same as rx_pkt_compress_cmpl,\n+\t * we should be able to use bnxt_agg_bufs_valid to check if AGG\n+\t * bufs are valid when using compressed CQEs.\n+\t * All we want to check here is if the CQE is valid and the\n+\t * location of valid bit is same irrespective of the CQE type.\n+\t */\n+\tif (agg_buf && !bnxt_agg_bufs_valid(cpr, agg_buf, tmp_raw_cons))\n+\t\treturn -EBUSY;\n+\n+\traw_prod = rxr->rx_raw_prod;\n+\n+\tcons = rxcmp->errors_agg_bufs_opaque & BNXT_CRX_CQE_OPAQUE_MASK;\n+\tmbuf = bnxt_consume_rx_buf(rxr, cons);\n+\tif (mbuf == NULL)\n+\t\treturn -EBUSY;\n+\n+\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n+\tmbuf->nb_segs = 1;\n+\tmbuf->next = NULL;\n+\tmbuf->pkt_len = rxcmp->len;\n+\tmbuf->data_len = mbuf->pkt_len;\n+\tmbuf->port = rxq->port_id;\n+\n+#ifdef RTE_LIBRTE_IEEE1588\n+\t/* TODO: Add timestamp support. */\n+#endif\n+\n+\tbnxt_set_ol_flags_crx(rxr, rxcmp, mbuf);\n+\tmbuf->packet_type = bnxt_parse_pkt_type_crx(rxcmp);\n+\tbnxt_set_vlan_crx(rxcmp, mbuf);\n+\n+\tif (bnxt_alloc_rx_data(rxq, rxr, raw_prod)) {\n+\t\tPMD_DRV_LOG(ERR, \"mbuf alloc failed with prod=0x%x\\n\",\n+\t\t\t raw_prod);\n+\t\trc = -ENOMEM;\n+\t\tgoto rx;\n+\t}\n+\traw_prod = RING_NEXT(raw_prod);\n+\trxr->rx_raw_prod = raw_prod;\n+\n+\tif (agg_buf)\n+\t\tbnxt_rx_pages_crx(rxq, mbuf, &tmp_raw_cons, agg_buf);\n+\n+rx:\n+\trxr->rx_next_cons = RING_IDX(rxr->rx_ring_struct, RING_NEXT(cons));\n+\t*rx_pkt = mbuf;\n+\n+\t*raw_cons = tmp_raw_cons;\n+\n+\treturn rc;\n+}\n+\n static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,\n \t\t struct bnxt_rx_queue *rxq, uint32_t *raw_cons)\n {\n@@ -1148,6 +1345,10 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\tbreak;\n \t\tif (CMP_TYPE(rxcmp) == CMPL_BASE_TYPE_HWRM_DONE) {\n \t\t\tPMD_DRV_LOG(ERR, \"Rx flush done\\n\");\n+\t\t} else if (CMP_TYPE(rxcmp) == CMPL_BASE_TYPE_RX_L2_COMPRESS) {\n+\t\t\trc = bnxt_crx_pkt(&rx_pkts[nb_rx_pkts], rxq,\n+\t\t\t\t\t (struct rx_pkt_compress_cmpl *)rxcmp,\n+\t\t\t\t\t &raw_cons);\n \t\t} else if ((CMP_TYPE(rxcmp) >= CMPL_BASE_TYPE_RX_TPA_START_V2) &&\n \t\t\t (CMP_TYPE(rxcmp) <= CMPL_BASE_TYPE_RX_TPA_START_V3)) {\n \t\t\trc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);\ndiff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h\nindex 439d29a07f..c51bb2d62c 100644\n--- a/drivers/net/bnxt/bnxt_rxr.h\n+++ b/drivers/net/bnxt/bnxt_rxr.h\n@@ -52,6 +52,52 @@ static inline uint16_t bnxt_tpa_start_agg_id(struct bnxt *bp,\n #define BNXT_OL_FLAGS_TBL_DIM\t64\n #define BNXT_OL_FLAGS_ERR_TBL_DIM 32\n \n+#define BNXT_CRX_CQE_OPAQUE_MASK\t\t\\\n+\tRX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_MASK\n+#define BNXT_CRX_CQE_AGG_BUF_MASK\t\t\\\n+\tRX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_MASK\n+#define BNXT_CRX_CQE_AGG_BUF_SFT\t\t\\\n+\tRX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_SFT\n+#define BNXT_CRX_CQE_AGG_BUFS(cmp)\t\t\\\n+\t(((cmp)->errors_agg_bufs_opaque & BNXT_CRX_CQE_AGG_BUF_MASK) >> \\\n+\t BNXT_CRX_CQE_AGG_BUF_SFT)\n+#define BNXT_CRX_CQE_CSUM_CALC_MASK\t\t\\\n+\t(RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_CALC | \\\n+\t RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_CALC | \\\n+\t RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_CALC | \\\n+\t RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_CALC)\n+#define BNXT_CRX_CQE_CSUM_CALC_SFT\t8\n+#define BNXT_PKT_CMPL_T_IP_CS_CALC\t0x4\n+\n+#define BNXT_CRX_TUN_CS_CALC \\\n+\t(!!(RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_CALC | \\\n+\t RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_CALC))\n+\n+# define BNXT_CRX_CQE_CSUM_ERROR_MASK\t\t\\\n+\t(RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_ERROR | \\\n+\t RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_ERROR | \\\n+\t RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_ERROR | \\\n+\t RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_ERROR)\n+\n+/* meta_format != 0 and bit3 is valid, the value in meta is VLAN.\n+ * Use the bit as VLAN valid bit\n+ */\n+#define BNXT_RXC_METADATA1_VLAN_VALID\t\t\\\n+\tRX_PKT_COMPRESS_CMPL_METADATA1_VALID\n+\n+static inline void bnxt_set_vlan_crx(struct rx_pkt_compress_cmpl *rxcmp,\n+\t\t\t\t struct rte_mbuf *mbuf)\n+{\n+\tuint16_t metadata = rte_le_to_cpu_16(rxcmp->metadata1_cs_error_calc_v1);\n+\tuint16_t vlan_tci = rte_le_to_cpu_16(rxcmp->vlanc_tcid);\n+\n+\tif (metadata & RX_PKT_COMPRESS_CMPL_METADATA1_VALID)\n+\t\tmbuf->vlan_tci =\n+\t\t\tvlan_tci & (RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_MASK |\n+\t\t\t\t RX_PKT_COMPRESS_CMPL_VLANC_TCID_DE |\n+\t\t\t\t RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_MASK);\n+}\n+\n struct bnxt_tpa_info {\n \tstruct rte_mbuf\t\t\t*mbuf;\n \tuint16_t\t\t\tlen;\n@@ -70,6 +116,7 @@ struct bnxt_tpa_info {\n struct bnxt_rx_ring_info {\n \tuint16_t\t\trx_raw_prod;\n \tuint16_t\t\tag_raw_prod;\n+\tuint16_t\t\tag_cons; /* Needed with compressed CQE */\n \tuint16_t rx_cons; /* Needed for representor */\n \tuint16_t rx_next_cons;\n \tstruct bnxt_db_info rx_db;\n@@ -160,6 +207,10 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)\n #define CMPL_FLAGS2_VLAN_TUN_MSK \\\n \t(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN | RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)\n \n+#define CMPL_FLAGS2_VLAN_TUN_MSK_CRX \\\n+\t(RX_PKT_COMPRESS_CMPL_METADATA1_VALID | \\\n+\t RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_CALC)\n+\n #define BNXT_CMPL_ITYPE_TO_IDX(ft) \\\n \t(((ft) & RX_PKT_CMPL_FLAGS_ITYPE_MASK) >> \\\n \t (RX_PKT_CMPL_FLAGS_ITYPE_SFT - BNXT_PTYPE_TBL_TYPE_SFT))\n@@ -168,6 +219,10 @@ bnxt_cfa_code_dynfield(struct rte_mbuf *mbuf)\n \t(((f2) & CMPL_FLAGS2_VLAN_TUN_MSK) >> \\\n \t (RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT - BNXT_PTYPE_TBL_VLAN_SFT))\n \n+#define BNXT_CMPL_VLAN_TUN_TO_IDX_CRX(md) \\\n+\t(((md) & CMPL_FLAGS2_VLAN_TUN_MSK_CRX) >> \\\n+\t (RX_PKT_COMPRESS_CMPL_METADATA1_SFT - BNXT_PTYPE_TBL_VLAN_SFT))\n+\n #define BNXT_CMPL_IP_VER_TO_IDX(f2) \\\n \t(((f2) & RX_PKT_CMPL_FLAGS2_IP_TYPE) >> \\\n \t (RX_PKT_CMPL_FLAGS2_IP_TYPE_SFT - BNXT_PTYPE_TBL_IP_VER_SFT))\n", "prefixes": [ "02/18" ] }