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GET /api/patches/135036/?format=api
{ "id": 135036, "url": "http://patches.dpdk.org/api/patches/135036/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20231211171109.89716-10-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231211171109.89716-10-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231211171109.89716-10-ajit.khaparde@broadcom.com", "date": "2023-12-11T17:11:04", "name": "[v3,09/14] net/bnxt: add support for backing store v2", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "33f009a0bcb10a4f9be257ba657e67435bcefc4e", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "http://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20231211171109.89716-10-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 30511, "url": "http://patches.dpdk.org/api/series/30511/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=30511", "date": "2023-12-11T17:10:55", "name": "support new 5760X P7 devices", "version": 3, "mbox": "http://patches.dpdk.org/series/30511/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/135036/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/135036/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 885C6436C8;\n\tMon, 11 Dec 2023 18:12:34 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D3B5742DDD;\n\tMon, 11 Dec 2023 18:11:38 +0100 (CET)", "from mail-qk1-f169.google.com (mail-qk1-f169.google.com\n [209.85.222.169])\n by mails.dpdk.org (Postfix) with ESMTP id 44F1042DA3\n for <dev@dpdk.org>; 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c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1702314696; x=1702919496;\n h=mime-version:references:in-reply-to:message-id:date:subject:to:from\n :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to;\n bh=FL1grHKT+Xmx2EA/zQNDiok355sO1wixfqx0xp0u5C0=;\n b=C4XDyoG8ZUZGwn7BuoYPMDuK6cvFU+mahM7i355FGY0kO4Xn3v6cKWzJ4Falm1Ogwl\n WTxWoNuoC/XHl6p4FM4E14ZlVAy0NyJ3Zshy/ZS0fmdSZ0rXPWzh4pQQj9499b98rsrG\n W0oxwTRPfQhpQ94+V7FpNZo6aP3NcusAnD8tPfVRh0ccHIQ/izwVpbRpYf4Ia+rYzBr5\n JNTH3MEH4Dq7t2+KqZdGvkoVsnCOxGMP6z4p4E91XIKjwSrBk1vkKaN/vOo24abTF21u\n 4i4wyftROIoqfzVETRiDTqsPSiE9ChXzLiP8/SI6Pbv7gBXy2ol3da6bzZfo7gCx4OeN\n FCJw==", "X-Gm-Message-State": "AOJu0YzSAVCUkjVgTOGDQvDlQnpwbKcmwAZ+vLiCKIvkvCFVQYpC93a4\n GR0JHv0a5WBg3KDd15I5A1w3l7jN/0nplsdM2n46pJZsDbSobc+RaEgSJfuGuzjRSuWO4YW9pdc\n a4J1Ps/rUaHLdse4uG3mYz4a6hvRiCYQgUO1btW2ZSYbqTnBIlAGDwQ3Ro4BZNu2PguE+", "X-Google-Smtp-Source": "\n AGHT+IFUzC1dX8uoti9F9H3iCHFipWYaWAhYtxea26KPSCB5d0v7mWq4/0I3Nk2djpSzMEwOywbKsA==", "X-Received": "by 2002:ae9:c00a:0:b0:77b:aa20:8dd with SMTP id\n u10-20020ae9c00a000000b0077baa2008ddmr2987023qkk.8.1702314695776;\n Mon, 11 Dec 2023 09:11:35 -0800 (PST)", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Subject": "[PATCH v3 09/14] net/bnxt: add support for backing store v2", "Date": "Mon, 11 Dec 2023 09:11:04 -0800", "Message-Id": "<20231211171109.89716-10-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.39.2 (Apple Git-143)", "In-Reply-To": "<20231211171109.89716-1-ajit.khaparde@broadcom.com>", "References": "<20231211171109.89716-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "multipart/signed; protocol=\"application/pkcs7-signature\";\n micalg=sha-256; boundary=\"000000000000c9ae42060c3f066f\"", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add backing store v2 changes.\nThe firmware supports the new backing store scheme for P7\nand newer devices.\n\nTo support this, the driver queries the different types of chip\ncontexts the firmware supports and allocates the appropriate size\nof memory for the firmware and hardware to use.\nThe code then goes ahead and frees up the memory during cleanup.\n\nOlder P5 device family continues to support the version 1 of\nbacking store. While the P4 device family does not need any\nbacking store memory.\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h | 69 ++++++-\n drivers/net/bnxt/bnxt_ethdev.c | 177 ++++++++++++++++--\n drivers/net/bnxt/bnxt_hwrm.c | 319 +++++++++++++++++++++++++++++++--\n drivers/net/bnxt/bnxt_hwrm.h | 8 +\n drivers/net/bnxt/bnxt_util.c | 10 ++\n drivers/net/bnxt/bnxt_util.h | 1 +\n 6 files changed, 545 insertions(+), 39 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex 3fbdf1ddcc..68c4778dc3 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -81,6 +81,11 @@\n #define BROADCOM_DEV_957508_N2100\t0x5208\n #define BROADCOM_DEV_957414_N225\t0x4145\n \n+#define HWRM_SPEC_CODE_1_8_3\t\t0x10803\n+#define HWRM_VERSION_1_9_1\t\t0x10901\n+#define HWRM_VERSION_1_9_2\t\t0x10903\n+#define HWRM_VERSION_1_10_2_13\t\t0x10a020d\n+\n #define BNXT_MAX_MTU\t\t9574\n #define BNXT_NUM_VLANS\t\t2\n #define BNXT_MAX_PKT_LEN\t(BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\\\n@@ -430,16 +435,26 @@ struct bnxt_coal {\n #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)\n #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)\n \n+#define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)\n+\n #define PTU_PTE_VALID 0x1UL\n #define PTU_PTE_LAST 0x2UL\n #define PTU_PTE_NEXT_TO_LAST 0x4UL\n \n+#define BNXT_CTX_MIN\t\t1\n+#define BNXT_CTX_INV\t\t0xffff\n+\n+#define BNXT_CTX_INIT_VALID(flags)\t\\\n+\t((flags) &\t\t\t\\\n+\t HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT)\n+\n struct bnxt_ring_mem_info {\n \tint\t\t\t\tnr_pages;\n \tint\t\t\t\tpage_size;\n \tuint32_t\t\t\tflags;\n #define BNXT_RMEM_VALID_PTE_FLAG\t1\n #define BNXT_RMEM_RING_PTE_FLAG\t\t2\n+#define BNXT_RMEM_USE_FULL_PAGE_FLAG\t4\n \n \tvoid\t\t\t\t**pg_arr;\n \trte_iova_t\t\t\t*dma_arr;\n@@ -460,7 +475,50 @@ struct bnxt_ctx_pg_info {\n \tstruct bnxt_ring_mem_info ring_mem;\n };\n \n+struct bnxt_ctx_mem {\n+\tuint16_t\ttype;\n+\tuint16_t\tentry_size;\n+\tuint32_t\tflags;\n+#define BNXT_CTX_MEM_TYPE_VALID \\\n+\tHWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID\n+\tuint32_t\tinstance_bmap;\n+\tuint8_t\t\tinit_value;\n+\tuint8_t\t\tentry_multiple;\n+\tuint16_t\tinit_offset;\n+#define\tBNXT_CTX_INIT_INVALID_OFFSET\t0xffff\n+\tuint32_t\tmax_entries;\n+\tuint32_t\tmin_entries;\n+\tuint8_t\t\tlast:1;\n+\tuint8_t\t\tsplit_entry_cnt;\n+#define BNXT_MAX_SPLIT_ENTRY\t4\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint32_t\tqp_l2_entries;\n+\t\t\tuint32_t\tqp_qp1_entries;\n+\t\t\tuint32_t\tqp_fast_qpmd_entries;\n+\t\t};\n+\t\tuint32_t\tsrq_l2_entries;\n+\t\tuint32_t\tcq_l2_entries;\n+\t\tuint32_t\tvnic_entries;\n+\t\tstruct {\n+\t\t\tuint32_t\tmrav_av_entries;\n+\t\t\tuint32_t\tmrav_num_entries_units;\n+\t\t};\n+\t\tuint32_t\tsplit[BNXT_MAX_SPLIT_ENTRY];\n+\t};\n+\tstruct bnxt_ctx_pg_info\t*pg_info;\n+};\n+\n+#define BNXT_CTX_FLAG_INITED 0x01\n+\n struct bnxt_ctx_mem_info {\n+\tstruct bnxt_ctx_mem\t*ctx_arr;\n+\tuint32_t\tsupported_types;\n+\tuint32_t\tflags;\n+\tuint16_t\ttypes;\n+\tuint8_t\t\ttqm_fp_rings_count;\n+\n+\t/* The following are used for V1 */\n \tuint32_t qp_max_entries;\n \tuint16_t qp_min_qp1_entries;\n \tuint16_t qp_max_l2_entries;\n@@ -484,10 +542,6 @@ struct bnxt_ctx_mem_info {\n \tuint16_t tim_entry_size;\n \tuint32_t tim_max_entries;\n \tuint8_t tqm_entries_multiple;\n-\tuint8_t tqm_fp_rings_count;\n-\n-\tuint32_t flags;\n-#define BNXT_CTX_FLAG_INITED 0x01\n \n \tstruct bnxt_ctx_pg_info qp_mem;\n \tstruct bnxt_ctx_pg_info srq_mem;\n@@ -739,6 +793,13 @@ struct bnxt {\n #define BNXT_FW_CAP_TRUFLOW_EN\t\tBIT(8)\n #define BNXT_FW_CAP_VLAN_TX_INSERT\tBIT(9)\n #define BNXT_FW_CAP_RX_ALL_PKT_TS\tBIT(10)\n+#define BNXT_FW_CAP_BACKING_STORE_V2\tBIT(12)\n+#define BNXT_FW_BACKING_STORE_V2_EN(bp)\t\\\n+\t((bp)->fw_cap & BNXT_FW_CAP_BACKING_STORE_V2)\n+#define BNXT_FW_BACKING_STORE_V1_EN(bp)\t\\\n+\t(BNXT_CHIP_P5_P7((bp)) && \\\n+\t (bp)->hwrm_spec_code >= HWRM_VERSION_1_9_2 && \\\n+\t !BNXT_VF((bp)))\n #define BNXT_TRUFLOW_EN(bp)\t((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN &&\\\n \t\t\t\t (bp)->app_id != 0xFF)\n \ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex 95f9dd1aa1..004b2df4f4 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -4759,8 +4759,26 @@ static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)\n \treturn 0;\n }\n \n+static void bnxt_init_ctxm_mem(struct bnxt_ctx_mem *ctxm, void *p, int len)\n+{\n+\tuint8_t init_val = ctxm->init_value;\n+\tuint16_t offset = ctxm->init_offset;\n+\tuint8_t *p2 = p;\n+\tint i;\n+\n+\tif (!init_val)\n+\t\treturn;\n+\tif (offset == BNXT_CTX_INIT_INVALID_OFFSET) {\n+\t\tmemset(p, init_val, len);\n+\t\treturn;\n+\t}\n+\tfor (i = 0; i < len; i += ctxm->entry_size)\n+\t\t*(p2 + i + offset) = init_val;\n+}\n+\n static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,\n \t\t\t\t struct bnxt_ctx_pg_info *ctx_pg,\n+\t\t\t\t struct bnxt_ctx_mem *ctxm,\n \t\t\t\t uint32_t mem_size,\n \t\t\t\t const char *suffix,\n \t\t\t\t uint16_t idx)\n@@ -4776,8 +4794,8 @@ static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,\n \tif (!mem_size)\n \t\treturn 0;\n \n-\trmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /\n-\t\t\t BNXT_PAGE_SIZE;\n+\trmem->nr_pages =\n+\t\tRTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / BNXT_PAGE_SIZE;\n \trmem->page_size = BNXT_PAGE_SIZE;\n \n \tsnprintf(name, RTE_MEMZONE_NAMESIZE, \"bnxt_ctx_pg_arr%s_%x_%d\",\n@@ -4794,13 +4812,13 @@ static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,\n \n \trmem->pg_arr = ctx_pg->ctx_pg_arr;\n \trmem->dma_arr = ctx_pg->ctx_dma_arr;\n-\trmem->flags = BNXT_RMEM_VALID_PTE_FLAG;\n+\trmem->flags = BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_USE_FULL_PAGE_FLAG;\n \n \tvalid_bits = PTU_PTE_VALID;\n \n \tif (rmem->nr_pages > 1) {\n \t\tsnprintf(name, RTE_MEMZONE_NAMESIZE,\n-\t\t\t \"bnxt_ctx_pg_tbl%s_%x_%d\",\n+\t\t\t \"bnxt_ctxpgtbl%s_%x_%d\",\n \t\t\t suffix, idx, bp->eth_dev->data->port_id);\n \t\tname[RTE_MEMZONE_NAMESIZE - 1] = 0;\n \t\tmz = rte_memzone_lookup(name);\n@@ -4816,9 +4834,11 @@ static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,\n \t\t\t\treturn -ENOMEM;\n \t\t}\n \n-\t\tmemset(mz->addr, 0, mz->len);\n+\t\tmemset(mz->addr, 0xff, mz->len);\n \t\tmz_phys_addr = mz->iova;\n \n+\t\tif (ctxm != NULL)\n+\t\t\tbnxt_init_ctxm_mem(ctxm, mz->addr, mz->len);\n \t\trmem->pg_tbl = mz->addr;\n \t\trmem->pg_tbl_map = mz_phys_addr;\n \t\trmem->pg_tbl_mz = mz;\n@@ -4839,9 +4859,11 @@ static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,\n \t\t\treturn -ENOMEM;\n \t}\n \n-\tmemset(mz->addr, 0, mz->len);\n+\tmemset(mz->addr, 0xff, mz->len);\n \tmz_phys_addr = mz->iova;\n \n+\tif (ctxm != NULL)\n+\t\tbnxt_init_ctxm_mem(ctxm, mz->addr, mz->len);\n \tfor (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {\n \t\trmem->pg_arr[i] = ((char *)mz->addr) + sz;\n \t\trmem->dma_arr[i] = mz_phys_addr + sz;\n@@ -4866,6 +4888,34 @@ static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,\n \treturn 0;\n }\n \n+static void bnxt_free_ctx_mem_v2(struct bnxt *bp)\n+{\n+\tuint16_t type;\n+\n+\tfor (type = 0; type < bp->ctx->types; type++) {\n+\t\tstruct bnxt_ctx_mem *ctxm = &bp->ctx->ctx_arr[type];\n+\t\tstruct bnxt_ctx_pg_info *ctx_pg = ctxm->pg_info;\n+\t\tint i, n = 1;\n+\n+\t\tif (!ctx_pg)\n+\t\t\tcontinue;\n+\t\tif (ctxm->instance_bmap)\n+\t\t\tn = hweight32(ctxm->instance_bmap);\n+\n+\t\tfor (i = 0; i < n; i++) {\n+\t\t\trte_free(ctx_pg[i].ctx_pg_arr);\n+\t\t\trte_free(ctx_pg[i].ctx_dma_arr);\n+\t\t\trte_memzone_free(ctx_pg[i].ring_mem.mz);\n+\t\t\trte_memzone_free(ctx_pg[i].ring_mem.pg_tbl_mz);\n+\t\t}\n+\n+\t\trte_free(ctx_pg);\n+\t\tctxm->pg_info = NULL;\n+\t}\n+\trte_free(bp->ctx->ctx_arr);\n+\tbp->ctx->ctx_arr = NULL;\n+}\n+\n static void bnxt_free_ctx_mem(struct bnxt *bp)\n {\n \tint i;\n@@ -4874,6 +4924,12 @@ static void bnxt_free_ctx_mem(struct bnxt *bp)\n \t\treturn;\n \n \tbp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;\n+\n+\tif (BNXT_FW_BACKING_STORE_V2_EN(bp)) {\n+\t\tbnxt_free_ctx_mem_v2(bp);\n+\t\tgoto free_ctx;\n+\t}\n+\n \trte_free(bp->ctx->qp_mem.ctx_pg_arr);\n \trte_free(bp->ctx->srq_mem.ctx_pg_arr);\n \trte_free(bp->ctx->cq_mem.ctx_pg_arr);\n@@ -4903,6 +4959,7 @@ static void bnxt_free_ctx_mem(struct bnxt *bp)\n \t\t\trte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);\n \t}\n \n+free_ctx:\n \trte_free(bp->ctx);\n \tbp->ctx = NULL;\n }\n@@ -4921,28 +4978,113 @@ static void bnxt_free_ctx_mem(struct bnxt *bp)\n \n #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)\n \n+int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp)\n+{\n+\tstruct bnxt_ctx_mem_info *ctx = bp->ctx;\n+\tstruct bnxt_ctx_mem *ctx2;\n+\tuint16_t type;\n+\tint rc = 0;\n+\n+\tctx2 = &ctx->ctx_arr[0];\n+\tfor (type = 0; type < ctx->types && rc == 0; type++) {\n+\t\tstruct bnxt_ctx_mem *ctxm = &ctx->ctx_arr[type];\n+\t\tstruct bnxt_ctx_pg_info *ctx_pg;\n+\t\tuint32_t entries, mem_size;\n+\t\tint w = 1;\n+\t\tint i;\n+\n+\t\tif (ctxm->entry_size == 0)\n+\t\t\tcontinue;\n+\n+\t\tctx_pg = ctxm->pg_info;\n+\n+\t\tif (ctxm->instance_bmap)\n+\t\t\tw = hweight32(ctxm->instance_bmap);\n+\n+\t\tfor (i = 0; i < w && rc == 0; i++) {\n+\t\t\tchar name[RTE_MEMZONE_NAMESIZE] = {0};\n+\n+\t\t\tsprintf(name, \"_%d_%d\", i, type);\n+\n+\t\t\tif (ctxm->entry_multiple)\n+\t\t\t\tentries = bnxt_roundup(ctxm->max_entries,\n+\t\t\t\t\t\t ctxm->entry_multiple);\n+\t\t\telse\n+\t\t\t\tentries = ctxm->max_entries;\n+\n+\t\t\tif (ctxm->type == HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ)\n+\t\t\t\tentries = ctxm->cq_l2_entries;\n+\t\t\telse if (ctxm->type == HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP)\n+\t\t\t\tentries = ctxm->qp_l2_entries;\n+\t\t\telse if (ctxm->type == HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV)\n+\t\t\t\tentries = ctxm->mrav_av_entries;\n+\t\t\telse if (ctxm->type == HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM)\n+\t\t\t\tentries = ctx2->qp_l2_entries;\n+\t\t\tentries = clamp_t(uint32_t, entries, ctxm->min_entries,\n+\t\t\t\t\t ctxm->max_entries);\n+\t\t\tctx_pg[i].entries = entries;\n+\t\t\tmem_size = ctxm->entry_size * entries;\n+\t\t\tPMD_DRV_LOG(DEBUG,\n+\t\t\t\t \"Type:0x%x instance:%d entries:%d size:%d\\n\",\n+\t\t\t\t ctxm->type, i, ctx_pg[i].entries, mem_size);\n+\t\t\trc = bnxt_alloc_ctx_mem_blk(bp, &ctx_pg[i],\n+\t\t\t\t\t\t ctxm->init_value ? ctxm : NULL,\n+\t\t\t\t\t\t mem_size, name, i);\n+\t\t}\n+\t}\n+\n+\treturn rc;\n+}\n+\n int bnxt_alloc_ctx_mem(struct bnxt *bp)\n {\n \tstruct bnxt_ctx_pg_info *ctx_pg;\n \tstruct bnxt_ctx_mem_info *ctx;\n \tuint32_t mem_size, ena, entries;\n+\tint types = BNXT_CTX_MIN;\n \tuint32_t entries_sp, min;\n-\tint i, rc;\n+\tint i, rc = 0;\n+\n+\tif (!BNXT_FW_BACKING_STORE_V1_EN(bp) &&\n+\t !BNXT_FW_BACKING_STORE_V2_EN(bp))\n+\t\treturn rc;\n+\n+\tif (BNXT_FW_BACKING_STORE_V2_EN(bp)) {\n+\t\ttypes = bnxt_hwrm_func_backing_store_types_count(bp);\n+\t\tif (types <= 0)\n+\t\t\treturn types;\n+\t}\n+\n+\trc = bnxt_hwrm_func_backing_store_ctx_alloc(bp, types);\n+\tif (rc != 0)\n+\t\treturn rc;\n+\n+\tif (bp->ctx->flags & BNXT_CTX_FLAG_INITED)\n+\t\treturn 0;\n+\n+\tctx = bp->ctx;\n+\tif (BNXT_FW_BACKING_STORE_V2_EN(bp)) {\n+\t\trc = bnxt_hwrm_func_backing_store_qcaps_v2(bp);\n+\n+\t\tfor (i = 0 ; i < bp->ctx->types && rc == 0; i++) {\n+\t\t\tstruct bnxt_ctx_mem *ctxm = &ctx->ctx_arr[i];\n+\n+\t\t\trc = bnxt_hwrm_func_backing_store_cfg_v2(bp, ctxm);\n+\t\t}\n+\t\tgoto done;\n+\t}\n \n \trc = bnxt_hwrm_func_backing_store_qcaps(bp);\n \tif (rc) {\n \t\tPMD_DRV_LOG(ERR, \"Query context mem capability failed\\n\");\n \t\treturn rc;\n \t}\n-\tctx = bp->ctx;\n-\tif (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))\n-\t\treturn 0;\n \n \tctx_pg = &ctx->qp_mem;\n \tctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;\n \tif (ctx->qp_entry_size) {\n \t\tmem_size = ctx->qp_entry_size * ctx_pg->entries;\n-\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, \"qp_mem\", 0);\n+\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, NULL, mem_size, \"qp_mem\", 0);\n \t\tif (rc)\n \t\t\treturn rc;\n \t}\n@@ -4951,7 +5093,7 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)\n \tctx_pg->entries = ctx->srq_max_l2_entries;\n \tif (ctx->srq_entry_size) {\n \t\tmem_size = ctx->srq_entry_size * ctx_pg->entries;\n-\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, \"srq_mem\", 0);\n+\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, NULL, mem_size, \"srq_mem\", 0);\n \t\tif (rc)\n \t\t\treturn rc;\n \t}\n@@ -4960,7 +5102,7 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)\n \tctx_pg->entries = ctx->cq_max_l2_entries;\n \tif (ctx->cq_entry_size) {\n \t\tmem_size = ctx->cq_entry_size * ctx_pg->entries;\n-\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, \"cq_mem\", 0);\n+\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, NULL, mem_size, \"cq_mem\", 0);\n \t\tif (rc)\n \t\t\treturn rc;\n \t}\n@@ -4970,7 +5112,7 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)\n \t\tctx->vnic_max_ring_table_entries;\n \tif (ctx->vnic_entry_size) {\n \t\tmem_size = ctx->vnic_entry_size * ctx_pg->entries;\n-\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, \"vnic_mem\", 0);\n+\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, NULL, mem_size, \"vnic_mem\", 0);\n \t\tif (rc)\n \t\t\treturn rc;\n \t}\n@@ -4979,7 +5121,7 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)\n \tctx_pg->entries = ctx->stat_max_entries;\n \tif (ctx->stat_entry_size) {\n \t\tmem_size = ctx->stat_entry_size * ctx_pg->entries;\n-\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, \"stat_mem\", 0);\n+\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, NULL, mem_size, \"stat_mem\", 0);\n \t\tif (rc)\n \t\t\treturn rc;\n \t}\n@@ -5003,8 +5145,8 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)\n \t\tctx_pg->entries = i ? entries : entries_sp;\n \t\tif (ctx->tqm_entry_size) {\n \t\t\tmem_size = ctx->tqm_entry_size * ctx_pg->entries;\n-\t\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,\n-\t\t\t\t\t\t \"tqm_mem\", i);\n+\t\t\trc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, NULL,\n+\t\t\t\t\t\t mem_size, \"tqm_mem\", i);\n \t\t\tif (rc)\n \t\t\t\treturn rc;\n \t\t}\n@@ -5016,6 +5158,7 @@ int bnxt_alloc_ctx_mem(struct bnxt *bp)\n \n \tena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;\n \trc = bnxt_hwrm_func_backing_store_cfg(bp, ena);\n+done:\n \tif (rc)\n \t\tPMD_DRV_LOG(ERR,\n \t\t\t \"Failed to configure context mem: rc = %d\\n\", rc);\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 2d0a7a2731..a2182af036 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -24,10 +24,6 @@\n #include \"bnxt_vnic.h\"\n #include \"hsi_struct_def_dpdk.h\"\n \n-#define HWRM_SPEC_CODE_1_8_3\t\t0x10803\n-#define HWRM_VERSION_1_9_1\t\t0x10901\n-#define HWRM_VERSION_1_9_2\t\t0x10903\n-#define HWRM_VERSION_1_10_2_13\t\t0x10a020d\n struct bnxt_plcmodes_cfg {\n \tuint32_t\tflags;\n \tuint16_t\tjumbo_thresh;\n@@ -35,6 +31,43 @@ struct bnxt_plcmodes_cfg {\n \tuint16_t\thds_threshold;\n };\n \n+const char *bnxt_backing_store_types[] = {\n+\t\"Queue pair\",\n+\t\"Shared receive queue\",\n+\t\"Completion queue\",\n+\t\"Virtual NIC\",\n+\t\"Statistic context\",\n+\t\"Slow-path TQM ring\",\n+\t\"Fast-path TQM ring\",\n+\t\"Unused\",\n+\t\"Unused\",\n+\t\"Unused\",\n+\t\"Unused\",\n+\t\"Unused\",\n+\t\"Unused\",\n+\t\"Unused\",\n+\t\"MR and MAV Context\",\n+\t\"TIM\",\n+\t\"Unused\",\n+\t\"Unused\",\n+\t\"Unused\",\n+\t\"Tx key context\",\n+\t\"Rx key context\",\n+\t\"Mid-path TQM ring\",\n+\t\"SQ Doorbell shadow region\",\n+\t\"RQ Doorbell shadow region\",\n+\t\"SRQ Doorbell shadow region\",\n+\t\"CQ Doorbell shadow region\",\n+\t\"QUIC Tx key context\",\n+\t\"QUIC Rx key context\",\n+\t\"Invalid type\",\n+\t\"Invalid type\",\n+\t\"Invalid type\",\n+\t\"Invalid type\",\n+\t\"Invalid type\",\n+\t\"Invalid type\"\n+};\n+\n static int page_getenum(size_t size)\n {\n \tif (size <= 1 << 4)\n@@ -894,6 +927,11 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)\n \tif (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)\n \t\tbp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;\n \n+\tif (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED) {\n+\t\tPMD_DRV_LOG(DEBUG, \"Backing store v2 supported\\n\");\n+\t\tif (BNXT_CHIP_P7(bp))\n+\t\t\tbp->fw_cap |= BNXT_FW_CAP_BACKING_STORE_V2;\n+\t}\n \tif (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {\n \t\tbp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;\n \t\tPMD_DRV_LOG(DEBUG, \"VLAN acceleration for TX is enabled\\n\");\n@@ -5461,7 +5499,194 @@ int bnxt_hwrm_set_ring_coal(struct bnxt *bp,\n \treturn 0;\n }\n \n-#define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)\n+static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem *ctxm,\n+\t\t\t\t uint8_t init_val,\n+\t\t\t\t uint8_t init_offset,\n+\t\t\t\t bool init_mask_set)\n+{\n+\tctxm->init_value = init_val;\n+\tctxm->init_offset = BNXT_CTX_INIT_INVALID_OFFSET;\n+\tif (init_mask_set)\n+\t\tctxm->init_offset = init_offset * 4;\n+\telse\n+\t\tctxm->init_value = 0;\n+}\n+\n+static int bnxt_alloc_all_ctx_pg_info(struct bnxt *bp)\n+{\n+\tstruct bnxt_ctx_mem_info *ctx = bp->ctx;\n+\tchar name[RTE_MEMZONE_NAMESIZE];\n+\tuint16_t type;\n+\n+\tfor (type = 0; type < ctx->types; type++) {\n+\t\tstruct bnxt_ctx_mem *ctxm = &ctx->ctx_arr[type];\n+\t\tint n = 1;\n+\n+\t\tif (!ctxm->max_entries || ctxm->pg_info)\n+\t\t\tcontinue;\n+\n+\t\tif (ctxm->instance_bmap)\n+\t\t\tn = hweight32(ctxm->instance_bmap);\n+\n+\t\tsprintf(name, \"bnxt_ctx_pgmem_%d_%d\",\n+\t\t\tbp->eth_dev->data->port_id, type);\n+\t\tctxm->pg_info = rte_malloc(name, sizeof(*ctxm->pg_info) * n,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\t\tif (!ctxm->pg_info)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\treturn 0;\n+}\n+\n+static void bnxt_init_ctx_v2_driver_managed(struct bnxt *bp __rte_unused,\n+\t\t\t\t\t struct bnxt_ctx_mem *ctxm)\n+{\n+\tswitch (ctxm->type) {\n+\tcase HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW:\n+\tcase HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW:\n+\tcase HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW:\n+\tcase HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW:\n+\t\t/* FALLTHROUGH */\n+\t\tctxm->entry_size = 0;\n+\t\tctxm->min_entries = 1;\n+\t\tctxm->max_entries = 1;\n+\t\tbreak;\n+\t}\n+}\n+\n+int bnxt_hwrm_func_backing_store_qcaps_v2(struct bnxt *bp)\n+{\n+\tstruct hwrm_func_backing_store_qcaps_v2_input req = {0};\n+\tstruct hwrm_func_backing_store_qcaps_v2_output *resp =\n+\t\tbp->hwrm_cmd_resp_addr;\n+\tstruct bnxt_ctx_mem_info *ctx = bp->ctx;\n+\tuint16_t last_valid_type = BNXT_CTX_INV;\n+\tuint16_t last_valid_idx = 0;\n+\tuint16_t types, type;\n+\tint rc;\n+\n+\tfor (types = 0, type = 0; types < bp->ctx->types && type != BNXT_CTX_INV; types++) {\n+\t\tstruct bnxt_ctx_mem *ctxm = &bp->ctx->ctx_arr[types];\n+\t\tuint8_t init_val, init_off, i;\n+\t\tuint32_t *p;\n+\t\tuint32_t flags;\n+\n+\t\tHWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS_V2, BNXT_USE_CHIMP_MB);\n+\t\treq.type = rte_cpu_to_le_16(type);\n+\t\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n+\t\tHWRM_CHECK_RESULT();\n+\n+\t\tflags = rte_le_to_cpu_32(resp->flags);\n+\t\ttype = rte_le_to_cpu_16(resp->next_valid_type);\n+\t\tif (!(flags & HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID))\n+\t\t\tgoto next;\n+\n+\t\tctxm->type = rte_le_to_cpu_16(resp->type);\n+\n+\t\tctxm->flags = flags;\n+\t\tif (flags &\n+\t\t HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY) {\n+\t\t\tbnxt_init_ctx_v2_driver_managed(bp, ctxm);\n+\t\t\tgoto next;\n+\t\t}\n+\t\tctxm->entry_size = rte_le_to_cpu_16(resp->entry_size);\n+\n+\t\tif (ctxm->entry_size == 0)\n+\t\t\tgoto next;\n+\n+\t\tctxm->instance_bmap = rte_le_to_cpu_32(resp->instance_bit_map);\n+\t\tctxm->entry_multiple = resp->entry_multiple;\n+\t\tctxm->max_entries = rte_le_to_cpu_32(resp->max_num_entries);\n+\t\tctxm->min_entries = rte_le_to_cpu_32(resp->min_num_entries);\n+\t\tinit_val = resp->ctx_init_value;\n+\t\tinit_off = resp->ctx_init_offset;\n+\t\tbnxt_init_ctx_initializer(ctxm, init_val, init_off,\n+\t\t\t\t\t BNXT_CTX_INIT_VALID(flags));\n+\t\tctxm->split_entry_cnt = RTE_MIN(resp->subtype_valid_cnt,\n+\t\t\t\t\t\tBNXT_MAX_SPLIT_ENTRY);\n+\t\tfor (i = 0, p = &resp->split_entry_0; i < ctxm->split_entry_cnt;\n+\t\t i++, p++)\n+\t\t\tctxm->split[i] = rte_le_to_cpu_32(*p);\n+\n+\t\tPMD_DRV_LOG(DEBUG,\n+\t\t\t \"type:%s size:%d multiple:%d max:%d min:%d split:%d init_val:%d init_off:%d init:%d bmap:0x%x\\n\",\n+\t\t\t bnxt_backing_store_types[ctxm->type], ctxm->entry_size,\n+\t\t\t ctxm->entry_multiple, ctxm->max_entries, ctxm->min_entries,\n+\t\t\t ctxm->split_entry_cnt, init_val, init_off,\n+\t\t\t BNXT_CTX_INIT_VALID(flags), ctxm->instance_bmap);\n+\t\tlast_valid_type = ctxm->type;\n+\t\tlast_valid_idx = types;\n+next:\n+\t\tHWRM_UNLOCK();\n+\t}\n+\tctx->ctx_arr[last_valid_idx].last = true;\n+\tPMD_DRV_LOG(DEBUG, \"Last valid type 0x%x\\n\", last_valid_type);\n+\n+\trc = bnxt_alloc_all_ctx_pg_info(bp);\n+\tif (rc == 0)\n+\t\trc = bnxt_alloc_ctx_pg_tbls(bp);\n+\treturn rc;\n+}\n+\n+int bnxt_hwrm_func_backing_store_types_count(struct bnxt *bp)\n+{\n+\tstruct hwrm_func_backing_store_qcaps_v2_input req = {0};\n+\tstruct hwrm_func_backing_store_qcaps_v2_output *resp =\n+\t\tbp->hwrm_cmd_resp_addr;\n+\tuint16_t type = 0;\n+\tint types = 0;\n+\tint rc;\n+\n+\t/* Calculate number of valid context types */\n+\tdo {\n+\t\tuint32_t flags;\n+\n+\t\tHWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS_V2, BNXT_USE_CHIMP_MB);\n+\t\treq.type = rte_cpu_to_le_16(type);\n+\t\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n+\t\tHWRM_CHECK_RESULT();\n+\n+\t\tflags = rte_le_to_cpu_32(resp->flags);\n+\t\ttype = rte_le_to_cpu_16(resp->next_valid_type);\n+\t\tHWRM_UNLOCK();\n+\n+\t\tif (flags & HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Valid types 0x%x - %s\\n\",\n+\t\t\t\t req.type, bnxt_backing_store_types[req.type]);\n+\t\t\ttypes++;\n+\t\t}\n+\t} while (type != HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID);\n+\tPMD_DRV_LOG(DEBUG, \"Number of valid types %d\\n\", types);\n+\n+\treturn types;\n+}\n+\n+int bnxt_hwrm_func_backing_store_ctx_alloc(struct bnxt *bp, uint16_t types)\n+{\n+\tint alloc_len = sizeof(struct bnxt_ctx_mem_info);\n+\n+\tif (!BNXT_CHIP_P5_P7(bp) ||\n+\t bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||\n+\t BNXT_VF(bp) ||\n+\t bp->ctx)\n+\t\treturn 0;\n+\n+\tbp->ctx = rte_zmalloc(\"bnxt_ctx_mem\", alloc_len,\n+\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (bp->ctx == NULL)\n+\t\treturn -ENOMEM;\n+\n+\talloc_len = sizeof(struct bnxt_ctx_mem) * types;\n+\tbp->ctx->ctx_arr = rte_zmalloc(\"bnxt_ctx_mem_arr\",\n+\t\t\t\t alloc_len,\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (bp->ctx->ctx_arr == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tbp->ctx->types = types;\n+\treturn 0;\n+}\n+\n int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)\n {\n \tstruct hwrm_func_backing_store_qcaps_input req = {0};\n@@ -5469,27 +5694,19 @@ int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)\n \t\tbp->hwrm_cmd_resp_addr;\n \tstruct bnxt_ctx_pg_info *ctx_pg;\n \tstruct bnxt_ctx_mem_info *ctx;\n-\tint total_alloc_len;\n \tint rc, i, tqm_rings;\n \n \tif (!BNXT_CHIP_P5_P7(bp) ||\n \t bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||\n \t BNXT_VF(bp) ||\n-\t bp->ctx)\n+\t bp->ctx->flags & BNXT_CTX_FLAG_INITED)\n \t\treturn 0;\n \n+\tctx = bp->ctx;\n \tHWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);\n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \tHWRM_CHECK_RESULT_SILENT();\n \n-\ttotal_alloc_len = sizeof(*ctx);\n-\tctx = rte_zmalloc(\"bnxt_ctx_mem\", total_alloc_len,\n-\t\t\t RTE_CACHE_LINE_SIZE);\n-\tif (!ctx) {\n-\t\trc = -ENOMEM;\n-\t\tgoto ctx_err;\n-\t}\n-\n \tctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);\n \tctx->qp_min_qp1_entries =\n \t\trte_le_to_cpu_16(resp->qp_min_qp1_entries);\n@@ -5500,8 +5717,13 @@ int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)\n \t\trte_le_to_cpu_16(resp->srq_max_l2_entries);\n \tctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);\n \tctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);\n-\tctx->cq_max_l2_entries =\n-\t\trte_le_to_cpu_16(resp->cq_max_l2_entries);\n+\tif (BNXT_CHIP_P7(bp))\n+\t\tctx->cq_max_l2_entries =\n+\t\t\tRTE_MIN(BNXT_P7_CQ_MAX_L2_ENT,\n+\t\t\t\trte_le_to_cpu_16(resp->cq_max_l2_entries));\n+\telse\n+\t\tctx->cq_max_l2_entries =\n+\t\t\trte_le_to_cpu_16(resp->cq_max_l2_entries);\n \tctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);\n \tctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);\n \tctx->vnic_max_vnic_entries =\n@@ -5555,12 +5777,73 @@ int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)\n \tfor (i = 0; i < tqm_rings; i++, ctx_pg++)\n \t\tctx->tqm_mem[i] = ctx_pg;\n \n-\tbp->ctx = ctx;\n ctx_err:\n \tHWRM_UNLOCK();\n \treturn rc;\n }\n \n+int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt *bp,\n+\t\t\t\t\tstruct bnxt_ctx_mem *ctxm)\n+{\n+\tstruct hwrm_func_backing_store_cfg_v2_input req = {0};\n+\tstruct hwrm_func_backing_store_cfg_v2_output *resp =\n+\t\tbp->hwrm_cmd_resp_addr;\n+\tstruct bnxt_ctx_pg_info *ctx_pg;\n+\tint i, j, k;\n+\tuint32_t *p;\n+\tint rc = 0;\n+\tint w = 1;\n+\tint b = 1;\n+\n+\tif (!BNXT_PF(bp)) {\n+\t\tPMD_DRV_LOG(INFO,\n+\t\t\t \"Backing store config V2 can be issued on PF only\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tif (!(ctxm->flags & BNXT_CTX_MEM_TYPE_VALID) || !ctxm->pg_info)\n+\t\treturn 0;\n+\n+\tif (ctxm->instance_bmap)\n+\t\tb = ctxm->instance_bmap;\n+\n+\tw = hweight32(b);\n+\n+\tfor (i = 0, j = 0; i < w && rc == 0; i++) {\n+\t\tif (!(b & (1 << i)))\n+\t\t\tcontinue;\n+\n+\t\tHWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG_V2, BNXT_USE_CHIMP_MB);\n+\t\treq.type = rte_cpu_to_le_16(ctxm->type);\n+\t\treq.entry_size = rte_cpu_to_le_16(ctxm->entry_size);\n+\t\treq.subtype_valid_cnt = ctxm->split_entry_cnt;\n+\t\tfor (k = 0, p = &req.split_entry_0; k < ctxm->split_entry_cnt; k++)\n+\t\t\tp[k] = rte_cpu_to_le_32(ctxm->split[k]);\n+\n+\t\treq.instance = rte_cpu_to_le_16(i);\n+\t\tctx_pg = &ctxm->pg_info[j++];\n+\t\tif (!ctx_pg->entries)\n+\t\t\tgoto unlock;\n+\n+\t\treq.num_entries = rte_cpu_to_le_32(ctx_pg->entries);\n+\t\tbnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,\n+\t\t\t\t &req.page_size_pbl_level,\n+\t\t\t\t &req.page_dir);\n+\t\tPMD_DRV_LOG(DEBUG,\n+\t\t\t \"Backing store config V2 type:%s last %d, instance %d, hw %d\\n\",\n+\t\t\t bnxt_backing_store_types[req.type], ctxm->last, j, w);\n+\t\tif (ctxm->last && i == (w - 1))\n+\t\t\treq.flags =\n+\t\t\trte_cpu_to_le_32(BACKING_STORE_CFG_V2_IN_FLG_CFG_ALL_DONE);\n+\n+\t\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n+\t\tHWRM_CHECK_RESULT();\n+unlock:\n+\t\tHWRM_UNLOCK();\n+\t}\n+\treturn rc;\n+}\n+\n int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)\n {\n \tstruct hwrm_func_backing_store_cfg_input req = {0};\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h\nindex f9fa6cf73a..3d5194257b 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.h\n+++ b/drivers/net/bnxt/bnxt_hwrm.h\n@@ -60,6 +60,8 @@ struct hwrm_func_qstats_output;\n \tHWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK\n #define HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK \\\n \tHWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK\n+#define BACKING_STORE_CFG_V2_IN_FLG_CFG_ALL_DONE \\\n+\tHWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE\n \n #define HWRM_SPEC_CODE_1_8_4\t\t0x10804\n #define HWRM_SPEC_CODE_1_9_0\t\t0x10900\n@@ -355,4 +357,10 @@ void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index);\n int bnxt_alloc_hwrm_tx_ring(struct bnxt *bp, int queue_index);\n int bnxt_hwrm_config_host_mtu(struct bnxt *bp);\n int bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);\n+int bnxt_hwrm_func_backing_store_qcaps_v2(struct bnxt *bp);\n+int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt *bp,\n+\t\t\t\t\tstruct bnxt_ctx_mem *ctxm);\n+int bnxt_hwrm_func_backing_store_types_count(struct bnxt *bp);\n+int bnxt_hwrm_func_backing_store_ctx_alloc(struct bnxt *bp, uint16_t types);\n+int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp);\n #endif\ndiff --git a/drivers/net/bnxt/bnxt_util.c b/drivers/net/bnxt/bnxt_util.c\nindex 47dd5fa6ff..aa184496c2 100644\n--- a/drivers/net/bnxt/bnxt_util.c\n+++ b/drivers/net/bnxt/bnxt_util.c\n@@ -27,3 +27,13 @@ void bnxt_eth_hw_addr_random(uint8_t *mac_addr)\n \tmac_addr[1] = 0x0a;\n \tmac_addr[2] = 0xf7;\n }\n+\n+uint8_t hweight32(uint32_t word32)\n+{\n+\tuint32_t res = word32 - ((word32 >> 1) & 0x55555555);\n+\n+\tres = (res & 0x33333333) + ((res >> 2) & 0x33333333);\n+\tres = (res + (res >> 4)) & 0x0F0F0F0F;\n+\tres = res + (res >> 8);\n+\treturn (res + (res >> 16)) & 0x000000FF;\n+}\ndiff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h\nindex 7f5b4c160e..b265f5841b 100644\n--- a/drivers/net/bnxt/bnxt_util.h\n+++ b/drivers/net/bnxt/bnxt_util.h\n@@ -17,4 +17,5 @@\n \n int bnxt_check_zero_bytes(const uint8_t *bytes, int len);\n void bnxt_eth_hw_addr_random(uint8_t *mac_addr);\n+uint8_t hweight32(uint32_t word32);\n #endif /* _BNXT_UTIL_H_ */\n", "prefixes": [ "v3", "09/14" ] }